JPH05275992A - Phase difference measuring circuit system - Google Patents

Abstract

PURPOSE:To measure the phase difference without using a special element by logically discriminating whether the phase difference between two pulses is within a prescribed range or not. CONSTITUTION:Pulse signals (a) and (b) are inputted to clock inputs CK of flip flops (FF) 11 and 12 respectively, and the FF 11 is reset before the FF 12, and respective outputs Q are changed with the same time difference. When both outputs Q go to the high level together, an AND gate 13 outputs the signals in the high level to both reset inputs R to reset FFs 11 and 12. Therefore, a pulse signal having the same time width as the phase difference between two pulse signals appears as a signal (c), and a whisker pulse signal due to signal delay between elements appears as a signal (d). Signals (c) and (d) and signals obtained by delaying them by a prescribed time are inputted to logic circuits 4 and 5, and signals (e) to (j) are outputted after logical operation. Thus, it is logically discriminated whether the phase difference between two pulses is within the prescribed range or not.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a phase difference measuring circuit system for measuring the phase difference between the rising and falling edges of a signal between two pulses, and more particularly, the phase difference of a signal between two pulses is several tens of nanoseconds or less. The present invention relates to a phase difference measuring circuit system for the case of being close to.

[0002]

2. Description of the Related Art Conventionally, in the case where the phase difference between signals between two pulses is close to several tens of nanoseconds or less, to measure this phase difference, a period of time less than the phase difference to be measured is set as a cycle. The two pulse signals are punched out by the high-speed clock signal to obtain the phase difference, that is, the time difference.

[0003]

In this conventional phase difference measuring circuit system, in order to increase the resolution of the desired phase difference, it is necessary to increase the frequency and stability of the clock signal which is the unit of resolution. When a value of tens of nanoseconds or less is required, a clock frequency of tens of megahertz or higher is required. On the other hand, when considering a cheap and highly stable crystal oscillator used in ordinary electronic circuits as the clock source,
Even though the maximum oscillation frequency is a multiple of harmonics, at present, the limit is around 100 megahertz, and the operating speed of logic elements is generally TTL system or CMO.
Since the S-type element is currently limited to several tens of megahertz, the resolution of the phase difference between two pulses in the conventional method is limited to about several tens of nanoseconds, and is close to several tens of nanoseconds or less. There was a problem that the phase difference when there was no measurement.

[0004]

According to the phase difference measuring circuit system of the present invention, the phase difference between two pulses is compared with the phase of one pulse as a reference by using the rising or falling edge of the pulse signal as a trigger. Then, the pulse output means for outputting the result as a pulse having a time width corresponding to the phase difference to the phase lead terminal or the phase delay terminal, and having a plurality of intermediate tap outputs and having a prescribed signal transmission delay time between taps A delay time setting means for freely setting a delay time and a tap output of the delay time setting means are used to determine logically whether or not the phase difference between the two pulses is within a predetermined range. And means.

[0005]

DESCRIPTION OF THE PREFERRED EMBODIMENTS Next, the present invention will be described with reference to the drawings. FIG. 1 is a circuit diagram of an embodiment of the phase difference measuring circuit system of the present invention.

In FIG. 1, the phase difference measuring circuit comprises an edge trigger type phase comparator 1 composed of two flip-flops (FF) 11 and 12 and an AND gate 13, delay elements 2 and 3, and an AND circuit. Gates 43,44,4
AND the same as the logic circuit 4 configured by combining 5
The logic circuit 5 includes gates 53, 54 and 55.

Next, the operation of this circuit will be described. Two pulse signals whose phase difference is to be measured are input to terminals A and B. Here, assuming that the two pulse signals input to the terminals A and B are a and b, and the phase of the pulse signal a is the phase of the pulse signal b by focusing on either the rising or falling of the signal. Consider the case where you are more advanced.

The pulse signal a is the clock input C of the FF11.
The pulse signal b is input to the clock input CK of the FF12, the FF11 is set prior to the FF12, and the FF12 is subsequently set.
The output Q of 1 and the output Q of the FF 12 change with the same time difference. The AND gate 13 outputs a high level signal, which is the output result thereof, to the reset input R of both FFs 11 and 12 when the outputs Q of both FFs 11 and 12 become high level, and outputs both FFs 11 and 12 to each other. Reset.

Therefore, in this case, a pulse signal having the same time width as the phase difference between the two pulse signals appears in the signal c in FIG. 1, and a whisker-shaped pulse signal resulting from the signal delay between the elements appears in the signal d. If the delay elements 2 and 3 have the same specifications and the signal delay time between taps is t, in this circuit, the delay times t and 2
This means that t and 3t are set. The logic circuits 4 and 5 keep the signals c and d as they are, and further delay times t, 2t and 3t.
The signal delayed by only
f, g, h, i, j are output. Therefore, in this case, if the pulse width of the signal c, which is the phase difference between the pulse signals a and b, is set to T, the signals h, i, and j are all at the low level without any change, whereas when T> 3t. e, f, g are all high level, 2t <T <3t, signals f, g are high level and only signal e is low level, and t <T <2t, signals e, f are low level and only signal g is high level, When T <t, the signals e, f and g are all at low level. On the contrary, when the phase of the pulse signal a lags the phase of the pulse signal b, the pulse of the phase difference is output to the signal d and the pulse width is measured to the signals h, i, and j contrary to the above result. The result is output.

FIG. 2 is a block diagram showing an application example of the phase difference measuring circuit system of the present invention. A delay time control block 100 configured by a delay element 1001 having a plurality of intermediate taps and a selection circuit 1002 to control a delay time of a signal;
A phase-locked oscillator block 200 including a phase comparator 2001, a low-pass filter, a voltage-controlled oscillator 2003, and a frequency divider 2004, a delay element 300, a phase difference measuring circuit 400 according to the present invention, and an arithmetic processing circuit 500. ing.

The operation of this application example is a signal delay amount capable of controlling the phase error, which remains in the steady state between the pulse signal 1 and the pulse signal n generated in the phase locked oscillator block 200, to the original pulse signal k. Is added, the phase difference between the pulse signal n and the reference output signal o is measured by the phase difference measuring circuit 400, and the arithmetic processing circuit 500 controls the delay time control block so that the phase error does not exceed the specified range. A feedback signal is output to the selection circuit 1002 in 100. Here, the delay time of the delay element 300 is about half the value of the delay time that can be set by the delay time control block 100. Further, the phase-locked oscillation block 200 outputs an output clock signal m to be supplied to a device under it.

[0012]

As described above, according to the present invention, when the phase difference between the signals between the two pulses is close to several tens of nanoseconds or less, the rising or falling position of the signal between the two pulses is high. It has an effect that the phase difference can be measured without using a special element.

Further, by incorporating the phase difference measuring circuit according to the present invention together with the delay circuit in the structure of the phase locked oscillator circuit, it is possible to obtain the effect that the steady phase error generated in the phase locked oscillator circuit can be absorbed. .

[Brief description of drawings]

FIG. 1 is a circuit diagram of an embodiment of a phase difference measuring circuit system according to the present invention.

FIG. 2 is a block diagram showing an application example of a phase difference measuring circuit system of the present invention.

[Explanation of symbols]

1 Edge Trigger Type Phase Comparator 2, 3, 300, 1001 Delay Element 4, 5 Logic Circuit 11, 12 Flip Flop (FF) 13, 41, 42, 43, 51, 52, 53 AND
Gate 100 Delay time control block 200 Phase locked oscillation block 400 Phase difference measurement block 500 Operation processing circuit 1002 Selection circuit 2001 Phase comparator 2002 Low pass filter 2003 Voltage controlled oscillator a, b, k, l, n Pulse signal c, d, e , F, g, h, i, j output signal m output clock signal o reference output signal

Claims (1)

[Claims] 1. A rising or falling edge of a pulse signal is used as a trigger to compare the phase difference between two pulses with reference to the phase of one pulse, and the result is converted into a pulse having a time width corresponding to the phase difference. A pulse output means for outputting to a phase lead terminal or a phase delay terminal; a delay time setting means for freely setting the delay time of an input signal with a prescribed signal transmission delay time between taps having a plurality of intermediate tap outputs;
A phase difference measuring circuit comprising: a judgment unit that logically judges whether or not the phase difference between the two pulses falls within a predetermined range by using the tap output of the delay time setting unit. method.