JPS61105629A - Clock controlling system - Google Patents

Abstract

PURPOSE:To execute clock control at a high speed by using an operating speed detecting circuit for detecting a clock frequency by which a circuit element can be operated, and a clock by which a frequency can be varied, and driving a circuit by the highest clock frequency by which it can be operated stably. CONSTITUTION:An output of a ring oscillator circuit 11 is counted by a counter 12, and this count value and a frequency of a clock 13 are compared by a comparing circuit 14. By this comparison, an information signal for showing a variation of an operating environment based on a temperature rise or a voltage variation, etc., and a control signal for varying a frequency dividing ratio by frequency dividers 2, 6 in order to adjust to an optimum clock frequency are supplied from the comparing circuit 14. Also, a clock of a clock speed corresponding to the operating environment is supplied to a logical circuit 10 through a clock supplying circuit 9 from a clock speed variable circuit 8. In this way, an oscillation frequency of a variable frequency oscillator can be controlled to the highest frequency by which each circuit element can be operated stably, therefore, in various operating conditions, the processing performance is excellent, and also a digital device which is suitable for integration can be offered.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a clock control system in a device such as a digital computer that performs processing using a clock. The processing circuits in such devices are clocked from a specific basic oscillator via a clock supply circuit. The processing power of a computer largely depends on the speed of this clock. Therefore, it is desirable that the clock speed be faster. However, the clock speed is limited by the circuit configuration or circuit components. In addition, the operable clock frequency is constrained by fluctuations in power supply voltage, changes in ambient temperature, and the like. Therefore, it is necessary to use a clock that is not influenced by these conditions and can operate stably.

[Conventional technology]

Conventionally, in order to ensure the operation of computers and other equipment even in the face of fluctuations in power supply voltage, variations in elements, changes in ambient temperature, etc., the most stable operation can be obtained in the face of changes in these operating conditions. In this way, clock speeds are adapted to the slowest operating circuit elements. For this reason, the processing speed of the entire device is reduced, although it may be possible to operate with a faster clock depending on the operating conditions.

Furthermore, although it has been conventional practice to incorporate circuit components to compensate for fluctuations in power supply voltage or changes in ambient temperature, the circuits become complex and become an impediment to high integration.

[Problem that the invention seeks to solve]

The present invention was made in view of these problems in the conventional example, and it is possible to achieve the highest speed within the given conditions without adding circuit elements to each circuit to compensate for changes in power supply voltage or ambient temperature. This invention provides a clock control method that can use a clock.

[Means for Solving the Problems] According to the method according to the present invention, an operating speed detection circuit for detecting a clock frequency at which a circuit element can operate and a clock whose frequency can be changed are used, and the clock frequency can be changed stably. The circuit is driven at the highest clock frequency at which it can operate.

[Effect]

The operating speed detection circuit may be one that detects the power supply voltage, ambient salinity, etc. and generates a signal to change the clock speed, or it may use circuit elements that are actually used to detect circuitry due to changes in temperature, etc. Compare the change in behavior with the reference value,
A control signal for changing the clock frequency may be generated as a comparison output. The output frequency of a clock circuit formed by a PLL circuit or the like is made variable by the output of this operating speed detection circuit.

〔Example〕

Embodiments of the present invention will be described in detail below with reference to the drawings.

FIG. 1 is a block diagram of one embodiment of the present invention.

In FIG. 1, 1 is a fixed oscillator of, for example, 100 MHz, and the output of this fixed oscillator 1 is supplied to a first frequency divider 2 and a clock supply circuit 3.

The clock supply circuit 3 supplies a constant clock generated by a fixed oscillator to a timer 4 or a charging device (not shown). On the other hand, the frequency divider 2 divides the output of the fixed oscillator 1 by 100, and supplies the I MHzO frequency divided output to one input terminal of the phase-locked loop 5. Further, the output of the phase-locked loop 5 is frequency-divided by a second frequency divider 6 that divides the frequency by, for example, 99, and then is supplied to the other input terminal of the phase-locked loop 5. Therefore, the output frequency of the phase-locked loop 5 is locked to a frequency according to the division ratio of the frequency divider 2.6. The phase-locked loop 59 and frequency dividers 2 and 6 constitute a variable clock speed circuit 8 that operates in response to the output of an operating speed detection circuit 7, which will be described later. The output frequency of the variable clock speed circuit 8 varies from 50% to 1 depending on the frequency division ratio of the frequency dividers 2 and 6, whose frequency division ratio is finely set by the output of the operating speed detection circuit 7.
It changes by about 00%. Here, the output of the variable clock speed circuit 8 is used as an operating clock for the logic circuit 10 via a clock supply circuit 9. Note that the operating speed detection circuit 7 transmits the operating state status information to the logic circuit 1 as necessary.
It may be sent to 0. Further, the outputs of the clock supply circuits 3 and 9 may be taken in as necessary for the operation of the operating speed detection circuit 7.

Next, a second diagram showing the operating speed detection circuit 7 of FIG. 1 in further detail.
The functions of the operating speed detection circuit 7 will be explained with reference to the drawings.

As shown in FIG. 2, the operating speed detection circuit 7 includes a plurality of ring oscillator circuits 11 . A counter 12 for counting the output frequency of the ring oscillator circuit 11, a clock 13, and a comparison circuit 14 are included. The plurality of ring oscillator circuits 11 include a combination of gate circuits with different loads, as shown in FIG. It includes circuit elements such as gate circuits with different numbers of series connections.

The output of these ring oscillator circuits 11 is the counter 1
2, and this count value and the frequency of the clock 13 are compared in the comparison circuit 14.

Through this comparison, the comparator circuit 14 outputs an information signal indicating a change in the operating environment due to temperature rise or voltage change, etc., and divides it into the frequency dividers 2 and 6 in order to adjust the clock frequency to the optimum clock frequency according to the change in the operating environment. Provides a control signal to change the frequency ratio. Thus, a clock having a clock speed corresponding to the operating environment is supplied from the clock speed variable circuit 8 to the logic circuit 10 via the clock supply circuit 9. Such logic circuit 10 is a digital device under test, and in order to test whether it operates at the clock speed of the device, it is necessary to test it under various conditions such as system conditions and program types. In general, the clock speed that satisfies such conditions, that is, the fastest clock speed under optimal conditions (circular section in Figure 5 (operating range 1, recommended operating range))
If a digital device can be tested to ensure its successful operation, it is possible to successfully operate the device at a slower clock speed than that used for testing, even under adverse conditions. (See the rectangular part (operation range 2, ie, the operable range) in FIG. 5). Therefore, in actual operation, if the operating conditions become worse than those at the time of testing, if the device is operated at a slower clock speed corresponding to the worsened conditions, the normal operation of the digital device will be improved. can maintain normal operation.

Further, as shown in FIG. 3, the operating speed detection circuit 7 uses a J-K FF to which a variable clock is supplied.
Control and information signals may be obtained by comparing the outputs of FFs, or simply by detecting power supply voltage and measuring parameters that affect the operating clock, such as ambient temperature, and determining the optimal clock frequency according to changes in these parameters. The frequency divider 6 of the frequency dividers 2 and 6 may be controlled so as to generate . Fixed oscillator 1 oscillation frequency is 100MHz
When the frequency accuracy is 0.01%, an example of the rate of change in clock speed and the step of change is as follows.

Clock frequency variable ratio: 50% Clock frequency change per step: 0.01% Time required to change 1 step: 10 μS Time required to change clock frequency to maximum: 0 ms [Effects of the invention] As explained above. According to the present invention, the oscillation frequency of the variable frequency oscillator can be controlled to the highest frequency at which each circuit element can stably operate, thereby providing a digital device that has excellent processing performance under various operating conditions and is suitable for integration. Be as effective as possible.

[Brief explanation of drawings]

FIG. 1 is a block diagram of one embodiment of the present invention, and FIG. 2 is a block diagram of an embodiment of the present invention.
3 is a block diagram of another embodiment of the operating speed detection circuit according to the present invention, and FIG. 4 is a gate circuit included in the detection circuit shown in FIG. 2. The circuit diagram of FIG. 5 is a diagram showing the operating range. In the figure, 1 is a fixed oscillator, 2 and 6 are frequency dividers, 3.9 is a clock supply circuit, 5 is a phase-locked loop, 7 is an operating speed detection circuit, and 8 is a variable clock speed circuit. Figure 1 Figure 2

Claims (3)

[Claims] (1) A clock control method for controlling the clock frequency of a digital device such as a digital computer, which includes a clock speed variable circuit and an operating speed detection circuit for detecting a clock speed at which a circuit element can operate; A clock control method characterized by controlling the clock speed using the output of an operating speed detection circuit and operating a digital device at the optimal clock speed. (2) In response to the output of the operating speed detection circuit, when testing the digital device, the digital device is tested at the fastest clock speed under optimal conditions, and the output indicates deterioration of conditions during actual operation. A clock control system as claimed in claim 1, characterized in that the digital device is operated at a slow clock speed in response. (3) The clock control method according to claim 1 or 2, wherein the variable clock speed circuit includes a frequency divider whose frequency division ratio can be changed and a phase-locked loop.