JPH1090370A - Ic circuit with pulse generation function and lsi testing apparatus using it - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a new pulse generation function which reduces a change in a power-supply voltage caused by a change in a current. SOLUTION: An LSI testing apparatus is provided with a pulse generation circuit 2 which generates desired pulses and with a current consumption circuit 5 which consumes a prescribed current as required. The consumed current of the pulse generation circuit 2 and the consumed current of the current consumption circuit 5 are controlled in such a way that their sum becomes a prescribed range. When the consumed current of a circuit as a whole containing the pulse generation circuit 2 and the current consumption circuit 5 is set within a permissible range in this manner, a change in a current within a unit time is reduced, a change in a power-supply voltage can be suppressed, and the generation accuracy of the desired pulses can be achieved.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

[0001] 1. Field of the Invention [0002] The present invention relates to an IC circuit having a pulse generation function and an LSI test apparatus using the same.

[0002]

2. Description of the Related Art In an LSI test apparatus for testing a semiconductor device, a pulse generation circuit, more specifically, an IC circuit with a pulse generation function is used to generate a test waveform.

FIG. 11 shows a conventional pulse generating circuit.

The pulse generation circuit shown in FIG. 11 includes a clock counting circuit 21, a delay circuit 22, and a data operation circuit 23.

The data operation circuit 23 supplies the delay amount data CT and D to the clock counting circuit 21 and the delay circuit 22, respectively.
Is output.

The clock counting circuit 21 outputs the delay amount data CT
, A delay of an integral multiple of the master clock is realized.

The delay circuit 22 realizes a delay equal to or shorter than the master clock based on the delay amount data D.

The count clock 21-1 output from the clock count circuit 21 is also used as a clock for internal operation of the data operation circuit.

Next, the operation of the pulse generation circuit of FIG. 11 will be described with reference to FIGS.

FIG. 12 shows an example in which the delay amount data is 0.

When the master clock 6 as shown in FIG. 12 is input, the delay amount data given by the data operation circuit 23 to the clock counting circuit 21 and the delay circuit 22 is (CT
(0), D (0)), the output pulse is output after being delayed by the propagation delay time (Tpd1 + Tpd2) required from the input of the master clock to the generation of the output pulse.

This propagation delay time is a clock transit time that causes the pulse generator to delay the time data to be set to 0, and is hereinafter referred to as an offset delay time.

Next, FIG. 13 shows that the delay amount data is (CT
(1), D (0.5)).

When the master clock 6 as shown in FIG. 13 is input, first, the clock counting circuit 21 counts the master clock 6 by one based on the delay amount data CT (1) given from the data operation circuit 23. Delay for minutes.

Next, in the delay circuit, the data operation circuit 23
Based on the delay amount data D (0.5) given by, the pulse delayed by one count in the clock counting circuit is further delayed by 周期 cycle of the master clock 6. Therefore, the delay time from the reference time is Tpd1 + CT
(1) + Tpd2 + D (0.5)

Now, such a pulse generating circuit is called a CM
In the case of a semiconductor device in which a switching current flows each time an internal logic transition such as an OSLSI transitions,
The power supply voltage fluctuates significantly, the signal propagation delay time of the internal circuit of the pulse generation circuit fluctuates, and the pulse generation accuracy deteriorates.

For example, the overall circuit scale of the pulse generation circuit shown in FIG.
9. If the ratio of the clock counting circuit 21 is set to 0.1 and only the clock counting circuit 21 is designed to always operate,
Assuming that the operating circuit scale is proportional to the amount of current consumption, by generating a desired coefficient clock (by transitioning the internal logic), the current consumption of the entire pulse generation circuit goes from 0.1 to 1. And the pulse generation accuracy is degraded. That is, the power supply pin (V
When a transient current (Δi / Δt) flows through the L component (inductance) between the CC) and the ground pin (GND), an inductive voltage ΔV (= −LΔi / Δt) is generated, and the pulse generation accuracy Deteriorates. Note that this voltage ΔV
Is caused by a delay in response to a current supply from a DC power supply or the like, and a considerable difference occurs in a situation where an LSI is mounted.

FIG. 14A shows, as an example, a power supply voltage fluctuation between VCC and GND immediately after the count clock is generated by the pulse generation circuit. This is an example in which the data operation circuits 23 are operated at the same time to generate the count clock. It can be seen from this that a current transiently flows between VCC and GND, and the power supply voltage VCC fluctuates.

As a method of reducing the fluctuation of the power supply voltage, as shown in FIG. 15, a capacitor 1 is connected between the power supply and GND.
6 (hereinafter abbreviated as "pass capacitor") to suppress a transient current change of the power supply voltage.

[0020]

However, the decap 16
Is effective in reducing the integral component of power supply voltage fluctuations, but it is difficult to reduce power supply voltage fluctuations that exceed the frequency response of the capacitor. That is, in the decap 16, since the electric charge is charged by the decap after the current change occurs, the power supply voltage cannot be brought into a steady state at a speed higher than the charge speed.

FIG. 14B shows an example of a power supply voltage waveform when the decap is mounted and when it is not mounted.

As can be seen from the figure, since the decap 16 cannot reduce the power supply voltage fluctuation in a time zone higher than its frequency response, the pulse generation accuracy of the pulse generation circuit in that time zone has not been improved. That is, the power supply voltage fluctuates only during the time for charging the electric charge by the bypass capacitor 16.

Further, the operating speed of recent semiconductor devices tends to increase more and more, and high-precision pulses cannot be supplied to such semiconductor devices only with the current decaps alone. As a result, reliable test results cannot be obtained.

It is an object of the present invention to provide a new pulse generating function for reducing the fluctuation of the power supply voltage caused by the current change.

It is another object of the present invention to provide a highly reliable LSI test apparatus using the above-described pulse generation function.

[0026]

According to the present invention, there is provided a pulse generating circuit for generating a desired pulse, and a current consuming circuit for consuming a predetermined current as required. The above object is achieved by controlling the sum of the current consumption of the current consuming circuit and the current consumption in a predetermined range.

If the current consumption of the entire circuit including the pulse generating circuit and the current consuming circuit is within the allowable range, the current change per unit time is reduced, and the fluctuation of the power supply voltage is suppressed. can do. That is, it is possible to achieve desired pulse generation accuracy.

For example, when the propagation delay time of a desired semiconductor device changes at a rate of change b per unit voltage, the error time (Terr) of the pulse generation of the output pulse from the pulse generation circuit is: Terr = Propagation delay time when the output pulse passes through the LSI × b × variation voltage. Here, the above-mentioned Terr should originally indicate the time during which the power supply voltage fluctuates in an extremely short time zone, but varies depending on various conditions such as the circuit configuration of the pulse generation circuit and the cycle of the input master clock. Therefore, here, it is set to b for convenience.

Therefore, since the fluctuating propagation delay time changes according to the fluctuating voltage of the power supply voltage (fluctuation of the current flowing between the power supply pin and GND), the pulse generation accuracy of the pulse generation circuit is set to ± a second or less. Then, the variation voltage of the power supply voltage <a / (propagation delay time through which output pulse passes xb). The pulse generation accuracy of the pulse generation circuit is n-th and n
There is a case where it is guaranteed at the (+1) th pulse generation interval, and a case where it is determined by generating the nth pulse within a required time within a required time from a predetermined reference time (reference clock). The arithmetic expression is an example in which the accuracy of the pulse generation circuit is set within ± a seconds in the latter case.

Further, according to the present invention, the sum of the current consumption of the pulse generation circuit and the current consumption of the current consumption circuit falls within a predetermined range with respect to a period including a period before and after the pulse is generated. It is preferable to control. By operating the current consuming circuit for a necessary cycle in this manner, power consumption of the entire circuit can be reduced.

Further, the present invention provides a data calculating means for generating a pulse generated at a desired cycle or a pulse delayed by a desired time from a reference signal, and a master clock of a master clock based on the first data from the data calculating means. Synchronized with a master clock constituted by clock counting means for counting an integral multiple and generating a pulse after the counting is completed, and pulse delay means for generating a delay amount equal to or less than the master clock cycle by the second data from the data arithmetic means. In the pulse generation circuit that operates in the following manner, the change in the rate at which the circuit of the internal logic realization means of the pulse generation means operates (hereinafter, the change in the rate at which the circuit operates is referred to as the operation rate) varies from coarse to fine First detection means for detecting in advance, and detecting in advance that the change in the operation rate of the internal logic realization means of the pulse generation means changes from dense to coarse. A second detecting means, and a current consuming means for consuming a predetermined current based on the detection signal of the first detecting means or the second detecting means, wherein the detecting signal from the second detecting means The above object can also be achieved by operating the current consuming means based on the detection signal from the first detecting means and stopping the current consuming means based on the detection signal from the first detecting means.

Alternatively, data calculation means for generating a pulse generated at a desired cycle or a pulse delayed by a desired time from a reference signal, and counting an integral multiple of the master clock by the first data from the data calculation means A clock counting means for generating a pulse after the counting is completed, and a pulse operating in synchronization with a master clock constituted by pulse delay means for generating a delay amount equal to or less than the master clock cycle by the second data from the data calculating means. In the generating circuit, detecting means for detecting a period other than the master clock period at which the count end signal of the clock counting means is output, and logical product of the output of the detecting means and the master clock or a clock having a desired generation period. Clock generating means for generating a taken output, and current consuming means operated by the clock generating means. It is possible to achieve the above object by causing.

The first detecting means may detect that the change in the operation rate of the internal logic realizing means of the pulse generating means changes from coarse to fine, by a first set time from a previously stored pulse generating time. Based on the pulse generation time stored in advance that the change in the operation rate of the internal logic realization means of the pulse generation means changes from fine to coarse. The detection may be performed based on time.

Further, the first detecting means detects that the change of the operation rate of the internal logic realizing means of the pulse generating means changes from coarse to fine, from the previously stored pulse generating times based on the first and third pulse generating times. The second detection means detects that the change in the operation rate of the internal logic realization means of the pulse generation means changes from dense to coarse, from the previously stored pulse generation time to the second detection means. The current consuming means may be operated / stopped in multiple stages by detecting based on the second and fourth set times.

As described above, the pulse generating circuit operates in multiple stages /
This is because if stopped, the current consuming means can be operated for a necessary period, which leads to low power consumption.

Further, a plurality of the current consuming means are provided,
The operation / stop cycle of the plurality of current consuming units may be different. If a plurality of current consuming means are used,
This is because the current consumption rate per unit time when the current consuming means is operated can be reduced.

On the other hand, if such a pulse generation circuit is applied to an LSI test apparatus, a highly accurate test pattern can be generated, and a highly reliable LSI test can be realized.

[0038]

DESCRIPTION OF THE PREFERRED EMBODIMENTS The present invention will be described below in detail with reference to the drawings.

FIG. 1 shows an embodiment of the present invention, in which a data operation circuit 23 for calculating the generation time of an output pulse and the output data CT from the data operation circuit 23 count the master clock 6 to determine a predetermined time. A clock counting circuit 21 for passing a master clock at the time of counting, a pulse generating circuit 2 comprising a delay circuit for outputting a pulse by delaying a predetermined value of data D from an output clock of the clock counting circuit 21; An operation rate detection circuit 4 for detecting an operation rate of the pulse generation circuit 2 based on the data from 23 (the operation rate is a ratio of a circuit performing a switching operation to the entire circuit); And a current consumption circuit 5 for consuming current.

In such a configuration, the operation detecting circuit 4
Detects the operation rate of the pulse generation circuit 2 and operates the current consumption circuit 5 that consumes current according to the detection result, thereby limiting the transient current generated in the entire LSI 1 including the pulse generation circuit to a predetermined range. To reduce the potential fluctuation.

FIG. 2 shows the operating state of the LSI 1, in which the horizontal axis represents time, and the vertical axis represents current consumption values and power supply voltage values of the pulse generation circuit 2 and the transient current reduction circuit 3.

In the circuit shown in FIG. 1, the current consumption in the transient current reduction circuit 3 and the current consumption in the pulse generation circuit 2 are controlled to have completely opposite characteristics as shown in FIG. The current change value (VCC · GN of the LSI) of the entire LSI 1 including the pulse generation circuit 2 and the transient current reduction circuit 3
The current value flowing between D) is substantially constant, as shown in FIG.

As described above, it can be seen that if the current value changing in the entire circuit is constant, that is, if there is no abrupt current change, the power supply voltage fluctuation due to it is reduced as shown in FIG.

Note that the allowable power supply voltage fluctuation range in the figure is set so that the pulse generation accuracy is always ± a second or less.

Next, an example of the transient current reducing circuit 3 will be described with reference to FIGS.

FIG. 3 shows a pulse generation circuit 2 and a change in internal operation rate occurring when the pulse is generated is calculated from the data A23-2 which is a pulse output time, and an operation rate detection for outputting an operation signal to the current consuming circuit 5 is shown. Circuit 4. This is a circuit that controls the operation / stop of the current consumption circuit in accordance with the operation / stop of the pulse generation circuit 2 to make the current consumption of the entire circuit substantially constant.

The pulse generation circuit 2 outputs a time data (delay amount data) for generating a pulse by performing a calculation process, a clock counting circuit 21 for delaying based on the time data, and a clock for the clock. Counting circuit 2
The delay circuit 22 delays the output pulse from 1 by the data D of the data operation circuit 23 (a delay amount equal to or less than the master clock cycle).

The configuration of the clock counting circuit 21 is as follows.

The counter 211 that outputs the data counted by the master clock 6, the FF 212 that latches the data (CT, D) 23-1 from the data operation circuit, and the output data of the counter 211 are compared with the output data. A coincidence detector 213 that outputs a coincidence signal H only when there is a coincidence, an FF 214 that latches a signal from the 213, and an AND 215 that passes the master clock 6 next to the latched timing.

Next, the operation rate detection circuit 4 includes a current consumption circuit 5
Signal generation circuit A41 which outputs a stop signal for stopping the operation
And a signal generation circuit B42 that outputs a start signal for starting the current consumption circuit 5, and a consumption clock generation circuit 43 that selectively outputs the above-described stop signal and start signal to the current consumption circuit 5.

The signal generation circuit A41 includes a register 411 in which a predetermined value is written, an adder 412 for adding the data A23-2 from the data operation circuit and the output data of the register 411, and an FF 413 for latching the output. A match detector 414 that compares the output with the output of the counter 211 and outputs a match signal H only when they match, an FF 415 that latches the output on the opposite phase side of the master clock,
A that passes the master clock when the output of the FF is H
ND 416.

Similarly, the signal generation circuit B42 loads the register 421 in which a predetermined value has been written and the value of the 421 register when the coincidence detector 213 outputs H, and counts down the value to indicate TC ( Terminal count 42
A down counter 422 for outputting 2-1) and an AND 423 for passing the master clock 6 by its TC.

Finally, the consumption clock generation circuit 43 resets the output of the AND signal 416 as a stop signal and sets the FF 431 of the output signal of the AND signal 423 as a start signal.
And an AND 432 that allows the master clock to pass through the output of the FF 431.

With such a circuit configuration, the operation detection circuit 4 detects the internal operation rate of the pulse generation circuit 2 and controls the operation / stop of the current consumption circuit 5 based on the detection result.

The control operation will be described with reference to FIG.

FIG. 4 shows the operation timing of each section of the circuit shown in FIG.

First, the master clock 6 continuously generates pulses at the timing shown in the figure. Counter 21
1 counts the pulses of the master clock 6. For example, counting is performed as 0, 1, 2, 3,.... At this time, the timing data 23-1 and 23-2 are output from the data operation circuit 23 in synchronization with the divided clock. In this embodiment, 7, B, F-- are sequentially output as delay amount data (timing data).

The FF 212 sequentially latches its outputs 2, 7, B--.

The coincidence detector 213 outputs only a cycle in which the output of the counter 211 coincides with the output of the FF 212 that has latched the output of the data operation circuit (not shown).

The cycle output in this manner corresponds to FF2
After being latched at 14, it is output as a count clock 21-1 via AND 215.

That is, the pulse generation circuit 2 of the present embodiment
Outputs the next pulse of the master clock that matches the timing data as the count clock 21-1 according to the timing data output from the data operation circuit 23.

Next, the operation of the operation rate detection circuit 4 is as follows.

The timing data from the data operation circuit is sent to the adder 412 to the signal generation circuit A provided in the operation detection circuit 4 in the same manner as the pulse generation circuit.

The stored value −1 is stored in the register 411 and sent to the adder 412.

The adder 412 outputs the timing data A
23−2 and the added value 6, E, of the stored value −1 of the register 411
−−− are sequentially calculated.

The operation results 1, 6, A-- are FF4
13 and is input to the coincidence detector 414.

The value of the counter 211 provided in the pulse generating circuit is also input to the coincidence detector 414, and only the cycle in which each data coincides is output (not shown).

The cycle output in this manner corresponds to FF4
After being latched at 15, it is output as a stop signal 416 via AND 416.

That is, in this embodiment, the register 41
Since -1 is stored in 1, the pulse generation timing of the stop signal, which is the output of the signal generator A, is 1 more than the pulse generation timing of the pulse generation circuit (clock counting circuit).
A stop signal is output earlier by the clock.

Similarly, the signal generation circuit B includes a register 42
The stored value 2 stored in 1 is input to the counter 422.

The output data B 213 of the coincidence detector 213 of the pulse generation circuit is also input to the counter 422, and when the value is H, the value stored in the register 421 is loaded and subtracted according to the master clock 6 to become 0. TC4 at the time
22-1 is output.

The AND circuit 423 outputs a logical product of the signal from the TC and the signal from the master clock as a start signal.

That is, the signal generation circuit B outputs a start signal two clocks later stored in the register 421 from the timing at which the pulse generation circuit generates a pulse.

The consumption clock generation circuit 43 outputs the master clock as the operation clock while the output of the FF 431 by the stop / start signal is H, and operates the current consumption circuit 5.

In the above operation procedure, the current consumption circuit 5 supplies a current to the portion where the operation rate of the pulse generation circuit 2 is low, and the current consumption circuit 5 is operated a predetermined time before the pulse generation circuit 2 operates (generates a clock). Is stopped (corresponding to the transient current reduction circuit operation stop line in FIG. 2A), and when the operation of the pulse generation circuit 2 is completed (current consumption is reduced), the current consumption circuit is operated again (FIG. 2 (a) (corresponding to the transient current reduction circuit operation start line), the power consumption voltage fluctuation of the LSI can be reduced by reducing the current consumption value per unit time of the entire LSI.

That is, in the present invention, the power supply voltage fluctuation is suppressed by reducing the current change value per unit time generated at the time of pulse generation (operation) of the conventional pulse generation circuit. The current consumption circuit of the entire circuit shown in FIG. 3 can be kept substantially constant by operating the current consumption circuit when the pulse generation circuit is stopped and stopping the current consumption circuit when the pulse generation circuit is operating. The consumption rate can be reduced.

The values stored in the registers 411 and 421 may be set in advance to minimize the fluctuation of the power supply voltage from the characteristics of the current consumption of the pulse generation circuit.

In the present embodiment, the clock counting circuit and the signal generation circuit A have almost the same configuration or the same configuration.
Can have substantially the same propagation delay, and the control of the entire circuit becomes highly accurate.

Next, another embodiment of the present invention will be described with reference to FIGS.
This will be described with reference to FIG.

FIG. 5 shows an operation rate detection circuit 8 in place of the operation rate detection circuit 4 shown in FIG. The operation rate detection circuit 8 receives the input of the master clock 6 and the inverted output of the FF214.
It is composed of a D circuit 82. That is, the operation rate detection circuit 8 uses the data B21-3 sent from the FF 214 as a change point of the operation rate.

In the present embodiment, since the operation clock for operating current consumption circuit 5 is generated in the period of master clock 6 in which no count clock is generated, current consumption circuit 5
Is preferably configured to have current consumption characteristics substantially equal to those of the pulse generation circuit 2. Thereby, the power supply fluctuation is stabilized by always supplying a current to the entire circuit in synchronization with the master clock 6.

That is, in the present embodiment, a current consumption circuit having the same current consumption as that of the pulse generation circuit is provided in the master clock cycle in which the pulse generation circuit does not generate a pulse, thereby stabilizing the entire current value. , The power supply voltage fluctuation of the LSI is reduced.

The operation of the circuit shown in FIG. 5 will be briefly described with reference to FIG.

In FIG. 6, a master clock 6, a counter 211, timing data 23-1, a coincidence detector 213,
The operations of the FF 214 and the count clock 21-1 are the same as those in FIG.

A signal obtained by inverting the pulse of the FF 214 indicating the operation timing of the pulse generation circuit is input to the operation detection circuit 8 as an inverter 81.

The AND 82 performs an AND operation on the master clock 6 and the inverter signal, and outputs the result as an operation clock 82.

The consumption circuit 5 operates / stops based on this output.

That is, when the pulse generation circuit is outputting a pulse, the current consumption circuit is controlled to stop, and when the pulse generation circuit is not outputting a pulse, the current consumption circuit is controlled to operate. For example, the current consumption rate per master clock cycle can be reduced, and power supply voltage fluctuation can be reduced.

Further, since a circuit such as a register is not required as compared with FIG. 3, it is suitable for downsizing.

Next, another embodiment of the present invention will be described with reference to FIGS.
This will be described with reference to FIG.

FIG. 7 shows an operation rate detection circuit 9 in which the operation rate detection circuit 4 of the embodiment of FIG. 3 is replaced by two signal generation circuits A41 and B42 shown in FIG. It is.

Signal generation circuit A95 stores a value stored in a register
3. Since 1 is set in the signal generation circuit B97, a start signal is generated three cycles before and one cycle after the count clock 21-1 of the pulse generation circuit 2 is output.

Similarly, since the stored value -1 is set in the signal generating circuit A94, the register is set to 3, and the signal generating circuit B96 is set to 3, the count clock 21-1 of the pulse generating circuit 2 is output.
A start signal is generated before and after three cycles.

Since the generated stop / start signals are input to the current consuming circuit via the consuming clock generating circuit, first, the current is generated three cycles before the counting clock 21-1 of the pulse generating circuit 2 is output. The consumption circuit is operated and stopped one cycle before.

Next, the counting clock 21 of the pulse generation circuit 2
The current consuming circuit 5 is operated one cycle after the output of −1, and the current consuming circuit 5 is stopped after three cycles.

That is, the count clock 2 of the pulse generation circuit 2
The current consuming circuit is operated only for a certain period immediately before and immediately after 1-1 is output.

Since the present invention aims at improving the pulse generation accuracy, it is sufficient that the current value that changes per unit time during pulse generation is small.

Therefore, it is sufficient to make the current value changing during a predetermined time immediately before and immediately after the pulse generation period constant as in this embodiment, and conversely, in the other periods, the current consumption circuit is not used. Not operating it leads to lower power consumption in the entire circuit.

Note that the configurations of the pulse generating circuit 2 and the current consuming circuit are the same as those in FIG.

Next, the operation of the operation detection circuit 9 shown in FIG. 7 will be described with reference to FIG. The basic operations of the pulse generation circuit 2 and the signal generation circuits A and B are the same as those in FIG.

As shown in FIG. 8, there are two signal generating circuits A and B for generating a stop signal and a start signal, respectively, which output signals in accordance with stored values stored therein.
The current consumption circuit is operated immediately before and immediately after the operation of the pulse generation circuit, and the current consumption circuit is stopped except immediately before and immediately after the operation.

The principle of the duty ratio detecting circuit for operating the current consuming circuit immediately before and immediately after the operation of the pulse generating circuit will be described with reference to FIG.

FIG. 9A shows the current consumption of the pulse generation circuit 2 and the current consumption of the transient current reduction circuit 3.
As shown in (a), the stabilization circuit is operated immediately before and immediately after the operation of the pulse generation circuit. In this case, the current consumption of the current consumption circuit is about half that of the pulse generation circuit.

The current consumption value of the entire LSI obtained by adding the current amounts of these two circuits is (b), and the current consumption value of the one which operates only the pulse generation circuit changes by Δi / Δt. It can be seen that in the case of operating at the same time, the rate of change of the current is reduced to about half since the rate of change is Δi / Δt2.

In this embodiment, as shown in FIG. 9 (C), by allowing a power supply voltage fluctuation in which the pulse generation accuracy does not exceed ± a seconds or more, the current generation circuit is not always operated but the pulse generation circuit is not operated. 2 operates immediately before and immediately after the output of the count clock, thereby reducing a sudden current change.

That is, if this embodiment is used, power consumption can be reduced particularly when the pulse generation circuit operates in a long cycle.

Next, another embodiment of the present invention will be described with reference to FIG.

FIG. 10 shows an embodiment of a consumed clock generation circuit and a current consumption circuit. The configuration is as follows.

The consumption clock generation circuit receives an input of a start signal / stop signal from an operation rate detection circuit (not shown).
F101, a shift register for shifting its output signal every master clock cycle, and AND groups 103, 104, 105, provided corresponding to the output of the shift register.
And the corresponding current consumption circuit groups 111, 112, 1
13.

This circuit uses the shift register 102
The start signal / stop signal output from the FF 101 is output as a signal that is shifted every master clock cycle.

Since the current consumption circuit group 11 starts and stops operating in response to the output of the shift register, it is possible to gradually increase or decrease the current change of the current consumption circuit every master clock cycle.

Therefore, in the present embodiment, when the pulse generation circuit becomes large-scale and the current consumption circuit becomes large-scale, the effect of reducing the transient current of the pulse generation circuit and the voltage due to the transient current of the current consumption circuit itself are obtained. Fluctuation can be prevented.

That is, since the current consumption circuit group is gradually operated, the current value that changes when the current consumption circuit itself operates can be reduced.

It is needless to say that this embodiment can be combined with the embodiment described above.

Further, a decoupling capacitor may be inserted between VSS and GND outside the LSI to reduce the fluctuation of the power supply voltage in combination with the above embodiments.

FIG. 16 shows a power supply voltage variation when a bypass capacitor is used in combination with the circuits shown in FIGS.

In the operation mode shown in FIG.
FIG. 9 shows output pulses of the pulse generation circuit when operating at a cycle of 96 ns and power supply voltage fluctuations at that time.

FIG. 16A shows the power supply voltage fluctuation only in the decaps. The power supply voltage fluctuation when a pulse is output is about 20 mV in pp (Peak to Peak). ) Is a power supply voltage waveform when the ballast circuit is operated, and can be reduced to about 10 mV or less in pp.

In addition, when combined in this manner, the transient current can be reduced, and the number of mounted large-capacity decaps with good high-frequency characteristics can be reduced.

The embodiment of the present invention described so far can be easily applied to a circuit such as a timing generator of an LSI test apparatus using a plurality of high-precision pulse generating circuits.

This can be achieved by using any one of the embodiments of the present invention and providing the transient current consuming circuit in each of the timing generating circuits for each pin of the LSI test apparatus.

Next, a sixth embodiment will be described with reference to FIGS.

This embodiment is the same as the embodiment described with reference to FIG. 10 except that shift register 102 and AND1
As shown in FIG.
6. The delay circuit group 107 was used.

The AND 106 outputs the master clock to the FF 10
1 is passed as a gate signal, and the output is further delayed by a delay circuit 107 to provide the current consumption circuit 11 with the signal further delayed.

At this time, the delay circuit group 107 operates the current consuming circuit from an arbitrary set timing by delaying a desired delay time.

The delay circuit group 107 is connected in order as shown in the figure to individually control the operation start time of the current consuming circuits 111 to 113.

The delay time of the delay circuit group 107 can be easily changed by using a delay amount setting means (not shown) such as a register.

FIG. 18 shows another example of the configuration of the current consumption circuit group.

The current consuming circuit 114 does not simply consume a current by operating a fixed number of circuits with a signal from the consuming clock generating circuit as in the current consuming circuits 111 to 113 described above. A means 114a is provided to adjust the amount of current consumed in one current consuming circuit.

For example, using a setting register for the operation circuit setting means 114a, the logical value H is applied to the ANDs 114b and 114c.
Alternatively, a desired current consumption is set by changing the number of operating circuits by giving L.

This embodiment describes that the rate of change in the amount of current flowing through the transient current prevention circuit when the operation is started or stopped is controlled by the consumption clock generation circuit or the current consumption circuit. Therefore, if the LSI 1 can prevent transient current as a whole, FIG.
The invention is not limited to the circuit configuration of FIG.

Next, another embodiment of the present invention will be described.
This will be described with reference to FIG.

FIG. 19 is a diagram in which the DC power supply 12 is connected to the LSI 1 and, at that time, the LSI 1 operates to generate a current Ilsi.

The current Ilsi changes by a change in the circuit operating rate of the LSI, causing a current fluctuation of ΔIlsi.
A noise voltage of ΔV = −2L · ΔIlsi / Δt is generated between the current pins of I1, and radiation noise (EMI) is generated. Here, L is an inductance component between the LSI 1 and the DC power supply 12, and the inductance components L on the VCC side and the GND side in this example are the same. It should be noted that ΔIlsi / Δt indicates a transient current change.

However, L using the above-described embodiment will be described.
If the SI is mounted on a printed circuit board, etc., L · ΔIlsi / Δ
Even if radiation noise (EMI) caused by t occurs, the voltage fluctuation (noise voltage) ΔV between VCC and GND can be reduced, so that the radiation noise (EMI) can be reduced.

[0136]

According to the present invention, a sudden change in the amount of current can be reduced by starting or stopping the current consumption circuit before and after the operation cycle of the pulse generation circuit changes. It is possible to reduce the power supply voltage fluctuation that occurs.

In particular, according to the present invention, in a circuit requiring a high precision in the generation time of an output signal, such as a high-precision pulse generation circuit, fluctuations in the internal propagation delay time due to fluctuations in the power supply voltage are greatly reduced. it can.

Further, according to the present invention, the EMC (Electromagnetic compatibility) countermeasures can be implemented by reducing the noise voltage caused by the current fluctuation occurring between the power supply grounds of the circuit due to the change in the ratio of the operating circuits. It becomes possible.

[Brief description of the drawings]

FIG. 1 is a diagram showing a first embodiment of the present invention.

FIG. 2 is a diagram showing a first embodiment of the present invention.

FIG. 3 is a diagram showing a detailed example of Embodiment 1 of the present invention.

FIG. 4 is a diagram showing an operation of a detailed example according to the first embodiment of the present invention;

FIG. 5 is a diagram showing a second embodiment of the present invention.

FIG. 6 is a diagram showing an operation according to the second embodiment of the present invention.

FIG. 7 is a diagram showing a third embodiment of the present invention.

FIG. 8 is a diagram showing an operation of the third embodiment of the present invention.

FIG. 9 is a diagram showing the principle of Embodiment 3 of the present invention.

FIG. 10 is a diagram showing a fourth embodiment of the present invention.

FIG. 11 is a diagram showing a conventional technique.

FIG. 12 is a diagram showing a conventional technique.

FIG. 13 is a diagram showing a conventional technique.

FIG. 14 is a diagram showing a conventional technique.

FIG. 15 is a diagram showing a conventional technique.

FIG. 16 is a photograph of an oscilloscope waveform showing the effect of the present invention.

FIG. 17 shows a fifth embodiment of the present invention.

FIG. 18 is a diagram showing a fifth embodiment of the present invention.

FIG. 19 illustrates an effect of the present invention.

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 1 ... LSI 2 ... Pulse generation circuit 3 ... Transient current reduction circuit 4 ... Operation rate detection circuit 5 ... Current consumption circuit 6 ... Master clock 7 ... Pulse output pin 21 ... Clock counting circuit 22 ... Delay circuit 23 ... Data calculation circuit 41 ... Signal generation circuit A 42 ... Signal generation circuit B 211 ... Counter 212 ... FF 213 ... Primary detector 215 ... Adder

Claims (16)

[Claims] 1. A data calculating means for generating a pulse generated at a desired cycle or a pulse delayed by a desired time from a reference signal, and counting an integral multiple of a master clock by the first data from the data calculating means. A clock counting means for generating a pulse after the counting is completed, and a pulse operating in synchronization with a master clock constituted by pulse delay means for generating a delay amount equal to or less than the master clock cycle by the second data from the data calculating means. In an IC circuit with a generating function, a first detecting means for detecting in advance that a change in an operation rate of an internal logic realizing means of the pulse generating means changes from coarse to fine, and an internal logical realizing means of the pulse generating means. A second detecting means for detecting in advance that the change in the operation rate changes from dense to coarse, and based on a detection signal of the first detecting means or the second detecting means. Current consumption means for consuming a predetermined current, operating the current consumption means based on a detection signal from the second detection means, and controlling the current consumption based on a detection signal from the first detection means. An IC circuit with a pulse generation function, characterized by stopping consumption means. 2. A data calculation means for generating a pulse generated at a desired cycle or a pulse delayed by a desired time from a reference signal, and counting an integral multiple of a master clock by the first data from the data calculation means. A clock counting means for generating a pulse after the counting is completed, and a pulse operating in synchronization with a master clock constituted by pulse delay means for generating a delay amount equal to or less than the master clock cycle by the second data from the data calculating means. In the generating circuit, detecting means for detecting a period other than the period of the master clock at which the count end signal of the clock counting means is output, and the logical product of the output of the detecting means and the master clock or a clock having a desired generation period. Clock generating means for generating an output and current consuming means operated by the clock generating means. Pulse generator function with IC circuit to butterflies. 3. The method according to claim 1, wherein the first detecting means detects that the change in the operation rate of the internal logic realizing means of the pulse generating means varies from coarse to fine, and sets the first set time from a previously stored pulse generating time. Based on the pulse generation time stored in advance that the change in the operation rate of the internal logic realization means of the pulse generation means changes from fine to coarse. The IC circuit with a pulse generation function according to claim 1, wherein the detection is performed based on time. 4. The method according to claim 1, wherein the first detecting means determines from a previously stored pulse generation time that the change in the operation rate of the internal logic realizing means of the pulse generating means varies from coarse to fine.
Detecting based on a third set time, the second detecting means determines from the pulse generation time stored in advance that the change in the operation rate of the internal logic realizing means of the pulse generating means changes from dense to coarse. The IC with a pulse generation function according to claim 1, wherein the current consuming means is operated / stopped in multiple stages by detecting based on the second and fourth set times.
circuit. 5. A pulse generating function according to claim 1, wherein a plurality of said current consuming means are provided, and a period of operation / stop of said plurality of current consuming means is made different. IC circuit. 6. The IC circuit with a pulse generation function according to claim 1, wherein a bypass capacitor is provided between a power supply voltage pin and a ground pin of the LSI for realizing the pulse generation circuit. 7. A pulse generating circuit for generating a desired pulse, and a current consuming circuit for consuming a predetermined current as required, wherein a current consumption of the pulse generating circuit and a current consuming current of the current consuming circuit are calculated. An IC circuit with a pulse generation function, characterized in that the sum is controlled to be within a predetermined range. 8. A method according to claim 1, wherein a sum of a current consumption of said pulse generation circuit and a current consumption of said current consumption circuit is within a predetermined range with respect to a period including a period before and after said pulse generation circuit generates a pulse. 8. The IC circuit with a pulse generation function according to claim 7, wherein 9. A data calculating means for generating a pulse generated in a desired cycle or a pulse delayed by a desired time from a reference signal, and counting an integral multiple of a master clock by the first data from the data calculating means. Clock counting means for generating a pulse after completion of counting, pulse delay means for generating a delay amount equal to or less than a master clock cycle by the second data from the data operation means, and operation of internal logic realizing means of the pulse generation means First detection means for detecting in advance that the change in rate changes from coarse to fine; and second detection for detecting in advance that the change in the operation rate of the internal logic realizing means of the pulse generation means changes from fine to coarse. Detecting means, and current consuming means for consuming a predetermined current based on the detection signal of the first detecting means or the second detecting means. The current waveform is output to a device under test by a pulse generation circuit that operates the current consuming means based on the signal and stops the current consuming means based on a detection signal from the first detecting means. LSI test equipment. 10. A data calculating means for generating a pulse generated in a desired cycle or a pulse delayed by a desired time from a reference signal, and counting an integral multiple of a master clock by the first data from the data calculating means. A clock counting means for generating a pulse after the counting is completed; a pulse delaying means for generating a delay amount equal to or less than a master clock cycle by the second data from the data calculating means; and a counting end signal of the clock counting means. Detecting means for detecting a period other than the period of the master clock, clock generating means for generating an AND of the output of the detecting means and the master clock or a clock having a desired generation period, and the clock generating means An LSI test circuit for outputting a test waveform to a device under test by a pulse generation circuit having current consuming means operating according to Apparatus. 11. The first detecting means according to claim 1, wherein a change in the operation rate of the internal logic realizing means of said pulse generating means varies from coarse to fine, and said first detecting means calculates a first set time from a previously stored pulse generating time. Based on the second detection means,
10. The method according to claim 9, wherein a change in the operation rate of the internal logic realizing means of the pulse generating means from a fine to a coarse change is detected based on a second set time from a previously stored pulse generating time. The described LSI test apparatus. 12. The first detecting means according to claim 1, wherein said change in operation rate of said internal logic realizing means of said pulse generating means varies from coarse to fine from a previously stored pulse generating time. The second detection means detects that the change in the operation rate of the internal logic realization means of the pulse generation means changes from dense to coarse, from the previously stored pulse generation time to the second detection means. 10. The LSI test apparatus according to claim 9, wherein the current consumption means is operated / stopped in multiple stages by detecting based on the second and fourth set times. 13. The LSI according to claim 9, wherein a plurality of said current consuming means are provided, and an operation / stop cycle of said plurality of current consuming means is made different.
Testing equipment. 14. The LSI test apparatus according to claim 9, wherein a bypass capacitor is provided between a power supply voltage pin and a ground pin of the LSI for realizing the pulse generation circuit. 15. A pulse generating circuit for generating a desired pulse, and a current consuming circuit for consuming a predetermined current as necessary, wherein a current consumption of the pulse generating circuit and a current consuming current of the current consuming circuit are determined. An LSI test apparatus characterized in that a test waveform is output to a device under test by the pulse generation circuit by controlling the sum so as to be within a predetermined range. 16. A sum of a current consumption of the pulse generation circuit and a current consumption of the current consumption circuit is in a predetermined range with respect to a period including a period before and after the pulse generation circuit generates a pulse. 2. The method according to claim 1, wherein
5. The LSI test apparatus according to 5.