JP2005249526A - Semiconductor device inspection method, semiconductor device inspection device, and semiconductor device - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To accurately perform inspection such as speed evaluation by effectively suppressing fluctuation in power supply voltage for an LSI which is an inspecting object in performing semiconductor inspection. <P>SOLUTION: When starting inspection and selecting clock frequency, the frequency of a function clock CK is slowly changed with the passage of time to prevent the amount of consumed current within the LSI from abruptly changing, thereby suppressing fluctuation in the supply voltage EV. An LSI tester 100 is provided with a clock generation circuit 120 utilizing a PLL synthesizer and a clock frequency adjustment circuit 130. The frequency division ratio N of a variable frequency divider 125 is slowly changed by means of a control signal S1 outputted from the adjustment circuit 130 to actualize a gradual shift in the frequency of the function clock CK. <P>COPYRIGHT: (C)2005,JPO&NCIPI

Description

  The present invention relates to a semiconductor device inspection method, a semiconductor inspection device, and a semiconductor device.

  FIG. 10 is a block diagram illustrating a configuration example of a power supply unit of a semiconductor inspection apparatus (LSI tester). As shown in the figure, a power supply unit 301 of a semiconductor inspection apparatus (LSI tester) supplies a power supply voltage generated from a variable voltage source 302 via a voltage follower (100% negative feedback operational amplifier) 303 to an object to be inspected. The semiconductor device (DUT) 307 is configured to be provided.

  The output voltage of the operational amplifier 303 is supplied to the power supply terminal 308 of the semiconductor device 307 through the force terminal 305 of the power supply unit 301. The power supply terminal 308 of the semiconductor device 307 is connected to the inverting input terminal of the operational amplifier 303 via the sense terminal 306 of the power supply unit 301, thereby forming a negative feedback path. Note that the signal line connecting the force terminal 305 and the power supply terminal 308 and the signal line connecting the sense terminal 106 and the power supply terminal 308 are short-circuited in the vicinity of the power supply terminal 108 of the semiconductor device 307. Since the output impedance of the voltage follower is extremely low, fluctuations in the power supply voltage applied to the power supply terminal 308 of the semiconductor device 307 are quickly absorbed, and thus the power supply voltage is stabilized.

  During pattern operation in the semiconductor function test, the power supply unit 301 of the semiconductor inspection apparatus (LSI tester) suppresses the voltage fluctuation of the power supply terminal 308 of the semiconductor device 307 and inputs a test pattern signal under a stable power supply voltage. Expected value determination or the like is performed (see Patent Document 1).

JP 2001-4692 (FIG. 1)

  In the configuration of FIG. 10, the power supply voltage output from the voltage follower 303 of the semiconductor inspection apparatus (LSI tester) is output to the outside from the follow terminal 305 of the power supply unit 301 and the power supply terminal 308 of the semiconductor device 307 to be inspected. Branching to the feedback path in the vicinity and returning to the inverting terminal of the operational amplifier 303 via the sense terminal 306 of the power supply unit 301 inevitably increases the path length of the negative feedback path. Since the voltage follower is a negative feedback control system, it is necessary to rotate the loop many times in order to suppress the power supply fluctuation. If the loop length is long, it is difficult to instantaneously suppress the voltage fluctuation.

  On the other hand, when an internal circuit operates in a large-scale integrated circuit such as a system LSI or a memory circuit (here, for example, a CMOS circuit is assumed), a through current flows through each CMOS element at the time of switching. As a result, a large current instantaneously flows in the power supply voltage line. The rapid fluctuation of the large current causes the power supply voltage fluctuation (ringing) in the power supply line.

  In the conventional method for suppressing fluctuations in the power supply voltage using the negative feedback control system, the operation of the negative feedback control system cannot follow the sudden fluctuations in the power supply voltage. It cannot be suppressed. In recent years, higher integration and higher speed of electronic devices have dramatically increased, and accordingly, the power supply voltage has been lowered, and the allowable voltage fluctuation range (voltage fluctuation margin) has become extremely narrow. Under such circumstances, if a large fluctuation in power supply voltage as described above occurs during semiconductor inspection, accurate inspection (for example, speed evaluation of a semiconductor device) cannot be performed.

  FIG. 11 is a waveform diagram showing a state in which the power supply voltage fluctuates rapidly when a large current fluctuates with the operation of the semiconductor device to be inspected. In FIG. 11, reference numeral 110 is a voltage (power supply voltage) of a power supply terminal of the semiconductor device, and reference numeral 111 is a current flowing through the power supply terminal of the semiconductor device.

  As shown in the lower side of FIG. 11, when the power supply current 111 of the semiconductor device suddenly changes stepwise (time t10, time t11), a large fluctuation C and D is generated. Since there are parasitic resistance (R) and parasitic resistance (C) in the power supply line, the fluctuation of the power supply voltage becomes a differential waveform. In order to suppress such fluctuations, a long settling period is required. However, such a settling period cannot be ensured because of a demand for high-speed inspection.

  It is an object of the present invention to effectively suppress fluctuations in power supply voltage and accurately perform inspections such as speed evaluation during semiconductor inspection.

  According to a semiconductor device inspection method of the present invention, a first step of supplying a power supply voltage and a clock from a semiconductor inspection device to a semiconductor device to be inspected, and a clock supplied from the semiconductor inspection device or the semiconductor based on the clock And a second step of suppressing a time change rate of a current consumption amount of an internal circuit of the semiconductor device that operates using a clock generated inside the device.

  The fluctuation of the power supply voltage is caused by a sudden change in the current consumption amount in the LSI. Therefore, the power supply voltage can be stabilized by suppressing the rate of change of current consumption in the semiconductor device with respect to time.

  In the present invention, the second step controls a clock supplied from the semiconductor inspection device or a frequency of a clock generated inside the semiconductor device based on the clock. The amount of current consumption in the internal circuit of the semiconductor device is closely related to the frequency of the operation clock, and the amount of current consumption increases as the frequency of the operation clock increases. Therefore, if the frequency of the operation clock is switched suddenly, the amount of current consumption varies greatly. Therefore, frequency control is performed so as to avoid a sudden change in the frequency of the operation clock. As a result, the change in the current consumption amount of the internal circuit becomes gradual, and the fluctuation of the power supply voltage is suppressed accordingly.

  In the present invention, in the second step, the frequency is controlled based on the value of the power supply voltage supplied from the semiconductor inspection apparatus. The frequency of the operation clock is accurately controlled by feedback control. That is, based on the power supply voltage value, the frequency of the operation clock is dynamically controlled so as to suppress the fluctuation.

  In the present invention, the second step suppresses the frequency at the start of inspection of the semiconductor device of a clock supplied from the semiconductor inspection device or a clock generated inside the semiconductor device based on the clock. . At the start of inspection, the internal circuits of the semiconductor device operate all at once and large power supply voltage fluctuations are likely to occur. Therefore, the elapsed time from the start of inspection is measured using a counter, timer, etc. The frequency is gradually increased. Thereby, rapid fluctuations in the current consumption of the semiconductor device are suppressed, and fluctuations in the power supply voltage are suppressed.

  In the present invention, the second step includes an operation region of an internal circuit of the semiconductor device that operates based on a clock supplied from the semiconductor inspection device or a clock generated inside the semiconductor device based on the clock. Control the number of The internal circuit of the semiconductor device is divided into a plurality of operation areas, and the operation of each operation area can be individually controlled. If inspection is performed by operating each operation region at the same time, the total amount of current consumption increases and current fluctuations increase, so the number of operation regions to be inspected is increased (or decreased gradually). ) To control. Thereby, rapid fluctuations in current consumption in the semiconductor device are suppressed, and fluctuations in the power supply voltage are suppressed.

  The semiconductor inspection apparatus of the present invention includes means for supplying a power supply voltage and a clock to the semiconductor device to be inspected, and means for controlling the frequency of the clock supplied to the semiconductor device to be inspected. In addition to means for supplying the power supply voltage and clock to the semiconductor device, means for gently changing the frequency of the clock is provided in the semiconductor inspection apparatus (LSI tester).

  The semiconductor device of the present invention has frequency control means for controlling the frequency of the clock generated inside the semiconductor device based on the clock supplied from the semiconductor inspection device. Control means for controlling the frequency of the internal clock when generating the operation clock (internal clock) by performing frequency conversion inside the semiconductor device based on the operation clock supplied from the semiconductor inspection device. It is built in. Since the operation clock is controlled inside the semiconductor device, the burden on the semiconductor inspection device (LSI tester) is reduced accordingly.

  The semiconductor device of the present invention further includes monitoring means for generating a signal for controlling the frequency control means based on the value of the power supply voltage supplied from the semiconductor inspection apparatus. Monitoring means for monitoring the level of the power supply voltage is provided inside the semiconductor device, and the monitoring result is output as a control signal for adjusting the frequency of the operation clock. As a result, the frequency of the operation clock can be changed so as to suppress fluctuations in the power supply voltage, and accurate frequency adjustment by negative feedback control can be performed. Here, from the viewpoint of performing negative feedback control at high speed, it is better to shorten the path length of the negative feedback loop. In this respect, it is desirable to employ a configuration in which the frequency is adjusted inside the semiconductor.

  According to another aspect of the present invention, there is provided a semiconductor device including a measuring unit that measures an elapsed time from a test start time of a semiconductor device, a clock supplied from the semiconductor test device based on a measured value, or the semiconductor device based on the clock Frequency control means for suppressing the frequency immediately after the start of the inspection of the clock generated inside. In order to suppress rapid fluctuations in the power supply voltage at the start of the inspection, frequency control means for measuring the elapsed time and controlling the frequency of the operation clock is provided inside the semiconductor device.

  Further, the semiconductor device of the present invention controls the number of operation regions of the internal circuit of the semiconductor device that operates based on a clock supplied from the semiconductor inspection device or a clock generated inside the semiconductor device based on the clock. It has an operation area number control means. When inspection is performed by operating a plurality of operation areas in a semiconductor device at the same time, the total current consumption increases and current fluctuations increase. Therefore, the number of operation areas to be inspected is gradually increased. The semiconductor device is provided with a control means (operation area number control means) for controlling the number of operation areas (or reducing the operation area little by little). Thereby, rapid fluctuations in the operating current of the internal circuit of the semiconductor device are suppressed, and fluctuations in the power supply voltage are suppressed.

  According to another aspect of the present invention, a semiconductor inspection apparatus according to claim 6 is mounted as a BIST (Built In Self Test) circuit on the semiconductor device to be inspected. In consideration of the case where the semiconductor inspection device is built in the semiconductor device to be inspected, a function for controlling the frequency of the operation clock is provided in a BIST (Built In Self Test) circuit. As a result, even in a large-scale memory circuit or the like having a built-in BIST circuit, it is possible to minimize fluctuations in the power supply voltage during inspection.

  According to the present invention, by controlling the “operating clock frequency” or “number of operating regions” of the semiconductor device by software or hardware, by suppressing the rapid fluctuation of the “operating current” in the semiconductor device, It is possible to minimize “power line voltage fluctuation”.

  In the prior art, when a semiconductor device is inspected, a large power supply voltage fluctuation occurs, and the inspection cannot be performed accurately, but the present invention can suppress the power supply voltage fluctuation as much as possible. With respect to semiconductor devices (system LSI, large-scale memory LSI, etc.) that consume a large current due to high speed and high integration, accurate voltage characteristic evaluation and stable inspection are realized.

(First embodiment)
FIG. 1 is a block diagram showing an example of a main configuration of a semiconductor inspection apparatus (LSI tester) according to the present invention. The LSI tester 100 evaluates the voltage characteristics of the LSI 140, evaluates the operation speed, and the like while supplying the power supply voltage EV and the operation clock CK to the LSI (DUT) 140 to be inspected.

  As illustrated, the LSI tester 100 includes a power supply circuit 110, an operation clock generation circuit 120 (A / D converter 121, a phase comparator 122, a low-pass filter (LPF) 123, a digital synthesizer), and a digital synthesizer. VCO (124), variable frequency divider (frequency division ratio N) 125), and clock frequency adjustment circuit 130 for dynamically controlling the frequency of the operation clock. The power supply voltage EV is applied to the power supply terminal 142 of the LSI (DUT) 140. The operation clock CK is given to the clock terminal 144 of the LSI 140.

  Although not shown, the LSI tester 110 has a function of generating various test patterns and a function of performing various diagnoses by analyzing signals output from a semiconductor device (LSI) to be inspected.

  As described above, the amount of current consumption in the LSI (DUT) to be inspected changes abruptly at “immediately after the start of inspection” or “when the frequency of the operation clock (CK) is switched”. As a result, voltage fluctuation of the power supply terminal 142 of the LSI 140 (that is, fluctuation of the power supply line inside the LSI) occurs.

  In the present embodiment, at the timing when a large fluctuation of the power supply voltage is expected (immediately after the start of inspection or when the frequency of the operation clock CK is switched), the operation clock frequency is not increased (or decreased) to a desired frequency at the same time. A method of changing gradually (slowly) with time (dynamic management method of operation clock frequency) is adopted.

  The total current consumption in the LSI 140 increases as the frequency of the operation clock increases. Therefore, if the frequency change of the operation clock on the time axis is made gentle, the change in the current consumption in the LSI 140 becomes gentle, and therefore the fluctuation (ringing) of the power supply voltage can be minimized.

  The LSI tester 100 of FIG. 1 changes the frequency of the operation clock CK using a PLL synthesizer. That is, the operation clock generation circuit 120 includes an A / D converter 121, a phase comparator 122, a low-pass filter (LPF) 123, a digital VCO (124), a variable frequency divider (frequency division ratio N) 125, The frequency of the clock CK output from the digital VCO 124 is changed over time by switching the frequency dividing ratio N of the variable frequency divider in multiple stages (or continuously changing it). Can be changed gradually. The frequency division ratio N in the variable frequency divider 125 changes according to the control signal S1 output from the clock frequency adjustment circuit 130.

  FIG. 2 is a waveform diagram showing the relationship between the power supply voltage, the current flowing through the power supply line, and the frequency of the operation clock at the time of inspection. In FIG. 2, reference numeral 20 is a characteristic line indicating the characteristic of the power supply voltage at the power supply terminal 142 of the LSI (DUT) 140 to be inspected, and reference numeral 21 is a current flowing through the power supply terminal 142 (current of the power supply line). The reference numeral 22 is a characteristic line indicating the frequency characteristic of the operation clock CK supplied to the LSI (DUT) 140.

  The frequency 22 of the operation clock CK is gradually increased from the time t1 which is the inspection start time (or operation clock frequency switching time) to the time t2. As a result, the change in the amount of current flowing through the power supply line (see the characteristic line 21) also becomes gradual (that is, the amount of current does not increase rapidly), and therefore the fluctuation range a of the power supply voltage is reduced.

  Similarly, the frequency of the operation clock CK is gradually decreased from time t3, which is the time point when the inspection is completed (or when the operation clock frequency is switched), to time t4. As a result, the change in the current flowing through the power supply line also becomes gentle (that is, the amount of current does not decrease rapidly), and the fluctuation width b of the power supply voltage becomes small.

(Second Embodiment)
FIG. 3 is a block diagram showing an example of a main configuration of the semiconductor device (LSI) of the present invention. In the above-described embodiment, the frequency of the operation clock is controlled in the LSI tester. However, in this embodiment, the control of the frequency of the operation clock (frequency conversion) is performed inside the semiconductor device. That is, the operating frequency control circuit 142 is provided inside the LSI (DUT) 140 to be inspected. The operating frequency control circuit 142 divides the clock CK supplied from the LSI tester 100 to generate an operating clock CLK for the internal circuit.

  The frequency of the operation clock CLK is controlled as indicated by the lower characteristic line 22 in FIG. That is, the frequency of the operation clock CLK is gradually increased or decreased. As a result, the change in the current flowing through the power supply line becomes gradual (that is, a steep change in the amount of current is suppressed), and therefore the fluctuation range of the power supply voltage can be reduced.

(Third embodiment)
In the above-described embodiment, the frequency of the operation clock is controlled. However, in the present invention, the internal circuit of the semiconductor device (LSI) is divided into a plurality of operation regions, and the number of operation regions to be inspected is adjusted. A method of suppressing a rapid change in current consumption is adopted. That is, the internal circuit of the LSI is divided into a plurality of blocks (operation areas), and the operation of each block (operation area) can be individually controlled.

  Here, if each block (operation area) is operated at the same time for inspection, the total current consumption increases, and a large current flows at the start or end of the inspection or when the frequency of the operation clock is switched. , Current fluctuations in the power supply line become noticeable.

  Therefore, in this embodiment, the number of circuit blocks (operation areas) to be inspected is increased little by little (or gradually reduced) at the start of inspection, at the end of inspection, or at the time of switching the operation clock frequency. Control. As a result, rapid fluctuations in the current flowing through the power supply line of the LSI are suppressed, and accordingly, fluctuations in the power supply voltage are suppressed.

  FIG. 4 is a block diagram showing another example of the main configuration of the semiconductor device (LSI) of the present invention. As shown in the figure, the interior of the LSI (DUT) 140 is divided into three circuit blocks (operation areas) A, B, and C, and the operation / non-operation of each circuit block (operation area) is controlled independently. can do.

  The operation / non-operation of each circuit block (operation area) is controlled by the operation area control circuit 150. That is, the operation area control circuit 150 generates three systems of operation clocks CLK1, CLK2, and CLK3 based on the clock CK supplied from the LSI tester 100, and each of the operation clocks is converted into three circuit blocks (operation areas) A. , B, and C can be supplied (and the supply can be stopped).

  The three operation clocks CLK1, CLK2, and CLK3 may be the clock CK itself supplied from the LSI tester 100, or may be obtained by frequency conversion of the clock CK. The operation / non-operation of the three circuit blocks (operation areas) A, B, and C can be individually controlled by appropriately controlling supply / stop of the operation clocks CLK1 to CLK3.

  FIG. 5 is a waveform diagram showing the relationship between the number of circuit blocks (operation regions) in the operating state, the fluctuation in the amount of current in the power supply line, and the fluctuation in the power supply voltage at the time of inspection. In the figure, reference numeral 50 is a characteristic line showing fluctuations in the power supply voltage of the LSI (DUT) 100, and reference numeral 51 is a characteristic line showing fluctuations in the amount of current flowing in the power supply line of the LSI (DUT) 100. .

  In the lower part of FIG. 5, the number of circuit blocks (operation areas) in the operation state is shown in association with time (period). Here, the notation T1 (A) indicates that the operating circuit block (operation area) is only “A” in the period T1. The same applies to other notations.

  As illustrated, only the circuit block (operation region) A operates in the period T1 (time t3 to t4), and the circuit blocks (operation regions) A and B operate in the period T2 (time t4 to t5). In the period T3 (time t5 to t6), the circuit blocks (operation areas) A, B and C operate, and in the period T4 (time t5 to t7), the circuit blocks (operation areas) A and B operate. At T5 (time t7 to t8), only the circuit block (operation area) A operates.

  In this way, at the start of one inspection (time t3 in the figure), the current consumption is reduced by shifting all the circuit blocks (operation areas) to the operation state at the same time, rather than at the same time. The fluctuation range becomes smaller. Therefore, fluctuations in the power supply voltage can be suppressed. Similarly, at the end of one inspection (time t6 in the figure), the entire circuit block (operating area) is not inactivated at the same time, but is gradually shifted to the inoperative state, thereby consuming The fluctuation range of the current is reduced. Therefore, fluctuations in the power supply voltage can be suppressed.

(Fourth embodiment)
In this embodiment, the frequency of the operation clock is controlled using a feedback control system to suppress fluctuations in the power supply voltage. FIG. 6 is a diagram showing a system configuration for carrying out a semiconductor device inspection method (inspection method in which inspection is performed while dynamically controlling the frequency of an operation clock) according to the present invention.

  As shown in the figure, this semiconductor inspection system includes an LSI tester 100, an inspection target LSI (DUT) 140 (which includes an internal circuit 143 and a power supply voltage monitor circuit 160), and a clock frequency adjustment circuit 170. Is done.

  The LSI tester 100 supplies a power supply voltage (EV) and an operation clock (CK) to the internal circuit 143 of the LSI (DUT) 140. The power supply voltage monitor circuit 160 monitors the power supply voltage (EV) in the LSI (DUT) 140 and sends a signal S 7 indicating the monitoring result to the clock frequency adjustment circuit 170. The clock frequency adjusting circuit 170 sends a control signal S8 for controlling the frequency of the operation clock (CK) to the LSI tester 100 based on the signal S7 indicating the monitoring result. As a result, the frequency (CK) of the operation clock supplied to the LSI (DUT) 140 changes.

  Specifically, when a decrease in the power supply voltage (EV) of the LSI (DUT) 140 is detected, the clock frequency adjustment circuit 170 generates the control signal S8 so as to reduce the frequency of the operation clock (CK). (On the contrary, when an increase in the power supply voltage (EV) is detected, the frequency of the operation clock (CK) is increased). That is, the fact that the power supply voltage (EV) of the LSI (DUT) 140 is instantaneously reduced means that a large voltage drop occurs due to a large current flowing through the power supply line.

  Therefore, in this case, the operation clock (CK) is slowed down, and the amount of current (consumption current amount) flowing through the circuit block in the LSI (DUT) 140 is reduced, thereby suppressing the voltage fluctuation of the power supply line. be able to. By performing negative feedback control, accurate control can be realized.

(Fifth embodiment)
FIG. 7 is a block diagram showing a main configuration of a semiconductor device for carrying out a semiconductor device inspection method (inspection method in which inspection is performed while dynamically controlling the frequency of an operation clock) according to the present invention. In the present embodiment, similarly to the fourth embodiment, the frequency of the operation clock is controlled using a feedback control system to suppress fluctuations in the power supply voltage. However, in this embodiment, the power supply voltage monitor circuit 180 is provided inside the LSI (DUT) 140 to be inspected. That is, the power supply voltage monitor circuit 180 provided in the LSI 140 monitors the voltage fluctuation of the power supply line, and outputs the control signal S9 to the operating frequency adjusting circuit 182 based on the monitoring result. The operating frequency adjusting circuit 182 In accordance with the control signal S9, frequency conversion processing of the clock (CK) supplied from the LSI tester 100 is performed to generate an operation clock (CLK).

  A specific example of the control is the same as that in the fourth embodiment. For example, when a decrease in the power supply voltage (EV) of the LSI (DUT) 140 is detected, the frequency of the operation clock (CLK) decreases, Conversely, when an increase in power supply voltage (EV) is detected, the frequency of the operation clock (CLK) increases.

  In the present embodiment, it is not necessary to provide a power supply voltage monitor circuit on the LSI tester 100 side, and the burden on the LSI tester 100 is reduced accordingly. Further, since the power supply voltage is monitored inside the LSI 140 and the frequency of the operation clock is adjusted based on the monitoring result, the path length of the feedback system is short and prompt feedback control can be performed.

(Sixth embodiment)
At the start of semiconductor inspection, the circuit blocks inside the LSI operate at the same time, so that sudden power supply voltage fluctuations are likely to occur, and if a large power supply voltage fluctuation occurs, subsequent accurate inspection cannot be performed. Focusing on this point, in this embodiment, the elapsed time from the start of the test is measured inside the LSI, and the frequency of the operation clock is gradually changed with the passage of time to prevent rapid fluctuations in the current consumption. And suppresses large fluctuations in power supply voltage.

  FIG. 8 is a block diagram showing the configuration of a semiconductor device for carrying out a semiconductor device inspection method (inspection method in which inspection is performed while controlling the frequency of an operation clock according to the elapsed time at the start of inspection) according to the present invention. It is. As shown in the figure, in the LSI (DUT) 140 to be inspected, a counter 190 for measuring the elapsed time from the inspection start time and an operating frequency adjusting circuit 182 are provided.

  The clock (CK) supplied from the LSI tester 100 is supplied to the counter 190 and the operating frequency adjusting circuit 182. When the inspection is started, the counter 190 counts in synchronization with the clock (CK) and supplies the count value to the operating frequency adjustment circuit 182. Based on the count value from the counter 190, the operating frequency adjusting circuit 182 controls the frequency of the operating clock (CLK) to be lowered immediately after the start of inspection and gradually increased with time. As a result, it is possible to prevent the current consumption from changing abruptly and to suppress a large fluctuation in the power supply voltage.

(Seventh embodiment)
In the above-described embodiment, it is assumed that the LSI tester and the LSI to be inspected are separated, but in this embodiment, it is assumed that the inspection circuit is incorporated in the LSI. FIG. 9 is a block diagram showing the configuration of a semiconductor device incorporating a test circuit for carrying out the semiconductor device method (method of dynamically changing the frequency of the operation clock) of the present invention.

  As shown in the figure, an LSI (DU7) 140 is equipped with a BIST (Built In Self Test) circuit 200 for inspecting the internal circuit 210. The BIST circuit 200 is provided with a clock frequency adjusting circuit 204 and an LSI test circuit 202. The LSI test circuit 202 supplies a power supply voltage (EV) and an operation clock (CK) to the LSI 210 and dynamically changes the frequency of the operation clock (CK) based on a control signal from the clock frequency adjustment circuit 204. Can be made.

  In the present embodiment, the frequency of the operation clock (CK) is simultaneously raised (or lowered) to a desired frequency at the timing at which a large fluctuation in the power supply voltage is expected (immediately after the start of inspection or when the frequency of the operation clock CK is switched). Instead of changing gradually over time. As a result, it is possible to prevent the amount of current consumption of the LSI from changing suddenly, and to suppress the occurrence of large power supply voltage fluctuations. Therefore, even in a system LSI or a large-scale memory LSI incorporating a BIST circuit, fluctuations in the power supply voltage during inspection can be suppressed.

(Eighth embodiment)
As is apparent from the above-described embodiments, the present invention employs a method that avoids a rapid change in the amount of current consumption in the LSI and suppresses fluctuations in the power supply voltage. The contents of this method (semiconductor device inspection method) are summarized as follows.

  That is, the semiconductor device inspection method of the present invention basically includes a first step of supplying a power supply voltage and a clock from a semiconductor inspection device to a semiconductor device to be inspected, and the semiconductor device in the middle of the inspection of the semiconductor device. A rapid change on the time axis of the current consumption amount in the operation region inside the semiconductor device that operates based on the clock supplied from the inspection device or a clock generated based on the clock is suppressed, and thereby the power supply And a second step of suppressing voltage fluctuation.

  Specifically, in the second step described above, it is avoided that the clock supplied from the semiconductor inspection apparatus or the frequency of the clock generated inside the semiconductor apparatus based on the clock changes sharply. To control. Alternatively, a feedback control system is configured, the value of the power supply voltage supplied from the semiconductor inspection device is monitored inside the semiconductor device, and the power supply voltage value is supplied from the semiconductor inspection device so as to suppress a sharp change in the power supply voltage value. Or the frequency of a clock generated inside the semiconductor device.

  In addition, in order to efficiently suppress a large voltage fluctuation immediately after the start of inspection with a simple configuration, the elapsed time from the start of inspection is measured inside the semiconductor device, and based on the measured value, immediately after the start of inspection, The clock frequency is controlled to be low and the frequency is gradually increased with time.

  In addition, instead of changing the clock frequency, the circuit inside the semiconductor device is divided into a plurality of operation areas (circuit blocks), and the operation / non-operation of each operation area can be individually controlled. By gradually changing the number with respect to time, it is possible to prevent a rapid change in current consumption and to suppress fluctuations in the power supply voltage.

  As described above, according to the present embodiment, the “operation clock frequency” or the “number of operation regions” of the semiconductor device is controlled by software or hardware, and the “operation current” in the semiconductor device is rapidly increased. By suppressing the fluctuation, the “voltage fluctuation of the power supply line” can be minimized.

  In the prior art, when a semiconductor device is inspected, a large power supply voltage fluctuation occurs, and the inspection cannot be performed accurately, but the present invention can suppress the power supply voltage fluctuation as much as possible. Accurate voltage characteristic evaluation and stable inspection are realized for semiconductor devices (system LSI, large-scale memory, etc.) that consume a large current due to high speed and high integration. The inspection system of the present invention has a merit that it is relatively simple in configuration and easy to implement.

  According to the semiconductor device inspection method of the present invention, the “operation clock frequency” or “number of operation regions” of the semiconductor device is controlled by software or hardware to suppress rapid fluctuations in “operation current” in the semiconductor device. By doing so, it is possible to minimize the “voltage fluctuation of the power supply line”, and a semiconductor inspection device (LSI tester, BIST circuit, etc.) and semiconductor device (system LSI, large-scale memory, etc.) Useful as.

The block diagram which shows an example of the main structures of the semiconductor inspection apparatus (LSI tester) of this invention Waveform diagram showing the relationship between the power supply voltage, current flowing through the power supply line, and the frequency of the operating clock during inspection 1 is a block diagram showing an example of a main configuration of a semiconductor device (LSI) of the present invention The block diagram which shows the other example of main structures of the semiconductor device (LSI) of this invention Waveform diagram showing the relationship between the number of circuit blocks (operating regions) in the operating state, fluctuations in the amount of current in the power supply line, and fluctuations in the power supply voltage at the time of inspection System configuration for implementing semiconductor device inspection method (inspection method in which inspection is performed while dynamically controlling frequency of operation clock) of the present invention The block which shows the main structures of the semiconductor device for enforcing the inspection method (inspection method which inspects while controlling the frequency of an operation clock dynamically) of the semiconductor device of the present invention The block diagram which shows the structure of the semiconductor device for enforcing the inspection method (inspection method which inspects while controlling the frequency of an operation clock according to elapsed time at the time of an inspection start) of the semiconductor device of the present invention The block diagram which shows the structure of the semiconductor device which incorporates the test circuit for enforcing the semiconductor device method (method which changes the frequency of an operation clock dynamically) of this invention Block diagram showing a configuration example of a power supply unit of a semiconductor inspection apparatus (LSI tester) Waveform diagram showing how the power supply voltage fluctuates suddenly when a large current fluctuates with the operation of the semiconductor device being inspected

Explanation of symbols

100 LSI tester (semiconductor inspection equipment)
DESCRIPTION OF SYMBOLS 110 Power supply circuit 120 Operation clock generation circuit using PLL synthesizer 121 A / D converter 122 Phase comparator 123 Low pass filter (LPF)
124 Digital VCO
125 Variable frequency divider (frequency division ratio N)
130 Clock frequency adjustment circuit 140 LSI to be tested (DUT)
142 Power supply terminal 144 Clock terminal

Claims (11)

A first step of supplying a power supply voltage and a clock from a semiconductor inspection device to a semiconductor device to be inspected;
A second method for suppressing a time change rate of a current consumption amount of an internal circuit of the semiconductor device that operates using a clock supplied from the semiconductor inspection device or a clock generated inside the semiconductor device based on the clock. Steps,
A method for inspecting a semiconductor device including: An inspection method for a semiconductor device according to claim 1,
The second step is a semiconductor device inspection method for controlling a clock supplied from the semiconductor inspection device or a frequency of a clock generated inside the semiconductor device based on the clock. A method for inspecting a semiconductor device according to claim 2,
The second step is a semiconductor device inspection method for controlling a frequency based on a value of the power supply voltage supplied from the semiconductor inspection device. A method for inspecting a semiconductor device according to claim 2,
The second step is a method of inspecting a semiconductor device that suppresses a frequency at the start of inspection of the semiconductor device of a clock supplied from the semiconductor inspection device or a clock generated inside the semiconductor device based on the clock. An inspection method for a semiconductor device according to claim 1,
The second step is a semiconductor for controlling the number of operation regions of an internal circuit of the semiconductor device that operates based on a clock supplied from the semiconductor inspection device or a clock generated inside the semiconductor device based on the clock. Device inspection method. Means for supplying a power supply voltage and a clock to a semiconductor device to be inspected;
Frequency control means for controlling the frequency of a clock supplied to the semiconductor device to be inspected;
A semiconductor inspection apparatus.   A semiconductor device comprising frequency control means for controlling a frequency of a clock generated inside the semiconductor device based on a clock supplied from a semiconductor inspection device.   8. The semiconductor device according to claim 7, further comprising monitor means for generating a signal for controlling the frequency control means based on a value of a power supply voltage supplied from the semiconductor inspection apparatus. A measuring means for measuring an elapsed time from the inspection start time of the semiconductor device;
A frequency control means for suppressing a frequency immediately after the start of inspection of a clock supplied from the semiconductor inspection apparatus based on a measured value or a clock generated inside the semiconductor apparatus based on the clock;
A semiconductor device.   A semiconductor device having an operation region number control means for controlling the number of operation regions of an internal circuit of the semiconductor device that operates by a clock supplied from the semiconductor inspection device or a clock generated inside the semiconductor device based on the clock .   7. A semiconductor device in which the semiconductor inspection device according to claim 6 is mounted as a BIST (Built In Self Test) circuit on the semiconductor device to be inspected.

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