JP2005249394A - Semiconductor device inspection method, semiconductor inspection system, and semiconductor device - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To perform accurate inspections such as speed evaluation etc. by eliminating the adverse effect of variations in a power supply voltage at the start of semiconductor inspection. <P>SOLUTION: A power supply voltage monitor circuit 120 monitors the level of a power supply voltage (EV) supplied for an LSI (DUT) 110 to be inspected at all times and provides a test enable circuit 130 with a signal S1 indicating results of the monitoring. The test enable circuit 130 verifies the convergence of variations in the power supply voltage (EV) and then starts prescribed inspections such as speed test etc. <P>COPYRIGHT: (C)2005,JPO&NCIPI

Description

  The present invention relates to a semiconductor device inspection method, a semiconductor inspection system, and a semiconductor device.

  FIG. 6 is a block diagram illustrating a configuration example of a power supply unit of a semiconductor inspection apparatus (LSI tester). As shown in the figure, a power supply unit 301 of a semiconductor inspection apparatus (LSI tester) supplies a power supply voltage generated from a variable voltage source 302 via a voltage follower (100% negative feedback operational amplifier) 303 to an object to be inspected. The semiconductor device (DUT) 307 is configured to be provided.

  An output signal (power supply voltage) 304 of the operational amplifier 303 is supplied to the power supply terminal 308 of the semiconductor device 307 through the force terminal 305 of the power supply unit 301. The power supply terminal 308 of the semiconductor device 307 is connected to the inverting input terminal of the operational amplifier 303 via the sense terminal 306 of the power supply unit 301, thereby forming a negative feedback path. Note that the signal line connecting the force terminal 305 and the power supply terminal 308 and the signal line connecting the sense terminal 106 and the power supply terminal 308 are short-circuited in the vicinity of the power supply terminal 108 of the semiconductor device 307. Since the output impedance of the voltage follower is extremely low, fluctuations in the power supply voltage applied to the power supply terminal 308 of the semiconductor device 307 are absorbed, and thus the power supply voltage is stabilized.

  During pattern operation in the semiconductor function test, the power supply unit 301 of the semiconductor inspection apparatus (LSI tester) suppresses the voltage fluctuation of the power supply terminal 308 of the semiconductor device 307 and inputs a test pattern signal under a stable power supply voltage. Expected value determination or the like is performed (see Patent Document 1).

JP 2001-4692 A (FIG. 1)

  In the configuration of FIG. 6, the fluctuation of the power supply voltage is prevented using a negative feedback control system. However, in order to suppress fluctuations in the power supply voltage, it is necessary to rotate the loop many times. If the loop length is long, it is difficult to instantaneously suppress voltage fluctuations.

  On the other hand, when an internal circuit operates in a large scale integrated circuit such as a system LSI or a memory circuit (here, for example, a CMOS circuit is assumed), a through current flows through each CMOS element during switching. When the internal circuits of the LSI start to operate all at once, the through currents of the elements are added together, and as a result, a large current flows instantaneously through the power supply voltage line. A rapid fluctuation of a large current causes a large voltage drop, causing a fluctuation of the power supply voltage in the power supply line.

  In the conventional method for suppressing fluctuations in the power supply voltage using the negative feedback control system, the operation of the negative feedback control system cannot follow the sudden fluctuations in the power supply voltage. It can no longer be suppressed. In other words, in recent years, the integration and speeding up of electronic devices have dramatically increased, and accordingly, the power supply voltage has been lowered, and the allowable voltage fluctuation range (voltage fluctuation margin) has become extremely narrow. Yes. Under such circumstances, if a large fluctuation in power supply voltage as described above occurs during semiconductor inspection, accurate inspection (for example, speed evaluation of a semiconductor device) cannot be performed.

  FIG. 7 is a waveform diagram showing how the power supply voltage fluctuates rapidly when the internal circuits of the semiconductor devices to be inspected operate at the same time when the inspection is started and the current consumption greatly fluctuates. In FIG. 7, reference numeral 310 is a voltage (power supply voltage) of a power supply terminal of the semiconductor device, and reference numeral 311 is a current flowing through the power supply terminal of the semiconductor device.

  As shown in the lower part of FIG. 7, when the power supply current 311 of the semiconductor device suddenly changes stepwise (time t0), a rapid voltage drop occurs accordingly, and the power supply voltage 310 of the semiconductor device greatly changes a. Occurs. That is, at time t0, the power supply voltage 310 changes rapidly from the level (LV1) to the level (LV2). Since there are parasitic resistance (R) and parasitic resistance (C) in the power supply line, the fluctuation of the power supply voltage becomes a differential waveform (spike shape), and the fluctuation does not converge immediately. Even if a predetermined inspection such as speed evaluation is performed under such a fluctuation of the power supply voltage, an accurate inspection result cannot be obtained.

  An object of the present invention is to make it possible to accurately perform a predetermined inspection such as speed evaluation at the start of a semiconductor inspection by eliminating the adverse effects of fluctuations in power supply voltage.

  The method for inspecting a semiconductor device of the present invention includes a step of supplying a power supply voltage and an operation clock from a semiconductor inspection device to a semiconductor device to be inspected, a level of a power supply voltage supplied from the semiconductor inspection device, or a power supply inside the semiconductor device Monitoring the level of the voltage; and starting the inspection of the semiconductor device by the semiconductor inspection device when the level of the power supply voltage is at an allowable level.

  Instead of supplying a power supply voltage and an operation clock to a semiconductor device (LSI) to be inspected from a semiconductor inspection device (LSI tester) and immediately performing a test, the fluctuation of the power supply voltage accompanying a change in current consumption is monitored. The official test is started after the change is detected. As a result, the LSI can be accurately tested without being affected by fluctuations in the power supply voltage.

  The inspection system for a semiconductor device according to the present invention has a means for monitoring the level of the power supply voltage supplied from the semiconductor inspection device or the power supply voltage level inside the semiconductor device, and the monitored voltage level is at an allowable level. Means for enabling the semiconductor inspection apparatus to start inspection of the semiconductor device.

  The power supply voltage supplied from the LSI tester or the power supply voltage inside the LSI is monitored, and based on the monitoring result, the LSI can be tested (set to the test enable state), so that the influence of fluctuations in the power supply voltage can be reduced. An accurate test of the LSI can be performed without receiving it.

  According to another aspect of the present invention, there is provided a semiconductor device comprising: means for monitoring a level of a power supply voltage supplied from a semiconductor inspection device or a power supply voltage level in the semiconductor device; and the semiconductor inspection when the monitored voltage level is at an allowable level. Means for enabling the apparatus to start the inspection of the semiconductor device.

  By providing a power supply voltage monitoring function and a function for controlling test execution in a semiconductor device (LSI), the semiconductor device inspection method of the present invention can be realized without imposing a burden on the LSI tester. .

  According to the present invention, it is possible to perform a predetermined inspection of a semiconductor device while eliminating an adverse effect due to a large power supply voltage fluctuation that occurs at the start of the inspection. Therefore, accurate voltage characteristic evaluation and stable inspection of a semiconductor device (system LSI, large-scale memory LSI, etc.) that consumes a large current due to high speed and high integration can be realized.

(First embodiment)
FIG. 1 is a block diagram showing an example of a main configuration of a semiconductor inspection system of the present invention. As shown in the figure, this inspection system supplies the operation clock (CK) and the power supply voltage (EV) to the LSI (DUT) 110 to be inspected, and evaluates the voltage characteristics of the LSI 110 and the operation speed. An LSI tester 100 to perform, a power supply voltage monitor circuit 120 for monitoring the power supply voltage (EV), a test enable signal (S2) based on the monitoring result (S1), and an LSI (DUT) 110 by the LSI tester 100 And a test enable circuit 130 that permits the above test.

  Immediately after the start of inspection (or when the frequency of the operation clock (CK) is switched), the amount of current consumption in the LSI (DUT) to be inspected changes abruptly. A large fluctuation occurs in the power supply voltage supplied or the power supply voltage generated inside the LSI based on the power supply voltage.

  In the inspection system of FIG. 1, the fluctuation of the power supply voltage (EV) supplied from the LSI tester 100 is monitored in real time at the timing at which a large fluctuation of the power supply voltage is expected (particularly immediately after the start of the inspection). Avoiding the negative effects of power supply voltage fluctuations by starting the test while avoiding a large period.

  FIG. 2 is a waveform diagram showing the relationship between the power supply voltage at the start of inspection, the current flowing through the power supply line, and the test enable signal. In FIG. 2, reference numeral 20 indicates the power supply voltage of the LSI (DUT) 110 to be inspected, reference numeral 21 indicates the amount of current in the power supply line, and reference numeral 22 is generated by the test enable circuit 130. The enable signal (S2) is shown.

  At the start of operation (time t1), the amount of current flowing through the power supply line changes abruptly, a large voltage drop occurs, and the power supply voltage 20 drops rapidly (variation width a). Thereafter, the power supply voltage 20 gradually recovers with time. Then, at time t2, the testable voltage level (allowable level) RLV is reached.

  The power supply voltage monitor circuit 120 monitors the fluctuation of the power supply voltage 20 in real time, and constantly sends a signal S1 indicating the monitoring result to the test enable circuit 130. In the test enable circuit 130, after the power supply voltage 20 suddenly drops immediately after the start of the test, the voltage level gradually recovers, exceeds the allowable level RLV (time t2), and more preferably, the voltage fluctuation range is as shown in FIG. 2 is detected, the level of the test enable signal S2 is changed at that time (after time t2 (including time t2)), and the test enable signal S2 is detected. Is active. As a result, inspection by the LSI tester 100 becomes possible, a test pattern (not shown) is given from the LSI tester 100 to the LSI 110, and inspection of the LSI 110 is started.

  As described above, it is possible to perform an accurate test by delaying the timing for performing a formal test of the LSI and starting the test from the time when the fluctuation of the power supply voltage due to the voltage drop is sufficiently reduced.

(Second Embodiment)
FIG. 3 is a block diagram showing a main configuration example of the semiconductor device (LSI) of the present invention. 3, the same parts as those in FIG. 1 are denoted by the same reference numerals. In the inspection system of FIG. 1, the monitor circuit and the test enable circuit are provided outside the LSI tester and the LSI to be inspected. In this embodiment, these circuits are mounted inside the LSI. This reduces the burden on the LSI tester. Further, since the fluctuation of the power supply voltage is detected inside the LSI, the voltage level can be detected accurately.

  As shown in FIG. 3, a power supply voltage monitor circuit 210 and a test enable circuit 220 are mounted on an LSI (DUT) 200 to be inspected. As in FIG. 1, the LSI 200 is supplied with the power supply voltage EV and the operation clock CK from the LSI tester 100. However, the test is not started immediately after the supply is started, but the formal inspection is started when the fluctuation of the power supply voltage is converged.

  The power supply voltage monitor circuit 210 monitors the level of the power supply voltage EV in real time, and sends a signal S1 indicating the monitoring result to the test enable circuit 220. The test enable circuit 220 detects that the fluctuation of the power supply voltage has converged, and sends a test enable signal S2 to the LSI tester 100 at that time. As a result, a test by the LSI tester 100 is possible, and a formal test for the LSI 200 is started.

(Third embodiment)
FIG. 4 is a block diagram showing another example of the main configuration of the semiconductor inspection system of the present invention. In FIG. 4, the same reference numerals are given to the same portions as those in the previous drawings. The basic configuration of the semiconductor inspection system according to this embodiment is almost the same as that shown in FIG. However, in this embodiment, the power supply voltage supplied from the LSI tester is not directly monitored, but the internal power supply voltage of the LSI to be inspected is a dedicated “internal power supply voltage monitor terminal” provided in the LSI. Use to monitor. That is, a configuration is adopted in which the internal power supply voltage is derived from the “internal power supply voltage monitor terminal” and monitored.

  Here, the level of the “power supply voltage inside the LSI (internal power supply voltage)” may be the same as the power supply voltage (EV) supplied from the LSI tester, and the result of level conversion inside the LSI The voltage level may be different from that of EV.

  In FIG. 4, an LSI (DUT) 110 is provided with an internal power supply voltage monitor terminal 112. The internal power supply voltage monitor terminal 112 is connected to an internal power supply line (not shown) of the LSI 110. By using the internal power supply voltage monitor terminal 112, the voltage level of the internal power supply line can be monitored in real time. It can be done. As shown in the figure, this inspection system supplies the operation clock (CK) and the power supply voltage (EV) to the LSI (DUT) 110 to be inspected, while evaluating the voltage characteristics of the LSI 110, the operation speed, and the like. An LSI tester 100 to perform, a power supply voltage monitor circuit 120 for monitoring the power supply voltage (EV), a test enable signal (S2) based on the monitoring result (S1), and an LSI (DUT) 110 by the LSI tester 100 And a test enable circuit 130 that permits the above test. Immediately after the start of inspection (or when the frequency of the operation clock (CK) is switched), the amount of current consumption in the LSI (DUT) 110 to be inspected changes abruptly, resulting in the power supply voltage inside the LSI 110. A large fluctuation occurs.

  In the inspection system of FIG. 1, the internal power supply voltage is predicted by monitoring in real time the fluctuation of the internal power supply voltage immediately after the start of inspection, in which a large fluctuation of the power supply voltage is expected, and starting the test while avoiding the period when the voltage fluctuation is large. Avoid the adverse effects of fluctuations.

  FIG. 5 is a waveform diagram showing the relationship between the power supply voltage at the start of inspection, the current flowing through the internal power supply line, and the test enable signal. In FIG. 5, reference numeral 30 indicates the power supply voltage of the LSI (DUT) 110 to be inspected, reference numeral 31 indicates the amount of current in the power supply line, and reference numeral 32 is generated by the test enable circuit 130. The enable signal (S2) is shown.

  At the start of operation (time t3), the amount of current flowing through the power supply line changes abruptly, a large voltage drop occurs, and the power supply voltage 20 drops rapidly. Thereafter, the power supply voltage 20 gradually recovers with time. At time t4, the voltage level (allowable level) RLV that can be inspected is reached.

  The power supply voltage monitor circuit 120 monitors the fluctuation of the power supply voltage 20 in real time, and constantly sends a signal S1 indicating the monitoring result to the test enable circuit 130. The test enable circuit 130 changes the level of the test enable signal S2 after the time when the voltage level gradually recovers and exceeds the allowable level RLV (time t4) after the power supply voltage 20 suddenly drops immediately after the start of the test. The test enable signal S2 is activated. As a result, inspection by the LSI tester 100 becomes possible, a test pattern (not shown) is given from the LSI tester 100 to the LSI 110, and inspection of the LSI 110 is started.

  As described above, it is possible to perform an accurate test by delaying the timing for performing a formal test of the LSI and starting the test from the time when the fluctuation of the power supply voltage due to the voltage drop is sufficiently reduced. In the embodiment of FIG. 4, the LSI 110 only needs to be provided with a terminal 112 for monitoring the internal power supply voltage, and is easy to implement.

  In the above example, the LSI tester and the LSI to be inspected are separated, but the present invention can also be applied to the case where the LSI test circuit is built in the LSI itself. That is, the present invention can also be applied to a memory LSI or a system LSI in which an LSI test circuit is mounted in the LSI as a BIST (Built In Self Test) circuit.

  In this case, the level of the internal power supply voltage is monitored in the LSI, and the test enable signal is made active after the time when it is determined that the fluctuation of the power supply voltage has converged, and the test by the BIST circuit is enabled.

  As described above, according to the present embodiment, it is possible to eliminate the adverse effects caused by the large fluctuations in the power supply voltage that occur at the start of inspection, and therefore, a semiconductor device (system LSI) that consumes a large current due to high speed and high integration. Accurate voltage characteristic evaluation and stable inspection of a large-scale memory LSI or the like.

  The present invention eliminates adverse effects caused by large fluctuations in power supply voltage that occur at the start of inspection, and makes it possible to perform a predetermined inspection of a semiconductor device. Therefore, a semiconductor device that consumes a large current due to high speed and high integration ( System LSI, large-scale memory LSI, etc.) have an effect of enabling accurate voltage characteristic evaluation and stable inspection, semiconductor inspection system (inspection system using LSI tester or BIST circuit) and semiconductor device (system) This is useful as an LSI or a large-scale memory.

The block diagram which shows an example of the main structures of the semiconductor inspection system of this invention Waveform diagram showing the relationship between the power supply voltage, the current flowing through the power supply line, and the test enable signal at the start of inspection 1 is a block diagram showing a main configuration example of a semiconductor device (LSI) of the present invention. The block diagram which shows the other example of the main structures of the semiconductor inspection system of this invention Waveform diagram showing the relationship between the power supply voltage at the start of inspection, the current flowing through the internal power supply line, and the test enable signal Block diagram showing a configuration example of a power supply unit of a semiconductor inspection apparatus (LSI tester) Waveform diagram showing how the power supply voltage fluctuates rapidly when the internal circuits of the semiconductor devices to be inspected operate at the same time when the inspection starts and the current consumption greatly fluctuates.

Explanation of symbols

100 LSI tester (semiconductor inspection equipment)
110 LSI to be tested (DUT)
120 power supply voltage monitor circuit 130 test enable circuit

Claims (3)

Supplying a power supply voltage and an operation clock from a semiconductor inspection device to a semiconductor device to be inspected;
Monitoring the level of the power supply voltage supplied from the semiconductor inspection device or the level of the power supply voltage inside the semiconductor device;
Starting the inspection of the semiconductor device by the semiconductor inspection device when the level of the power supply voltage is at an allowable level;
A method for inspecting a semiconductor device including: Means for monitoring the level of the power supply voltage supplied from the semiconductor inspection device or the level of the power supply voltage inside the semiconductor device;
Means for allowing the semiconductor inspection apparatus to begin inspection of the semiconductor device when the monitored voltage level is at an acceptable level;
A semiconductor device inspection system comprising: Means for monitoring the level of the power supply voltage supplied from the semiconductor inspection device or the level of the power supply voltage inside the semiconductor device;
Means for allowing the semiconductor inspection apparatus to begin inspection of the semiconductor device when the monitored voltage level is at an acceptable level;
A semiconductor device comprising:

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