JP2010256026A - Apparatus and system for facilitating power source analysis - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide an apparatus and system for facilitating a power source analysis, which achieves facilitation of an estimation analysis in source voltage transition and voltage fluctuation, in a semiconductor circuit which makes operating source voltage and an operating frequency variable dynamically so as to reduce consumption. <P>SOLUTION: The device is provided with: a core circuit 1; power source SW circuits 2 the power levels of which are altered; and delay circuits 3 which set a transition time of gate signals of the power source SW circuits 2. Combination control of the transition time of the gate signals of the power source SW circuits 2 and the number of the power source SW circuits 2 being Active (alive), is made freely by a power source SW control circuit 4 and a voltage/frequency switching control circuit 5. Pseudo power source transition and voltage fluctuation are generated thereby, and the estimation analysis by an LSI tester or that by using an analyzing device is facilitated. <P>COPYRIGHT: (C)2011,JPO&INPIT

Description

  The present invention relates to an apparatus for facilitating power supply analysis and a system for facilitating power supply analysis, and in particular, power supply analysis effective for facilitating evaluation analysis in power supply fluctuations of a semiconductor integrated circuit or the like using DVFS (Dynamic Voltage Frequency Scaling) technology. The present invention relates to a facilitating device and a power analysis facilitating system.

  2. Description of the Related Art In recent years, semiconductor integrated circuits (LSIs) have been increasing in circuit scale and speeded up with process miniaturization. In particular, battery-powered mobile products are required to be designed to consume less leakage current and operating current due to the increase in circuit scale due to submicron design. For this reason, application of the DVFS technique has been studied as a power supply control technique as a countermeasure for reducing power supply leakage current during standby, a countermeasure for reducing operating current during operation, and a countermeasure for correcting transistor characteristics in process variations. Also, with the increase in circuit scale, complexity, and sophistication of low-consumption technology, it is becoming difficult to evaluate and analyze LSI defects / failures / low yield measures.

  In DVFS technology application, a method for critical path design utilizing a delay circuit and a method of detecting a malfunction error (see, for example, Patent Document 1) are proposed, and in order to bring the operating voltage closer to the optimum lower limit operating voltage, A semiconductor device (see, for example, Patent Document 2) that evaluates in steps and calculates an optimum voltage value has been proposed.

JP 2008-31767 A

JP 2004-194134 A

  However, in such a conventional semiconductor integrated circuit, LSI evaluation / analysis is not easy when LSI malfunctions / failures / low yields occur, and evaluation / analysis cannot be performed, resulting in an increase in man-hours. There was a problem like this.

  In realizing DVFS technology, it is necessary to consider the internal operating state of the LSI in cooperation with the actual operation of the application software. Therefore, optimization of LSI operation setting conditions, LSI malfunction, and evaluation analysis at the time of failure are extremely important. It is difficult to. Further, the operation analysis at the time of the power supply voltage transition has a problem that it cannot be performed due to the function restriction of the LSI tester.

  In general, factors that cause LSI malfunctions in DVFS technology include (1) noise factors when power changes, (2) mismatch between actual operation and operating frequency / operating voltage settings, and (3) device variation differences. It is done.

  The present invention solves the above-described conventional problems, and provides a power supply analysis facilitating device and a power supply analysis facilitating system for facilitating evaluation analysis in power supply fluctuation and power supply transition operation of an LSI using DVFS technology or the like. The purpose is to do.

  In order to solve the above-described conventional problems, a first aspect of the power supply analysis facilitating device of the present invention includes a core circuit that operates with a certain power supply, a plurality of power supply SW circuits that can change the power supply level of the core circuit, A delay circuit having a configuration capable of changing the transition time setting of the rise and fall of the gate signal of the power supply SW circuit, and a power supply SW for controlling active / inactive (Active / No Active) of the power supply SW circuit and the delay circuit A control circuit; and a voltage / frequency switching control circuit capable of selecting a combination of a plurality of power supply SW circuits and a plurality of delay circuits.

  According to this configuration, a pseudo power supply transition (by controlling the combination of the rise / fall transition time of the gate signal of the power supply SW circuit and the number of active / inactive power supply SW circuits freely ( The LSI tester evaluation analysis at the time of power supply fluctuation / power supply transition is made possible by causing a power supply fluctuation) or a voltage level change to generate a critical path fail (malfunction) state.

  In addition, since the analysis apparatus and the LSI can be easily synchronized in the LSI test, LSI evaluation analysis using the analysis apparatus can be facilitated. Thereby, the outstanding effect which can reduce an evaluation analysis man-hour significantly is acquired.

  The delay circuit used in the first embodiment of the present invention includes a plurality of delay value circuits and a selector circuit, and the plurality of power supply SW circuits are activated / deactivated by the power supply SW control circuit and the voltage / frequency switching control circuit. It has a configuration with a function that can freely select a combination of active (active / no active) and the delay value circuit.

  The second aspect of the power source analysis facilitating device of the present invention is connected to the voltage / frequency switching control circuit in the first aspect, and the voltage / frequency that optimizes the operating voltage and operating frequency of the core circuit in the actual product. A frequency optimization circuit is provided.

  According to this configuration, it is possible to realize analysis linked with actual operation voltage / frequency switching operation in the product by linking with the voltage / frequency optimization circuit in actual operation, not only reducing the evaluation analysis man-hours, but also improving the analysis accuracy. An excellent effect that can be improved is obtained.

  A third aspect of the power source analysis facilitating device of the present invention includes a current monitor circuit that is connected to a power source of the core circuit that operates with a certain power source in the first and second aspects, and monitors an operating current value. A function of outputting monitor information to the voltage / frequency optimization circuit and the IO terminal is provided.

  According to this configuration, the current consumption state of the core circuit can be monitored linearly, and by obtaining information on the operation state of the core circuit 1, an analysis associated with the actual operation voltage / frequency switching operation in the product becomes possible. In addition, an excellent effect of improving the analysis accuracy can be obtained.

  The current monitoring circuit used in the third embodiment of the present invention comprises a plurality of capacitors, one side is connected to the power supply of the core circuit, and one side is connected to the time determination circuit, and the operation per unit time The current value is monitored in the evaluation analysis mode.

  In the DVFS technology application, the operating power supply voltage is increased and the operating frequency is increased during high-speed operation. This increases the operating current. On the other hand, the reverse occurs during low-speed operation. Therefore, the operating current of the core circuit is an important parameter in evaluating and analyzing the optimum operating voltage and operating frequency setting of the core circuit. An excellent effect that current information can be obtained with such a simple configuration is obtained.

  In addition, by outputting current monitor information to the outside, it has a simple emulator function, which can be used not only for evaluation analysis but also for debugging software development in products, and has the excellent effect of reducing software development man-hours. Is obtained.

  As a system of the power analysis facilitating apparatus using the power analysis facilitating apparatus of the present invention, the power of the core circuit is supplied by a power circuit, and the core circuit is supplied through a power SW control circuit and a voltage / frequency optimization circuit. This can be realized by controlling the operation power supply voltage.

  According to the power supply analysis facilitating device and the power analysis facilitating system of the present invention, an analysis using an LSI tester / fault diagnosis analysis / analysis device in evaluation / analysis of power fluctuation or power transition of LSI using DVFS technology or the like. Can be realized easily.

The block diagram which shows the structure of the power supply analysis facilitation apparatus which concerns on Embodiment 1 of this invention. The block diagram which shows the structure of the delay circuit which concerns on Embodiment 1 of this invention. The block diagram which shows the structure of the power supply analysis facilitation apparatus which concerns on Embodiment 2 of this invention. A block diagram showing a configuration of a power source analysis facilitating device according to a third embodiment of the present invention. The block diagram which shows the structure of the current monitor circuit which concerns on Embodiment 3 of this invention. System diagram of power supply analysis facilitating apparatus according to Embodiment 4 of the present invention

  Hereinafter, embodiments of the present invention will be described with reference to the drawings.

(Embodiment 1)
FIG. 1 is a diagram showing a configuration of a semiconductor integrated circuit for explaining a power source analysis facilitating apparatus according to Embodiment 1 of the present invention. As shown in FIG. 1, the power supply analysis facilitating device according to the present embodiment includes a core circuit 1 that operates with a power supply VDD1, a plurality of power supply SW (switch) circuits 2 that can change the power supply level of the core circuit 1, and a power supply SW. The delay circuit 3 having a configuration capable of changing the transition time setting of the rise and fall of the gate signal of the circuit 2, and the power SW control for controlling the power SW circuit 2 and Active / No Active (active and inactive) of the delay circuit 3 A circuit 4 and a voltage / frequency switching control circuit 5 capable of selecting a combination of a plurality of power supply SW circuits 2 and a plurality of delay circuits 3 are provided.

  In FIG. 1, the power supply SW control circuit 4 controls the power supply SW circuit 2 (Active / No Active) at a time in a normal operation by a signal from an internal circuit or an IO signal from an external power supply IC or the like. The delay value at is fixed.

  At the time of the evaluation analysis, the voltage / frequency switching control circuit 5 controls the power supply SW control circuit 4 and the delay circuit 3, and individually controls Active / No Active (active and inactive) of the power supply SW circuit 2. The delay value can also be individually controlled. The voltage / frequency switching control circuit 5 has a configuration that can be controlled from the outside if connected to the IO terminal. A combination of the power SW circuit 2 and the delay value may be prepared as a test mode.

  According to this configuration, the operating current amount of the core circuit 1 can be controlled by freely combining the rise / fall transition time of the gate signal of the power supply SW circuit 2 and the number of SWs of Active / No Active (active and inactive). And the power supply transition time of the core circuit 1 can be controlled in a pseudo manner.

  This pseudo power transition (power fluctuation) and voltage level change are generated to generate a critical path fail (malfunction) state, and power fluctuation / power transition is generated by itself. Enables LSI tester evaluation analysis during transition.

  In addition, since the analysis apparatus and the LSI can be easily synchronized in the LSI test, LSI evaluation analysis using the analysis apparatus can be facilitated. Since an analysis that could not be realized in the past can be performed, an excellent effect of greatly reducing the number of evaluation analysis steps can be obtained.

  FIG. 2 is a diagram showing a configuration of the delay circuit 3 according to the first embodiment. As shown in FIG. 2, the delay circuit 3 includes a plurality of delay value circuits 6 and a selector circuit 7, and the power supply SW control circuit 4 and the voltage / frequency switching control circuit 5 perform Active / No Active ( (Active and inactive) It is a configuration in which individual control and delay value selection combination can be freely set.

  The number of power supply SW circuits 2 and the number of delay values are set to the optimum numbers according to the LSI specifications and are not limited. The power supply SW circuit 2 is inserted on the GND side in FIG. 1, but may be inserted on the VDD1 side. The power supply SW circuit 2 is normally composed of Nch Tr (GND side) and Pch Tr (VDD side), but is not limited thereto. Further, the number of core circuits 1 is not limited.

(Embodiment 2)
FIG. 3 is a diagram showing a configuration of a semiconductor integrated circuit for explaining the power supply analysis facilitating device according to the second embodiment of the present invention. As shown in FIG. 3, the power source analysis facilitating device of this embodiment is connected to the voltage / frequency switching control circuit 5 in the first aspect, and optimizes the operating voltage and operating frequency of the core circuit 1 in the actual product. The voltage / frequency optimization circuit 8 is provided.

  The voltage / frequency optimization circuit 8 is a circuit that determines an operating power supply voltage and an operating frequency that dynamically change depending on the operating state of the core circuit 1 in the normal operation, and in the standby operation (when the core circuit 1 is not operating). The power supply SW circuit 2 is set to No Active (inactive) through the power supply SW control circuit 4 to reduce the power supply leakage current.

  Therefore, it has a table (first table) for classifying states based on the operating power supply voltage and operating frequency of the core circuit 1 in normal operation, and the operation setting condition information of the core circuit 1 is used as the voltage / frequency switching control circuit 5. Output to.

  The voltage / frequency switching control circuit 5 determines a table (second table) for determining the number of Active / No Active (active and inactive) power supply SW circuits 2 and the delay value of the delay circuit 3 based on the operation setting condition information. The power supply SW control circuit 4 and the delay circuit 3 are controlled.

  According to this configuration, the voltage / frequency switching control circuit 5 can be linked with the voltage / frequency optimization circuit 8 in actual operation instead of external control from the IO terminal. The analysis associated with the frequency switching operation can be realized, and not only the evaluation analysis man-hours can be reduced, but also an excellent effect of improving the analysis accuracy can be obtained.

(Embodiment 3)
FIG. 4 is a diagram showing a configuration of a semiconductor integrated circuit for explaining a power source analysis facilitating device according to Embodiment 3 of the present invention. As shown in FIG. 4, the power source analysis facilitating device of the present embodiment is connected to the power source of the core circuit 1 that operates on the power source VDD1 and monitors the operating current value in the first and second aspects. 9 and a function of outputting the monitor information to the voltage / frequency optimization circuit 8 and the IO terminal.

  The voltage / frequency optimization circuit 8 has a function of correcting the operation setting condition information of the core circuit 1 based on the time determination output information in the current monitor circuit 9. Further, the control signal from the voltage / frequency switching control circuit 5 to the power supply SW control circuit 4 and the delay circuit 3 can be controlled by the time judgment output information in the direct current monitor circuit 9, and the number of active of the power supply SW circuit 2. And a function of determining a delay value of the delay circuit 3.

  According to this configuration, the current consumption state of the core circuit 1 can be linearly monitored, so that information on the operation state of the core circuit 1 can be obtained and an analysis associated with the actual operation voltage / frequency switching operation in the product can be performed. Furthermore, not only the range of analysis is widened, but also an excellent effect of improving the analysis accuracy can be obtained.

  FIG. 5 is a diagram showing a configuration of the current monitor circuit 9 according to the third embodiment. As shown in FIG. 5, the current monitor circuit 9 used in the third embodiment of the present invention includes a plurality of capacitors 10, one side connected to the power supply VDD 1 of the core circuit 1, and one side connected to the time determination circuit 11. To do. The time determination circuit 11 converts the operation setting condition (operation voltage / operation frequency) of the core circuit 1 based on the time charged in the capacitor 10.

  By inputting a refresh signal to the time determination circuit 11, the operating current of the core circuit 1 per unit time can be monitored. Also, as a matter of course, the control signal causes the operation to be in a No Active (inactive) state during normal operation so that no extra current flows. Here, the current monitor circuit 9 is configured on the VDD1 side. However, if the configuration is reversed, the current monitor on the GND side can be performed.

  In the DVFS technology application, the operating power supply voltage is increased and the operating frequency is increased during high-speed operation. This increases the operating current. On the other hand, the reverse occurs during low-speed operation. Therefore, the operating current of the core circuit 1 becomes an important parameter in evaluating and analyzing the optimum operating voltage and operating frequency setting of the core circuit 1. An excellent effect that current information can be obtained with such a simple configuration is obtained.

  By outputting current monitor information to the outside, it has a simple emulator function, which can be used not only for evaluation analysis but also for debugging software development in products, and has the excellent effect of reducing software development man-hours. can get.

(Embodiment 4)
FIG. 6 is a diagram illustrating a system configuration of the power supply analysis facilitating device according to the first, second, and third embodiments of the present invention. As the system 13 of the power supply analysis facilitating apparatus according to the first, second, and third embodiments of the present invention, the power supply IC circuit 12 supplies the power of the core circuit 1, and the power supply SW control circuit 4 and the voltage / frequency are supplied. This can be realized by controlling the operating power supply voltage of the core circuit 1 through the optimization circuit 8.

  The present invention is not limited to the embodiment described above, and can be implemented in various forms without departing from the gist of the present invention.

  The power supply analysis facilitating apparatus according to the present invention is effective for facilitating evaluation analysis of power supply fluctuations in a semiconductor integrated circuit or the like using DVFS (Dynamic Voltage Frequency Scaling) technology or the like.

DESCRIPTION OF SYMBOLS 1 Core circuit 2 Power supply SW circuit 3 Delay circuit 4 Power supply SW control circuit 5 Voltage / frequency switching control circuit 6 Delay value circuit 7 Selector circuit 8 Voltage / frequency optimization circuit 9 Current monitor circuit 10 Capacitor 11 Time determination circuit 12 Power supply IC

Claims (14)

A core circuit that operates with a specific power source;
A plurality of power SW circuits capable of changing the power level of the core circuit;
A delay circuit having a configuration capable of changing a transition time setting of rising or falling of a gate signal of the power supply SW circuit;
A power SW control circuit that controls activation / deactivation of the power SW circuit and the delay circuit;
A power supply analysis facilitating device comprising: a voltage / frequency switching control circuit capable of selecting a combination of the plurality of power supply SW circuits and the plurality of delay circuits. The apparatus for facilitating power analysis according to claim 1,
The power supply analysis facilitating device, wherein the power supply SW control circuit fixes a delay value of the delay circuit during normal operation. The apparatus for facilitating power analysis according to claim 1,
The voltage / frequency switching control circuit is an apparatus for facilitating power analysis, which individually controls a delay value of the delay circuit during evaluation analysis. The apparatus for facilitating power analysis according to claim 1,
The delay circuit is connected to the power supply SW control circuit and has a plurality of delay value circuits having different delay values;
A selector circuit connected to the plurality of delay value circuits, selecting a predetermined delay value according to a signal from the voltage / frequency switching control circuit, and supplying the selected delay value to the power SW circuit;
An apparatus for facilitating power supply analysis, wherein a combination of activation / inactivation of the plurality of power supply SW circuits and the delay value circuit is selected by the power supply SW control circuit and the voltage / frequency switching control circuit. The apparatus for facilitating power analysis according to claim 1,
An apparatus for facilitating power supply analysis, comprising a voltage / frequency optimization circuit that is connected to the voltage / frequency switching control circuit and optimizes an operating voltage and an operating frequency of the core circuit. The power supply analysis facilitating device according to claim 5,
The voltage / frequency optimization circuit includes a first table in which operation setting condition information including an operation power supply voltage and an operation frequency optimized for the core circuit is recorded. The apparatus for facilitating power analysis according to claim 6,
The voltage / frequency switching control circuit has a second table for determining activation / deactivation of the power supply SW circuit 2 and a delay value of the delay circuit based on the operation setting condition information, and facilitates power analysis apparatus. The power supply analysis facilitating device according to claim 5,
Connected to the power supply side or the ground side of the core circuit operating with a predetermined power supply, comprising a current monitor circuit for monitoring the operating current value of the core circuit;
A power supply analysis facilitating device that outputs the monitor information to the voltage / frequency optimization circuit or to the outside. The power supply analysis facilitating device according to claim 8,
The current monitor circuit includes a plurality of capacitors, one end of which is connected to the power source of the core circuit,
A power analysis facilitating device comprising: a time determination circuit connected to the other end of the plurality of capacitors and monitoring an operating current value of the core circuit. The power supply analysis facilitating device according to claim 9,
The apparatus for facilitating power analysis, wherein the time determination circuit converts an operating voltage and an operating frequency of the core circuit based on a time during which the capacitor is charged. The power supply analysis facilitating device according to claim 9,
The apparatus for facilitating power supply analysis, wherein the time determination circuit monitors an operating current per unit time of the core circuit based on a supplied refresh signal. The power supply analysis facilitating device according to claim 9,
The voltage / frequency optimization circuit corrects the operation setting condition information recorded in the first table based on output information of the time determination circuit. The power supply analysis facilitating device according to claim 9,
The power supply analysis facilitating device, wherein the voltage / frequency optimization circuit controls activation / deactivation of the power supply SW circuit and determines a delay value of the delay circuit in accordance with output information of the time determination circuit. The power supply analysis facilitating device according to any one of claims 1 to 13,
A power supply circuit that supplies power to the power supply SW circuit and the core circuit,
A power supply analysis facilitating system for controlling an operating power supply voltage of the core circuit through the power supply SW control circuit and the voltage / frequency optimization circuit.

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