CN113711065A - Semiconductor integrated circuit device and inspection method for semiconductor integrated circuit device - Google Patents
Semiconductor integrated circuit device and inspection method for semiconductor integrated circuit device Download PDFInfo
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- CN113711065A CN113711065A CN202080027610.4A CN202080027610A CN113711065A CN 113711065 A CN113711065 A CN 113711065A CN 202080027610 A CN202080027610 A CN 202080027610A CN 113711065 A CN113711065 A CN 113711065A
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- G—PHYSICS
- G01—MEASURING; TESTING
- G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
- G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
- G01R31/28—Testing of electronic circuits, e.g. by signal tracer
- G01R31/2851—Testing of integrated circuits [IC]
- G01R31/2855—Environmental, reliability or burn-in testing
- G01R31/2856—Internal circuit aspects, e.g. built-in test features; Test chips; Measuring material aspects, e.g. electro migration [EM]
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- G—PHYSICS
- G01—MEASURING; TESTING
- G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
- G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
- G01R31/28—Testing of electronic circuits, e.g. by signal tracer
- G01R31/2851—Testing of integrated circuits [IC]
- G01R31/2855—Environmental, reliability or burn-in testing
- G01R31/2872—Environmental, reliability or burn-in testing related to electrical or environmental aspects, e.g. temperature, humidity, vibration, nuclear radiation
- G01R31/2879—Environmental, reliability or burn-in testing related to electrical or environmental aspects, e.g. temperature, humidity, vibration, nuclear radiation related to electrical aspects, e.g. to voltage or current supply or stimuli or to electrical loads
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
- H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
- H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
- H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L22/00—Testing or measuring during manufacture or treatment; Reliability measurements, i.e. testing of parts without further processing to modify the parts as such; Structural arrangements therefor
- H01L22/10—Measuring as part of the manufacturing process
- H01L22/14—Measuring as part of the manufacturing process for electrical parameters, e.g. resistance, deep-levels, CV, diffusions by electrical means
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
- H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body
Abstract
The present invention provides a semiconductor integrated circuit device which incorporates an analog circuit and a diagnostic circuit thereof, wherein the diagnostic circuit is not operated at the time of wafer level burn-in, and burn-in screening quality can be improved by increasing the activation rate of a DSP, and a method for inspecting the semiconductor integrated circuit device.
Description
Technical Field
The present invention relates to a circuit structure and an inspection method of a semiconductor integrated circuit device, and more particularly, to a technique effective for application to a semiconductor integrated circuit device for inspection by wafer level burn-in (WLBI).
Background
Burn-in screening, which screens a fault hidden in a semiconductor integrated circuit device (LSI) in a short time by driving the LSI while applying a load such as temperature, is an essential process for ensuring quality in the LSI, particularly in an on-vehicle LSI which is required to have high reliability.
The method of performing this Burn-In screening for LSI chips formed on a Wafer is Wafer Level Burn-In (WLBI).
In wafer level burn-in (WLBI), a WLBI jig (WLBI probe) is brought into stable contact with a PAD (PAD) electrode of an LSI chip to supply power and input/output signals, and the LSI chip on the wafer is driven at high temperature to determine the quality of the LSI.
As a background art in this field, for example, there is a technology as in patent document 1. Patent document 1 discloses "a wafer burn-in test method in which the voltage level supplied to the gate of a column switch is changed in accordance with the lattice write level". (claim 1 of patent document 1).
Further, patent document 2 discloses "a semiconductor integrated circuit device having an analog circuit built therein, including: a voltage circuit in which an output voltage is changed in accordance with an input voltage value switching signal; and a switching element provided between an output of the voltage circuit and an analog signal input terminal of the analog circuit. (paragraph [0009] of patent document 2)
Documents of the prior art
Patent document
Patent document 1: japanese laid-open patent publication No. 2007-157282
Patent document 2: japanese patent laid-open No. 2008-32448
Disclosure of Invention
Problems to be solved by the invention
However, when an analog circuit is mounted in an on-vehicle LSI, a diagnostic circuit for diagnosing the analog circuit is generally arranged as a pair with the analog circuit in order to ensure high reliability.
When wafer level burn-in (WLBI) is performed on an LSI in which a diagnostic circuit is disposed, if a signal input PAD is in a released state, the diagnostic circuit operates, the internal state is fixed, the activation rate of a digital signal processing unit (DSP) decreases, and the quality of burn-in screening (determination of the quality of the LSI) decreases.
On the other hand, in the case of adding voltage application pins to the WLBI jig (WLBI probe) for wafer level burn-in (WLBI), the cost of the WLBI jig (WLBI probe) is increased.
In patent document 1, the memory peripheral circuit (sensing system circuit) is set to be aged without applying an excessively high voltage thereto, but there is no description of a problem associated with the operation of the diagnostic circuit during the above-described wafer level aging.
Further, in patent document 2, the input of the analog circuit is provided with a switch and a selection signal for switching between the burn-in and the normal operation, and the output of the voltage circuit is switched from the output of the voltage value switching signal generation circuit generated by the internal signal DINn _ n and/or the clock CLK and input to the analog circuit, but the purpose of switching the voltage is not described, and similarly to patent document 1, there is no description about the problem associated with the operation of the diagnostic circuit in the burn-in at the wafer level.
Accordingly, an object of the present invention is to provide a semiconductor integrated circuit device including an analog circuit and a diagnostic circuit thereof, in which the diagnostic circuit is not operated during wafer-level burn-in, the activation rate of a DSP is increased, and the quality of burn-in screening can be improved, and a semiconductor integrated circuit device inspection method.
Means for solving the problems
In order to solve the above problem, the present invention provides a semiconductor integrated circuit device including: an analog circuit; a diagnostic circuit that detects an abnormality on an input side of the analog circuit; a digital signal processing unit connected to an output side of the analog circuit; a voltage generation circuit connected to an input side of the analog circuit and capable of generating a plurality of voltages; and a switch circuit provided between the analog circuit and the voltage generation circuit, the switch circuit being turned on when an aging switching signal is input, the voltage generation circuit outputting a plurality of voltages that do not cause the diagnostic circuit to function.
In addition, the present invention provides a semiconductor integrated circuit device including: an analog circuit; a diagnostic circuit that detects an abnormality on an input side of the analog circuit; a digital signal processing unit connected to an output side of the analog circuit; a voltage generation circuit connected to an input side of the analog circuit and capable of generating a plurality of voltages; and a switch circuit provided between the analog circuit and the voltage generation circuit, which is turned on when an aging switching signal is input, and the diagnostic circuit stops its function when the aging switching signal is input.
Effects of the invention
According to the present invention, it is possible to realize a semiconductor integrated circuit device including an analog circuit and a diagnostic circuit thereof, in which the diagnostic circuit is not operated at the time of wafer level burn-in, and burn-in screening quality can be improved, and a method of inspecting the semiconductor integrated circuit device.
Problems, structures, and effects other than those described above will become apparent from the following description of the embodiments.
Drawings
Fig. 1 is a diagram showing a circuit configuration of a semiconductor integrated circuit device according to embodiment 1.
Fig. 2 is a timing chart showing the operation of the semiconductor integrated circuit device of example 1.
Fig. 3 is a view showing a modification (first modification) of fig. 1.
Fig. 4 is a diagram showing a circuit configuration of the voltage generation circuit of fig. 1.
Fig. 5 is a view showing a modification (first modification) of fig. 4.
Fig. 6 is a diagram showing a modification (second modification) of fig. 4.
Fig. 7 is a view showing a modification (third modification) of fig. 4.
Fig. 8 is a diagram showing a modification (fourth modification) of fig. 4.
Fig. 9 is a view showing a modification (second modification) of fig. 1.
Fig. 10 is a diagram showing a circuit configuration of a semiconductor integrated circuit device according to embodiment 2.
Fig. 11 is a diagram showing a circuit configuration of a semiconductor integrated circuit device according to embodiment 3.
Fig. 12 is a diagram showing a circuit configuration of a semiconductor integrated circuit device according to embodiment 4.
Detailed Description
Hereinafter, embodiments of the present invention will be described with reference to the drawings. In the drawings, the same components are denoted by the same reference numerals, and detailed description of overlapping portions is omitted.
Example 1
The structure of a semiconductor integrated circuit device and a method for inspecting the same according to embodiment 1 of the present invention will be described with reference to fig. 1 to 9. Fig. 1 is a circuit configuration diagram of a semiconductor integrated circuit device of the present embodiment.
As shown in fig. 1, the semiconductor integrated circuit device of the present embodiment includes: an analog circuit connected to an external connection terminal, i.e., a PAD electrode; a diagnostic circuit having one end connected to an input side A _ IN of the analog circuit and detecting an abnormality on the input side of the analog circuit; a digital signal processing part DSP connected with the output side of the analog circuit and the other end of the diagnosis circuit; a voltage generation circuit connected to an input side of the analog circuit and generating a plurality of voltages V1 and V2; an aging switching circuit which is arranged between the analog circuit and the voltage generating circuit and generates and outputs an aging switching signal MODE _ SEL; and a switch circuit which is turned on when the aging switching signal MODE _ SEL is input.
The voltage switching circuit includes an output voltage switching signal generating circuit that generates an output voltage switching signal V _ SEL for switching a plurality of voltages V1 and V2 output from the voltage generating circuit, outputs the output voltage switching signal V _ SEL to a switching circuit disposed in each of the plurality of voltages V1 and V2, and switches the voltages supplied to the analog circuit and the diagnostic circuit by ON/OFF controlling the switching circuit in each of the voltages V1 and V2. In fig. 1, the output voltage switching signal V _ SEL is output to the switch circuit at the voltage V2 line via the NOT circuit.
In a normal operation of the semiconductor integrated circuit device, when an abnormality on the input side of the analog circuit is detected, the diagnostic circuit outputs an abnormality detection signal Failure _ DET to the digital signal processing unit DSP. The input signal D _ IN is input from the analog circuit to the digital signal processing unit DSP.
Fig. 2 is a timing chart showing an operation when the semiconductor integrated circuit device of fig. 1 is inspected by wafer level burn-in (WLBI). IN fig. 2, the aging switching signal MODE _ SEL, the output voltage switching signal V _ SEL, the input side voltage a _ IN of the analog circuit, and the input signal D _ IN to the digital signal processing unit DSP are shown IN this order from the top, and the horizontal axis shows Time (Time).
As shown IN the graph of the input-side voltage a _ IN of the analog circuit IN fig. 2, IN the wafer level burn-IN (WLBI) of the semiconductor integrated circuit device of the present embodiment, a plurality of voltages V1, V2 that do not cause the diagnostic circuit to function are generated.
At the time of aging, the input side voltage a _ IN of the analog circuit is switched from the external connection terminal (PAD electrode) to the output voltage from the voltage generation circuit by the aging switching circuit. The voltage generation circuit does not operate a diagnostic circuit connected to the input side of the analog circuit, generates a plurality of voltages V1 and V2 that change the output of the analog circuit, and switches the input voltage of the analog circuit by an output voltage switching switch (switching circuit).
When the diagnostic circuit does not operate and the output of the analog circuit changes, the input of the digital signal processing unit DSP transitions to normal, and the internal activation rate of the digital signal processing unit DSP increases in accordance with the transition of the input.
According to the present embodiment shown in fig. 1 and 2, in the case of burn-in, by switching the plurality of voltages V1 and V2 that do not operate the diagnostic function and inputting them to the analog circuit, it is possible to eliminate the voltage application terminal on the burn-in jig (the jig for WLBI) and to improve the internal activation rate by switching the input of the digital signal processing unit DSP.
Fig. 3 is a view showing a first modification of fig. 1. In fig. 3, the voltage generation circuit is also used as a reference Voltage (VREF) generation circuit required for the analog circuit. The voltage generation circuit generates a plurality of voltages V1, V2, and generates a reference Voltage (VREF) required for the analog circuit.
As shown in fig. 3, by using the voltage generation circuit as the reference Voltage (VREF) generation circuit as well, it is not necessary to design the reference Voltage (VREF) generation circuit, and the chip size of the semiconductor integrated circuit device (LSI) can be reduced.
Fig. 4 to 8 show specific circuit configuration examples of the voltage generation circuit of fig. 1. Fig. 5, 6, 7, and 8 show a first modification, a second modification, a third modification, and a fourth modification of fig. 4, respectively.
The voltage generation circuit shown in fig. 4 is configured by a power supply potential VCC, a ground potential GND, and a plurality of resistance elements R1 to R3, and generates a first output voltage (V1) and a second output voltage (V2) by resistance-voltage-dividing of the power supply potential VCC by the plurality of resistance elements R1 to R3.
The voltage generation circuit shown in fig. 5 includes a switch circuit connected in series between a power supply potential VCC and a plurality of resistance elements R1 to R3. The switching circuit is composed of an NMOS transistor, a PMOS transistor, or both of them, and is turned ON/OFF by the aging switching signal MODE _ SEL and is turned OFF during normal operation, thereby preventing unnecessary current from flowing during normal operation.
The voltage generation circuit shown in fig. 6 includes a constant voltage output circuit such as a regulator or a Band Gap Reference (BGR) circuit connected in series between a power supply potential VCC and a plurality of resistance elements R1 to R3. The output of the constant voltage output circuit is divided to generate a first output voltage (V1) and a second output voltage (V2).
The voltage generation circuit shown in fig. 7 includes a constant voltage output circuit such as a regulator or a Band Gap Reference (BGR) circuit connected in series between a power supply potential VCC and a plurality of resistance elements R1 and R2. The constant voltage output circuit outputs a first output voltage (V1), and generates a second output voltage (V2) by resistance division of the first output voltage (V1) by a plurality of resistance elements R1 and R2.
The voltage generation circuit shown in fig. 8 includes an output voltage switching signal generation circuit that switches outputs of a plurality of voltages V1 and V2, and the output voltage switching signal generation circuit is configured by a clock signal (internal CLK) and a frequency divider in the semiconductor integrated circuit device. The frequency divider divides a clock signal (internal CLK) in the semiconductor integrated circuit device into frequencies lower than the operating frequency of the analog circuit.
Fig. 9 is a diagram showing a second modification of fig. 1. While the voltage generation circuit in fig. 1 outputs the plurality of voltages V1, V2 that do not cause the diagnostic circuit to function, in the configuration of fig. 9, the aging switching signal MODE _ SEL is directly output from the aging switching circuit to the diagnostic circuit. The diagnostic circuit stops its function when the aging switching signal MODE _ SEL is input.
As described above, according to the present embodiment, when wafer level burn-in (WLBI) is performed, the input of the analog circuit is switched to a voltage at which the diagnostic circuit mounted inside the LSI is not operated, thereby preventing the internal state from being fixed by the diagnostic circuit,
by generating a plurality of voltages V1 and V2 and switching the input voltages, the activation rate of internal circuits such as a digital signal processor DSP can be improved.
Example 2
The structure of a semiconductor integrated circuit device according to embodiment 2 of the present invention will be described with reference to fig. 10.
Fig. 10 is a circuit configuration diagram of the semiconductor integrated circuit device of the present embodiment.
As shown in fig. 10, the semiconductor integrated circuit device of the present embodiment is different from the semiconductor integrated circuit device of embodiment 1 (fig. 1) in that it has a plurality of analog circuits and a plurality of diagnostic circuits, which are connected in parallel to a voltage generating circuit, respectively. That is, in the present embodiment, one voltage generation circuit is shared among a plurality of analog circuits and diagnostic circuits.
As shown in the present embodiment, each of the analog circuits has a diagnostic function, and by configuring to generate and apply voltages V1 and V2 that do not operate the diagnostic function of each analog circuit to a plurality of analog circuits to which an external connection terminal (PAD electrode) is input, it is possible to reduce (reduce) the chip size of a semiconductor integrated circuit device (LSI) without designing a voltage generating circuit, as compared with a case where a voltage generating circuit is provided to each of the plurality of analog circuits and the diagnostic circuit.
Example 3
The structure of a semiconductor integrated circuit device according to embodiment 3 of the present invention will be described with reference to fig. 11.
Fig. 11 is a circuit configuration diagram of the semiconductor integrated circuit device of the present embodiment.
The semiconductor integrated circuit device of the present embodiment is different from the semiconductor integrated circuit device of embodiment 2 (fig. 10) in that the voltage generation circuit generates the plurality of voltage groups V1, V2, V3, and V4 having the largest activation rates of the digital signal processing units for each of the plurality of analog circuits and the plurality of diagnostic circuits, as shown in fig. 11.
As shown in the present embodiment, each of the analog circuits having the diagnostic function and having the external connection terminal (PAD electrode) as an input is supplied with the voltage set V1, V2, V3, V4 having the highest activation rate, that is, the most suitable voltage is supplied to the plurality of analog circuits, by generating and supplying the voltage set V1, V2, V3, V4 having the highest activation rate for each of the analog circuits, whereby the activation rate of the digital signal processing unit DSP is improved and the burn-in quality is improved.
Example 4
The structure of a semiconductor integrated circuit device according to embodiment 4 of the present invention will be described with reference to fig. 12.
Fig. 12 is a circuit configuration diagram of the semiconductor integrated circuit device of the present embodiment.
The semiconductor integrated circuit device of the present embodiment is different from the semiconductor integrated circuit device of embodiment 1 (fig. 1) in that a switch circuit for cutting off an input signal inputted from an external connection terminal (PAD electrode) is provided between the external connection terminal (PAD electrode) and an analog circuit, as shown in fig. 12.
As shown in this embodiment, by disposing a switch circuit for cutting OFF an input signal input from the external connection terminal (PAD electrode) between the external connection terminal (PAD electrode) and the analog circuit, even when an external input signal such as a sensor input is input from the external connection terminal (PAD electrode), the switch circuit can be ON/OFF controlled by the aging switch signal MODE _ SEL, whereby the input signal input from the external connection terminal (PAD electrode) can be invalidated, and the voltages V1 and V2 from the voltage generation circuit can be switched.
The present invention is not limited to the above-described embodiments, and various modifications are also included.
For example, the above-described embodiments are for describing the present invention in detail so as to facilitate understanding of the present invention, and do not necessarily have to have all the structures described. Further, a part of the structure of any embodiment may be replaced with the structure of another embodiment, or the structure of another embodiment may be added to the structure of any embodiment. Further, a part of the configuration of each embodiment may be added, deleted, or replaced with another configuration.
Description of the reference numerals
DSP … digital signal processing part
VCC … supply potential
R1, R2, R3 … resistance element
BGR … bandgap reference (circuit).
Claims (13)
1. A semiconductor integrated circuit device, comprising:
an analog circuit;
a diagnostic circuit that detects an abnormality on an input side of the analog circuit;
a digital signal processing unit connected to an output side of the analog circuit;
a voltage generation circuit connected to an input side of the analog circuit and capable of generating a plurality of voltages; and
a switching circuit provided between the analog circuit and the voltage generation circuit, which is turned on when an aging switching signal is input,
the voltage generation circuit outputs a plurality of voltages that do not cause the diagnostic circuit to function.
2. The semiconductor integrated circuit device according to claim 1, wherein:
the voltage generation circuit generates a reference Voltage (VREF) required by the analog circuit.
3. The semiconductor integrated circuit device according to claim 1, wherein:
the voltage generation circuit is composed of a power supply potential, a ground potential, and a plurality of resistance elements,
the power supply potential is resistance-divided by the plurality of resistance elements to generate a first output voltage (V1) and a second output voltage (V2).
4. The semiconductor integrated circuit device according to claim 3, wherein:
the voltage generation circuit has a switching circuit connected in series between the power supply potential and the plurality of resistance elements.
5. The semiconductor integrated circuit device according to claim 3, wherein:
the voltage generation circuit has a constant voltage output circuit of a regulator or a Band Gap Reference (BGR) circuit connected in series between the power supply potential and the plurality of resistance elements,
dividing an output of the constant voltage output circuit to generate the first output voltage (V1) and the second output voltage (V2).
6. The semiconductor integrated circuit device according to claim 1, wherein:
the voltage generation circuit is composed of a power supply potential, a ground potential, and a plurality of resistance elements,
a constant voltage output circuit having a regulator or a Band Gap Reference (BGR) circuit connected in series between the power supply potential and the plurality of resistance elements,
the constant voltage output circuit outputs a first output voltage (V1),
the first output voltage (V1) is resistance-divided by the plurality of resistance elements to generate a second output voltage (V2).
7. The semiconductor integrated circuit device according to claim 1, wherein:
the voltage generation circuit has an output voltage switching signal generation circuit that switches outputs of the plurality of voltages,
the output voltage switching signal generation circuit is configured by a clock signal and a frequency divider in the semiconductor integrated circuit device.
8. A semiconductor integrated circuit device, comprising:
an analog circuit;
a diagnostic circuit that detects an abnormality on an input side of the analog circuit;
a digital signal processing unit connected to an output side of the analog circuit;
a voltage generation circuit connected to an input side of the analog circuit and capable of generating a plurality of voltages; and
a switching circuit provided between the analog circuit and the voltage generation circuit, which is turned on when an aging switching signal is input,
the diagnostic circuit stops its function when the aging switch signal is input.
9. The semiconductor integrated circuit device according to claim 1, wherein:
each having a plurality of said analog circuits and said diagnostic circuits,
the plurality of analog circuits and the diagnostic circuit are each connected in parallel with the voltage generation circuit.
10. The semiconductor integrated circuit device according to claim 9, wherein:
the voltage generation circuit generates a voltage group having the largest activation rate of the digital signal processing section for each of the plurality of analog circuits and the diagnostic circuit.
11. The semiconductor integrated circuit device according to claim 1, comprising:
an external connection terminal; and
and a switch circuit for cutting off an input signal inputted from the external connection terminal between the external connection terminal and the analog circuit.
12. A method for inspecting a semiconductor integrated circuit device having an analog circuit and a diagnostic circuit built therein, the method comprising:
the inspection is a burn-in screen based on wafer level burn-in,
inputting a voltage that does not cause the diagnostic circuit to function to the analog circuit and the diagnostic circuit at the time of the wafer level burn-in.
13. The inspection method of a semiconductor integrated circuit device according to claim 12, wherein:
the voltage at which the diagnostic circuit does not function is the voltage at which the activation rate of the digital signal processing unit is maximized.
Applications Claiming Priority (3)
| Application Number | Priority Date | Filing Date | Title |
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| JP2019-081653 | 2019-04-23 | ||
| JP2019081653 | 2019-04-23 | ||
| PCT/JP2020/015285 WO2020217925A1 (en) | 2019-04-23 | 2020-04-03 | Semiconductor integrated circuit device and inspection method for semiconductor integrated circuit device |
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| CN113711065A true CN113711065A (en) | 2021-11-26 |
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| US (1) | US11808807B2 (en) |
| JP (1) | JP7179165B2 (en) |
| CN (1) | CN113711065A (en) |
| WO (1) | WO2020217925A1 (en) |
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Citations (10)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| DE19706534A1 (en) * | 1996-11-05 | 1998-05-07 | Mitsubishi Electric Corp | Semiconductor device capable of externally and quickly identifying a set port addition function, and a method of identifying an internal function of a semiconductor device |
| JPH10303371A (en) * | 1997-04-25 | 1998-11-13 | Sony Corp | Semiconductor integrated circuit |
| JP2004012180A (en) * | 2002-06-04 | 2004-01-15 | Matsushita Electric Ind Co Ltd | Semiconductor integrated circuit device |
| US20050030056A1 (en) * | 2003-06-25 | 2005-02-10 | From Thirty Incorporated | Apparatus for measuring VS parameters in a wafer burn-in system |
| JP2005121399A (en) * | 2003-10-15 | 2005-05-12 | Matsushita Electric Ind Co Ltd | Burn-in system and burn in test method |
| CN101111776A (en) * | 2005-01-27 | 2008-01-23 | 松下电器产业株式会社 | Semiconductor integrated circuit and system lsi |
| CN101165503A (en) * | 2006-10-20 | 2008-04-23 | 松下电器产业株式会社 | Semiconductor ic and testing method thereof |
| US20090267628A1 (en) * | 2008-02-26 | 2009-10-29 | Nec Electronics Corporation | Circuit board test system and test method |
| CN101825900A (en) * | 2009-03-06 | 2010-09-08 | 株式会社日立制作所 | The trouble-shooter of multi-channel analog input/output circuit and method for diagnosing faults |
| CN107229010A (en) * | 2016-03-25 | 2017-10-03 | 精工爱普生株式会社 | Circuit, detection means, oscillator, electronic equipment, moving body and detection method |
Family Cites Families (13)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2922733B2 (en) | 1992-10-14 | 1999-07-26 | 三菱電機株式会社 | Hybrid integrated circuit device |
| WO2002014883A2 (en) * | 2000-08-10 | 2002-02-21 | Xilinx, Inc. | Analog signal testing circuit and -method |
| DE10145299A1 (en) * | 2001-09-14 | 2003-04-03 | Bosch Gmbh Robert | Procedure for the automatic calculation of optimal routes |
| US6925408B2 (en) * | 2003-09-08 | 2005-08-02 | Texas Instruments Incorporated | Mixed-signal core design for concurrent testing of mixed-signal, analog, and digital components |
| JP2006234577A (en) | 2005-02-24 | 2006-09-07 | Sharp Corp | Semiconductor integrated circuit and its test method |
| JP2007157282A (en) | 2005-12-07 | 2007-06-21 | Elpida Memory Inc | Wafer burn-in test method, wafer burn-in test apparatus, and semiconductor storage device |
| JP2007163301A (en) | 2005-12-14 | 2007-06-28 | Matsushita Electric Ind Co Ltd | Burn-in test signal generation circuit and burn-in test method |
| JP2008032448A (en) | 2006-07-27 | 2008-02-14 | Matsushita Electric Ind Co Ltd | Semiconductor integrated circuit device |
| JP2008172097A (en) | 2007-01-12 | 2008-07-24 | Matsushita Electric Ind Co Ltd | Semiconductor integrated circuit |
| JP2009053130A (en) | 2007-08-29 | 2009-03-12 | Nec Electronics Corp | Semiconductor device |
| JP2010203898A (en) | 2009-03-03 | 2010-09-16 | Renesas Electronics Corp | Semiconductor device test circuit, semiconductor device, and method for manufacturing the same |
| JP5581960B2 (en) | 2010-10-14 | 2014-09-03 | 凸版印刷株式会社 | Semiconductor device |
| JP6130131B2 (en) | 2012-12-06 | 2017-05-17 | 三菱日立パワーシステムズ株式会社 | Control device for two-shaft gas turbine and two-shaft gas turbine having the same |
-
2020
- 2020-04-03 JP JP2021515933A patent/JP7179165B2/en active Active
- 2020-04-03 US US17/594,431 patent/US11808807B2/en active Active
- 2020-04-03 WO PCT/JP2020/015285 patent/WO2020217925A1/en active Application Filing
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Patent Citations (10)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| DE19706534A1 (en) * | 1996-11-05 | 1998-05-07 | Mitsubishi Electric Corp | Semiconductor device capable of externally and quickly identifying a set port addition function, and a method of identifying an internal function of a semiconductor device |
| JPH10303371A (en) * | 1997-04-25 | 1998-11-13 | Sony Corp | Semiconductor integrated circuit |
| JP2004012180A (en) * | 2002-06-04 | 2004-01-15 | Matsushita Electric Ind Co Ltd | Semiconductor integrated circuit device |
| US20050030056A1 (en) * | 2003-06-25 | 2005-02-10 | From Thirty Incorporated | Apparatus for measuring VS parameters in a wafer burn-in system |
| JP2005121399A (en) * | 2003-10-15 | 2005-05-12 | Matsushita Electric Ind Co Ltd | Burn-in system and burn in test method |
| CN101111776A (en) * | 2005-01-27 | 2008-01-23 | 松下电器产业株式会社 | Semiconductor integrated circuit and system lsi |
| CN101165503A (en) * | 2006-10-20 | 2008-04-23 | 松下电器产业株式会社 | Semiconductor ic and testing method thereof |
| US20090267628A1 (en) * | 2008-02-26 | 2009-10-29 | Nec Electronics Corporation | Circuit board test system and test method |
| CN101825900A (en) * | 2009-03-06 | 2010-09-08 | 株式会社日立制作所 | The trouble-shooter of multi-channel analog input/output circuit and method for diagnosing faults |
| CN107229010A (en) * | 2016-03-25 | 2017-10-03 | 精工爱普生株式会社 | Circuit, detection means, oscillator, electronic equipment, moving body and detection method |
Non-Patent Citations (2)
| Title |
|---|
| M.S. BAKIR: "Sea of Leads (SoL) ultrahigh density wafer-level chip input/output interconnections for gigascale integration (GSI)", IEEE TRANSACTIONS ON ELECTRON DEVICES, vol. 50, no. 10, pages 2039 - 2048, XP001172251, DOI: 10.1109/TED.2003.816528 * |
| 齐本胜: "新一代大规模集成电路高温动态老化 测试系统的研制", 电子测量与仪器学报, vol. 16, no. 2, pages 5 - 9 * |
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| Publication number | Publication date |
|---|---|
| WO2020217925A1 (en) | 2020-10-29 |
| US11808807B2 (en) | 2023-11-07 |
| US20220187363A1 (en) | 2022-06-16 |
| JPWO2020217925A1 (en) | 2020-10-29 |
| JP7179165B2 (en) | 2022-11-28 |
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