JP2008032448A - Semiconductor integrated circuit device - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To execute a wafer-level burn-in test even if a semiconductor integrated circuit has a plurality of built-in analog circuits while reducing the input terminal number necessary for input of test signal without increase in chip size. <P>SOLUTION: The semiconductor integrated circuit device includes a first switch element 102 provided between an analog input terminal AIN of an analog circuit 10 and an analog power supply terminal AVDD, a second switch element 103 provided between the analog input terminal AIN and an analog ground terminal AVSS, and a switch element switching control circuit 104 for controlling ON/OFF operation of the first switch element 102 and the second switch element 103. In the wafer-level burn-in test, the first switch element 102 and the second switch element 103 are controlled by the control circuit 104 so as to be alternately ON. <P>COPYRIGHT: (C)2008,JPO&INPIT

Description

  The present invention relates to a semiconductor integrated circuit device incorporating an analog circuit, and to a technique for applying a burn-in load to the built-in analog circuit.

  A semiconductor integrated circuit device incorporating an analog circuit may be subjected to a burn-in test at the wafer level (hereinafter referred to as a wafer level burn-in test).

  Conventional semiconductor integrated circuit devices with built-in analog circuits are usually subjected to a wafer level burn-in test by inputting a signal waveform from an analog input terminal provided externally by, for example, an external tester (wafer level burn-in test device). Done.

As another technique, in order to test an analog circuit with relatively high accuracy, a test circuit for inspecting a resistor element, a capacitor element, a switch element, and an analog circuit is configured inside the semiconductor integrated circuit device, and an external tester is provided. In some cases, an analog circuit is inspected without using (see, for example, Patent Document 1).
JP 2002-107424 A

  However, there is an upper limit on the number of terminals that can be used per chip due to the limitations of the wafer level burn-in test apparatus. Therefore, if the chip size is reduced, the number of terminals that can be used per chip is reduced. On the other hand, as the number of built-in analog circuits increases, the number of terminals required for testing increases. That is, if a signal waveform is input from an external analog input terminal, it may be difficult to assign a necessary terminal during the wafer level burn-in test.

  In addition, in a semiconductor integrated circuit device configured with a test circuit for inspecting a resistor element, a capacitor element, a switch element, and an analog circuit in order to reduce the number of test terminals required for the test and test the analog circuit with relatively high accuracy Although the wafer level burn-in test can be realized, the test circuit is configured to test the analog circuit with relatively high accuracy, so that the chip size increases.

  The present invention has been made by paying attention to the above-mentioned problem. Even if there are a plurality of built-in analog circuits while reducing the number of input terminals required for test signal input without increasing the chip size, wafer level burn-in is performed. An object of the present invention is to provide a semiconductor integrated circuit device capable of performing a test.

In order to solve the above problems, one embodiment of the present invention provides:
A semiconductor integrated circuit device including an analog circuit that operates by inputting a first power source and a second power source,
A first switch element provided between an analog signal input terminal of the analog circuit and the first power supply;
A second switch element provided between the analog signal input terminal of the analog circuit and the second power supply;
A switch element switching control circuit for controlling on / off operations of the first switch element and the second switch element;
The switch element switching control circuit is configured to alternately turn on the first switch element and the second switch element in accordance with an input switch element switching signal.

One embodiment of the present invention includes
A semiconductor integrated circuit device incorporating an analog circuit,
A voltage circuit that varies a voltage to be output in accordance with an input voltage value switching signal;
A switch element provided between the output of the voltage circuit and the analog signal input terminal of the analog circuit;
It is provided with.

  According to the present invention, it is possible to carry out a wafer level burn-in test even when there are a plurality of built-in analog circuits while reducing the number of input terminals required for test signal input without increasing the chip size.

  Hereinafter, embodiments of the present invention will be described with reference to the drawings. In the following description of each embodiment, components having the same functions as those described once are given the same reference numerals and description thereof is omitted.

Embodiment 1 of the Invention
FIG. 1 is a block diagram showing a configuration of a semiconductor integrated circuit device 100 according to Embodiment 1 of the present invention. As shown in FIG. 1, the semiconductor integrated circuit device 100 includes an analog circuit 101, a first switch element 102, a second switch element 103, and a switch element switching control circuit 104. The semiconductor integrated circuit device 100 is provided with an analog input terminal AIN, an analog ground terminal AVSS, and an analog power supply terminal AVDD as terminals connected to the outside.

  The analog circuit 101 is an analog circuit such as an AD converter (ADC) built in the semiconductor integrated circuit device 100. An analog signal is input to the analog circuit 101 via an analog input terminal AIN, and power is supplied via an analog power supply terminal AVDD and an analog ground terminal AVSS.

  The first switch element 102 is a switch element provided between the analog power supply terminal AVDD and the analog input terminal AIN. The first switch element 102 is controlled to be turned on / off by a switch element switching control circuit 104. In the present embodiment, the first switch element 102 is configured to be turned on when the signal input from the switch element switching control circuit 104 is “1” (set to H level).

  The second switch element 103 is a switch element provided between the analog input terminal AIN and the analog ground terminal AVSS. The second switch element 103 is also controlled to be turned on / off by the switch element switching control circuit 104. In the present embodiment, the second switch element 103 is configured to be turned on when the signal input from the switch element switching control circuit 104 is “1”.

  The switch element switching control circuit 104 outputs a switch element switching signal for controlling on / off of each of the first switch element 102 and the second switch element 103 in accordance with the input switch element switching signal DINin. ing. Further, the selection signal SEL is input to the switch element switching control circuit 104, and the switch element switching signal becomes valid or invalid according to the selection signal SEL.

  Specifically, the switch element switching control circuit 104 includes an inverter 104a, a buffer 104b, a selector 104c, and a selector 104d.

  The inverter 104a inverts the logic of the switch element switching signal DINin and outputs it. Further, the buffer 104b outputs the input switch element switching signal DINin with the logic as it is.

  The selector 104c receives the output of the inverter 104a (referred to as a second switch element switching signal), and outputs the second switch element switching signal to the second switch element 103 in response to the selection signal SEL. Whether to do is switched.

  The selector 104d receives the output of the buffer 104b (referred to as a first switch element switching signal), and outputs the first switch element switching signal to the first switch element 102 in response to the selection signal SEL. Whether to do is switched.

  With the above configuration, the switch element switching control circuit 104 performs control so that the first switch element 102 and the second switch element 103 are alternately turned on.

  When a wafer level burn-in test is performed on the semiconductor integrated circuit device 100, first, the switch signal switching control is performed on the selection signal SEL so that the switching signals for the first switch element and the second switch element are valid. Input to the circuit 104. Further, as the switch element switching signal DINin, for example, the switch element switching signal DINin having the waveform shown in FIG. 2 is transmitted from the outside of the semiconductor integrated circuit device 100 to the switch element switching control circuit 104. Thus, when the switch element switching signal DINin is “1” (set to H level), the first switch element 102 is turned on, and the switch element switching signal DINin is set to “0” (set to L level). At this time, the second switch element 103 is turned on. When the first switch element 102 is conductive, a voltage is transmitted from the analog power supply terminal AVDD to the analog circuit 101 via the first switch element 102. Further, when the second switch element 103 is conductive, a voltage is transmitted from the analog ground terminal AVSS to the analog circuit 101 via the second switch element 103.

  As described above, the test signal AINin can be generated according to the switch element switching signal DINin as shown in FIG. This test signal AINin is transmitted to the analog circuit 101 and a wafer level burn-in test is performed.

  As described above, according to the present embodiment, since a predetermined test signal is generated by a relatively simple test circuit provided in the semiconductor integrated circuit device 100, the analog circuit is used without using the analog input terminal AIN. A test signal can be input to 101. Therefore, the number of input terminals necessary for test signal input can be reduced. Therefore, even when the chip size is small and a plurality of analog circuits 101 are built in, a wafer level burn-in test can be performed without being limited to the number of terminals that can be allocated for testing. become. In addition, since the burn-in load is simplified and the test circuit is configured with a relatively simple circuit, an increase in chip size can be suppressed.

<< Embodiment 2 of the Invention >>
FIG. 3 is a block diagram showing a configuration of the semiconductor integrated circuit device 200 according to the second embodiment of the present invention. As shown in FIG. 3, the semiconductor integrated circuit device 200 is configured by adding a switch element switching signal generation circuit 201 to the semiconductor integrated circuit device 100 of the first embodiment.

  The switch element switching signal generation circuit 201 generates a switch element switching signal DINin based on the clock signal CKin. The switch element switching signal generation circuit 201 is configured so that the pulse width of the switch element switching signal DINin can be varied.

  When a wafer level burn-in test is performed on the semiconductor integrated circuit device 200, first, the switch signal switching control is performed on the selection signal SEL so that the switch signals for the first switch element and the second switch element are valid. Input to the circuit 104.

  When the clock signal CKin is transmitted to the switch element switching signal generation circuit 201, the switch element switching signal generation circuit 201 generates the switch element switching signal DINin having a waveform shown in FIG. 4, for example, according to the clock signal CKin. Accordingly, when the switch element switching signal DINin is “1”, the first switch element 102 is turned on, and when the switch element switching signal DINin is “0”, the second switch element 103 is turned on. . When the first switch element 102 is conductive, a voltage is transmitted from the analog power supply terminal AVDD to the analog circuit 101 via the first switch element 102. Further, when the second switch element 103 is conductive, a voltage is transmitted from the analog ground terminal AVSS to the analog circuit 101 via the second switch element 103. That is, according to the switch element switching signal DINin, the test signal AINin can be generated as shown in FIG. This test signal AINin is transmitted to the analog circuit 101 and a wafer level burn-in test is performed.

  As described above, according to the present embodiment, the wafer level burn-in test can be performed without inputting the switch element switching signal DINin from the outside of the semiconductor integrated circuit device 200. Although the clock signal CKin is used to generate the switch element switching signal DINin, it is common to use the clock signal when operating the semiconductor integrated circuit device. The clock signal for 201 can be easily obtained. Therefore, the switch element switching signal DINin can be generated with a relatively simple circuit.

<< Embodiment 3 of the Invention >>
FIG. 5 is a block diagram showing a configuration of a semiconductor integrated circuit device 300 according to Embodiment 3 of the present invention. As shown in FIG. 5, the semiconductor integrated circuit device 300 includes an analog circuit 101, a switch element 301, and a voltage circuit 302.

  The switch element 301 is a switch element provided between the analog input terminal AIN and the voltage circuit 302. The switch element 301 receives a selection signal SEL, and is turned on / off by this signal. In the present embodiment, the switch element 301 is configured to be turned on when the selection signal SEL is “1”.

  The voltage circuit 302 outputs a voltage corresponding to the input voltage value switching signal DINin_n. In the present embodiment, the voltage value switching signal DINin_n is a value from 0 to 3. The voltage circuit 302 is configured so that the output voltage can be varied in four stages. As shown in FIG. 6, the voltage circuit 302 is configured to increase the output voltage each time the value of the voltage value switching signal DINin_n increases. ing.

  When performing a wafer level burn-in test on the semiconductor integrated circuit device 300, first, the selection signal SEL is input to the switch element 301 so that the switch element 301 is turned on. Further, for example, the voltage value switching signal DINin_n having the value shown in FIG. 6 is transmitted from the outside of the semiconductor integrated circuit device 100 to the voltage circuit 302. As a result, a test signal AINin whose voltage changes as shown in FIG. 6 is transmitted to the analog circuit 101, and a wafer level burn-in test is performed.

  As described above, also in the present embodiment, a predetermined test signal can be input to the analog circuit 101 without using the analog input terminal AIN, so that the number of input terminals required for test signal input can be reduced. Is possible.

<< Embodiment 4 of the Invention >>
FIG. 7 is a block diagram showing a configuration of a semiconductor integrated circuit device 400 according to Embodiment 4 of the present invention. As shown in FIG. 7, a voltage value switching signal generation circuit 401 is added to the semiconductor integrated circuit device 300 of the third embodiment.

  The voltage value switching signal generation circuit 401 receives the clock signal CKin, and generates a voltage value switching signal DINin_n according to the clock signal CKin. Specifically, as shown in FIG. 8, the voltage value switching signal generation circuit 401 increases the value of the voltage value switching signal DINin_n by 1 every time the clock signal CKin rises, and again when the value becomes “3”. It is configured to return to “0”. Thereby, a test signal AINin whose voltage changes as shown in FIG. 8 is generated.

  Therefore, according to the present embodiment, the wafer level burn-in test can be performed without inputting the voltage value switching signal DINin_n from the outside of the semiconductor integrated circuit device 400. Note that the clock signal CKin is used to generate the voltage value switching signal DINin_n. However, when the semiconductor integrated circuit device is operated, the clock signal is generally used, and the voltage value switching signal generation circuit is used. The clock signal for 401 can be easily obtained. Therefore, the switch element switching signal DINin can be generated with a relatively simple circuit.

<< Embodiment 5 of the Invention >>
FIG. 9 is a block diagram showing a configuration of a semiconductor integrated circuit device 500 according to the fifth embodiment of the present invention. The semiconductor integrated circuit device according to the fifth embodiment is an example in which, when digital data is output from the analog circuit 101 (when the analog circuit 101 is an AD converter, for example), the digital data is used to generate a test signal. is there. Specifically, the semiconductor integrated circuit device 500 selects a part (DOUTin_n) of the output of the analog circuit 101 in the semiconductor integrated circuit device 300 and inputs DOUTin_n to the voltage circuit 302 as the voltage value switching signal DINin_n. It is composed. That is, in the semiconductor integrated circuit device 500, the output of the voltage circuit 302 is fed back to the voltage circuit 302 via the analog circuit 101.

  When performing a wafer level burn-in test on the semiconductor integrated circuit device 500, first, the selection signal SEL is input to the switch element 301 so that the switch element 301 is turned on. When the switch element 301 is turned on, the output of the voltage circuit 302 is input to the analog circuit 101, and the analog circuit 101 outputs digital data having a value corresponding to the input. Part of the output (DOUTin_n) of the analog circuit 101 is input to the voltage circuit 302. As a result, the voltage output from the voltage circuit 302 changes, for example, as shown in FIG.

  As described above, according to the present embodiment, a test signal can be easily generated with a relatively simple circuit configuration.

  The semiconductor integrated circuit device according to the present invention can perform a wafer level burn-in test even when there are a plurality of built-in analog circuits while reducing the number of input terminals necessary for test signal input without increasing the chip size. It has the effect of becoming possible, and is useful as a semiconductor integrated circuit device or the like incorporating an analog circuit.

1 is a block diagram illustrating a configuration of a semiconductor integrated circuit device according to a first embodiment. FIG. 3 is a diagram illustrating waveforms of signals during a wafer level burn-in test of the semiconductor integrated circuit device according to the first embodiment. FIG. 6 is a block diagram illustrating a configuration of a semiconductor integrated circuit device according to a second embodiment. FIG. 6 is a diagram illustrating waveforms of signals during a wafer level burn-in test of a semiconductor integrated circuit device according to a second embodiment. FIG. 6 is a block diagram illustrating a configuration of a semiconductor integrated circuit device according to a third embodiment. It is a figure which shows the waveform of each signal at the time of the wafer level burn-in test of the semiconductor integrated circuit device which concerns on Embodiment 3. FIG. FIG. 10 is a block diagram illustrating a configuration of a semiconductor integrated circuit device according to a fourth embodiment. FIG. 10 is a diagram illustrating waveforms of signals during a wafer level burn-in test of a semiconductor integrated circuit device according to a fourth embodiment. FIG. 10 is a block diagram illustrating a configuration of a semiconductor integrated circuit device according to a fifth embodiment. FIG. 10 is a diagram showing waveforms of signals during a wafer level burn-in test of a semiconductor integrated circuit device according to a fifth embodiment.

Explanation of symbols

DESCRIPTION OF SYMBOLS 100 Semiconductor integrated circuit device 101 Analog circuit 102 1st switch element 103 2nd switch element 104 Switch element switching control circuit 104a Inverter 104b Buffer 104c Selector 104d Selector 200 Semiconductor integrated circuit device 201 Switch element switching signal generation circuit 300 Semiconductor integrated circuit Device 301 Switch element 302 Voltage circuit 400 Semiconductor integrated circuit device 401 Voltage value switching signal generation circuit 500 Semiconductor integrated circuit device

Claims (5)

A semiconductor integrated circuit device including an analog circuit that operates by inputting a first power source and a second power source,
A first switch element provided between an analog signal input terminal of the analog circuit and the first power supply;
A second switch element provided between the analog signal input terminal of the analog circuit and the second power supply;
A switch element switching control circuit for controlling on / off operations of the first switch element and the second switch element;
The switch element switching control circuit is configured to alternately turn on the first switch element and the second switch element in accordance with an input switch element switching signal. Integrated circuit device. The semiconductor integrated circuit device according to claim 1,
A switching element switching signal generating circuit for generating the switching element switching signal;
The switch element switching signal generation circuit is configured to be able to vary the pulse width of the switch element switching signal to be generated,
The switch element switching control circuit is configured to control a conduction time of the first switch element and the second switch element according to a pulse width of the switch element switching signal. Semiconductor integrated circuit device. A semiconductor integrated circuit device incorporating an analog circuit,
A voltage circuit that varies a voltage to be output in accordance with an input voltage value switching signal;
A switch element provided between the output of the voltage circuit and the analog signal input terminal of the analog circuit;
A semiconductor integrated circuit device comprising: The semiconductor integrated circuit device according to claim 3,
A semiconductor integrated circuit device, further comprising a voltage value switching signal generation circuit for generating the voltage value switching signal. The semiconductor integrated circuit device according to claim 3,
The semiconductor integrated circuit device, wherein the voltage circuit is configured such that an output of the analog circuit is fed back as the voltage value switching signal.

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