JP2000009808A - Semiconductor device and liquid crystal driving device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To perform a test on multi-pin output ICs without increasing the size of a semiconductor chip or probing an output terminal by performing the test on the output terminal through the use of the off-transistor of a circuit for preventing an electrostatic breakdown in a semiconductor device and a testing circuit. SOLUTION: An output terminal 11 is connected to the output of an output- stage transistor part 6 formed of a Pch transistor 4 to connect an IC power source VCC17 to a source and a control signal 10 to a gate and of a Nch transistor 5 to connect an IC power source VGND18 to the source and the control signal 10 to the gate and is connected to a circuit 3 for preventing electrostatic breakdown. The device 3 for preventing electrostatic breakdown is constituted of a Pch transistor 1 to connect the IC power source VCC17 to the source and a test signal 12 to the gate and of a Nch transistor 2 to connect the IC power source VGND18 to the source and a test signal 13 to the gate. The IC power sources VCC17 and VGND18 are supplied from an external power source 16 via ammeters 14 and 15 for test.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to a semiconductor device and a test circuit.

[0002]

2. Description of the Related Art A conventional test circuit for a semiconductor device performs a test by probing all output terminals,
As disclosed in JP-A-207050 and JP-A-7-99452, a dedicated test terminal for performing at least one probe is provided, and a dedicated test terminal for switching a plurality of outputs by a selection circuit and probing is shared. Was.

[0003]

In a conventional semiconductor device and test circuit, particularly in a liquid crystal driving device, when testing an output terminal, it is necessary to probe the output terminal to be tested. There was a phenomenon that the yield was lowered due to the failure due to the contact property of the wafer. Also, when testing a semiconductor device with multiple pins output, the probe card becomes complicated and expensive, and there is a problem that a tester corresponding to multiple pins output must be prepared.

[0004]

According to a first aspect of the present invention, there is provided a semiconductor device having an electrostatic discharge prevention circuit using an output off transistor in a semiconductor device, and a test circuit including an off transistor of the electrostatic discharge prevention circuit. It is characterized by comprising means for using

The semiconductor device described in Item 2 is characterized in that the semiconductor device includes a decoder for controlling a transistor of the electrostatic discharge protection circuit.

According to a third aspect of the present invention, there is provided a semiconductor device including means for driving a liquid crystal display device.

[0007]

In a conventional semiconductor device test, all output terminals are probed or a dedicated test terminal is provided and probed and monitored as shown in the conventional example. Thus, a semiconductor device and a test circuit capable of performing a test using an electrostatic protection transistor as a test circuit without probing the output terminal are provided.

[0008]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment of the present invention will be described below in detail.

(1) First Embodiment FIG. 1 shows an example of a semiconductor device according to the present invention. FIG.
FIG. 2 is a diagram illustrating an output stage transistor, an output terminal, and an electrostatic breakdown prevention circuit.

An output terminal 11 has a source connected to the IC power supply VCC17 and a Pch transistor 4 connecting the control signal 10 to the gate, a source connected to the IC power supply VGND18, and a control signal 1
The output of an output stage transistor section 6 comprising an Nch transistor 5 for connecting 0 to the gate and an electrostatic breakdown prevention circuit 3
It is connected to the. The electrostatic breakdown prevention circuit 3 includes a Pch transistor 1 that connects the IC power supply VCC17 to the source and the test signal 12 to the gate, and an Nch transistor 2 that connects the IC power supply VGND18 to the source and the test signal 13 to the gate. IC power supply VCC17, V
The GND 18 is supplied from an external power supply 16 via test ammeters 14 and 15.

Next, the operation of FIG. 1 will be described. In the following description, the “H” level is VCC17, and the “L” level is V
Represents GND18. During normal use, the Pch transistor 1 and the Nch transistor 2 of the electrostatic discharge protection circuit 3 are turned off, and the test signal 12 and the test signal 13 are respectively supplied to the VCC 17 and the VCC 17 so as to operate as the electrostatic discharge protection circuit.
VGND is fixed to the level 18 and each is an off transistor. At this time, the control signal 1 of the output stage transistor
When 0 is at “H” level, the Nch transistor 5 is turned on, the Pch transistor 4 is turned off, and the output terminal 11
GND18 level is output. Similarly, when the control signal 10 of the output stage transistor is at “L” level, Nch
The transistor 5 is turned off, the Pch transistor 4 is turned on, and the output terminal 11 outputs the VCC17 level.

At the time of testing the Pch transistor 4 as an output stage, the control signal 10 is set at "L" level and the test signal 1
2 and 13 are set to “H” level, respectively. At this time, the Pch transistor 4 controlled by the control signal 10 is on, N
The channel transistor 5 is turned off, and the Pch transistor 1 and the Nch transistor 2 controlled by the test signals 12 and 13 are turned off and on, respectively.
The level is selected, and the current from the VCC 17 flows to the test ammeter 15 and the external power supply 16 via the Pch transistor 4 and the Nch transistor 2. The Pch transistor 4 is tested by monitoring the test ammeter 15 at this time. At this time, the current flowing through the ammeter 15 is the sum of the current flowing through the ammeter 15 during normal operation and the current determined by the resistance of the power supply 16 and the Pch transistor 4 and the Nch transistor 2. Similarly,
At the time of testing the Nch transistor 5 as an output stage, the control signal 10 is set at "H" level, and the test signals 12 and 13 are set at "L" level. At this time, the Pch transistor 4 controlled by the control signal 10 is turned off, and the Nch transistor 5
Is turned on, and the Pch transistor 1 and the Nch transistor 2 controlled by the test signals 12 and 13 are turned off and on, respectively, so that the VGND 18 level is selected, and VGN 18 is selected.
The current to D18 is supplied from the external power supply 16 to the test ammeter 1
4, flows through the Pch transistor 1 and the Nch transistor 5 to the VGND 18. At this time, the current flowing through the ammeter 14 is the current flowing through the ammeter 14 during normal operation,
This is obtained by adding a current determined by the power supply 16 and the resistances of the Nch transistor 5 and the Pch transistor 1. By monitoring the test ammeter 14 at this time, N
A test of the channel transistor 5 is performed.

The detection of the failure of the Pch transistor 4 is based on the P
When the channel transistor 4 has failed and does not turn on, when the control signal 10 is at the “L” level, the test signal 12 is at the “H” level, and the test signal 13 is at the “L” level, the ammeter 1
5, the power supply 16, the Pch transistor 4 and the N
The failure can be detected because there is no increase in current determined by the resistance of the channel transistor 2. If the Pch transistor 4 does not turn off due to a failure, the control signal 10
Is at "H" level, the Pch transistor 4 outputs N
A failure can be detected by monitoring an increase in the current of the ammeter 15 in which a through current flows to the channel transistor 5. Similarly, when the Nch transistor 5 is not turned on due to a failure, the control signal 10 is at the “H” level, the test signal 12 is at the “L” level, and the test signal 13 is not detected.
Is at the “L” level, the ammeter 14 displays the power supply 16
And the Nch transistor 5 and the Pch transistor 1 have no current increase, and the failure can be detected. When the Nch transistor 5 has failed and is not turned off, the normal operation is performed and the control signal 10 is at "L" level. In addition, a failure can be detected by monitoring an increase in the current of the ammeter 14 in which a through current flows from the Pch transistor 4 to the Nch transistor 5.

(2) Second Embodiment FIG. 2 shows a second embodiment of the semiconductor device according to the present invention.
In the basic configuration in the example of FIG. 2, the description of the parts common to the embodiment of FIG. 1 is omitted. FIG. 2 is a diagram illustrating an output stage transistor, an output terminal, an electrostatic discharge protection circuit, and a decoder.

The decoder 32 receives the control signal 10 of the output stage transistor and an external test signal 31 as inputs.
It outputs test signals 12 and 13, and has a structure as shown in FIG. 3, for example.

Referring to FIG. The test signal 12, which is the output of the decoder 32, includes the output of the clocked inverter 37 to which the control signal 10 and the test signal 31 of the output stage transistor, which are the input signals of the decoder 32, and the source of the IC power VCC17. Is the output of the Pch transistor 34 connecting the gate to the gate. The test signal 13, which is the output of the other decoder,
The control signal 10, which is the input signal of the output stage transistor,
Clocked inverter 38 receiving test signal 31 as input
And the output of an Nch transistor 35 that connects the IC power supply VGND 18 as a source and a signal obtained by inverting the test signal 31 by an inverter 36 to a gate. Clocked inverters 37 and 38 are turned off when test signal 31 is at "H" level and turned off when test signal 31 is at "L" level. The decoder 32 shown in FIG. 3 operates in the test mode when the test signal 31 is at "H" level.
When in the "L" level, the normal operation mode is set. When the test signal 31 is at the “L” level, that is, in the normal operation mode, the clocked inverters 37 and 38 are both turned off regardless of the state of the control signal 10 and the test signal 31
, And an Nch transistor 35 receiving a signal obtained by inverting the test signal 31 by an inverter 36 are turned on, and the test signals 12 and 13 become “H” level and “L” level, respectively. .

The test signals 12 and 13 are gate signals of the Pch transistor 1 and the Nch transistor 2 of the ESD protection circuit, respectively.
The channel transistors 2 are turned off, and the off transistors are used as an electrostatic breakdown prevention circuit. Control signal 10 is "H"
When the level is at the level, the output stage transistors 4 and 5 are turned off and on, respectively, and the VGND 18 level is output to the output terminal 11. When the control signal 10 is at the “L” level, the output stage transistors 4 and 5 are turned on and off, respectively. And output terminal 1
1 is the VCC17 level. On the contrary,
When the test signal 31 is at “H” level, that is, in the test mode, the Pch transistor 34 and the Nch transistor 35 are both turned off, and the clocked inverter 3
7 and 38 are control signals 10 to operate the inverter.
Is at the “H” level, the test signals 12 and 13 are both at the “L” level, and the output stage Pch transistors 4 and Nch
Since the transistor 5 is turned off and on, respectively, VG
The ND18 level was selected, and the ammeter 1 was used as in the first embodiment.
4 is monitored to test the Nch transistor 5. Similarly, when the control signal 10 is at the "L" level, the test signals 12 and 13 are both at the "H" level, and the output stage transistors 4 and 5 are on and off, respectively, so that the VCC17 level is selected. The P-channel transistor 4 is tested by monitoring the ammeter 15 in the same manner as described above.

As a result, not only is it easy to select a test mode in accordance with the output level, but also the number of external test signal input terminals and wiring can be reduced, and the chip size can be further reduced.

(3) Third Embodiment FIG. 4 shows a third embodiment of the semiconductor device according to the present invention.
In the basic configuration in the example of FIG. 4, the description of the parts common to the embodiment of FIG. 1 is omitted.

FIG. 4 is a diagram showing an arbitrary set of a liquid crystal drive output transistor, a liquid crystal drive output terminal, and an electrostatic breakdown prevention circuit of an arbitrary set of a semiconductor device having n liquid crystal drive outputs. The output terminal 61 is a liquid crystal drive output transistor section comprising a Pch transistor 54 for connecting the liquid crystal drive power supply VON69 to the source and the control signal 60 to the gate, and an Nch transistor 55 for connecting the liquid crystal drive power supply VOFF70 to the source and the control signal 60 to the gate. The output 56 is connected to the electrostatic breakdown prevention circuit 53. The electrostatic breakdown prevention circuit 53 includes a Pch transistor 51 that connects the IC power supply VHIGH67 as a source and a test signal 62 to a gate,
The Nch transistor 52 connects the C power supply VGND 68 to the source and connects the test signal 63 to the gate. The IC power supplies VHIGH67 and VGND68 are supplied from an external power supply 66 via test ammeters 64 and 65.

Next, the operation of FIG. 4 will be described. As for the power supply levels, VHIGH67 is VON69 or higher, VON69 is higher than VOFF70, and VOFF70 is VGND68 or higher. The “H” level in the following description is VHI
GH67, “L” level indicates VGND68. During normal use, similarly to the first embodiment, the test signals 51 and 52 are VHIGH67 and VGN respectively so that the Pch transistor 51 and the Nch transistor 52 of the electrostatic discharge prevention circuit 53 are turned off and operate as the electrostatic discharge prevention circuit.
Each transistor is fixed to the level of D68 and each transistor is an off transistor. At this time, when the control signal 60 of the liquid crystal drive output transistor is at “H” level, the Nch transistor 5
5 turns on, the Pch transistor 54 turns off, and the liquid crystal drive output 61 outputs the level of VOFF 70. Similarly, when the control signal 60 of the liquid crystal drive output transistor is at “L” level, the Nch transistor 55 is turned off,
The Pch transistor 54 is turned on, and the liquid crystal drive output 61
Outputs the level of VON69.

Next, the operation at the time of the test will be described. When a test of an arbitrary liquid crystal drive output 61 among the n liquid crystal drive outputs is performed, the VON69 output test is performed by outputting a VON69 level to the liquid crystal drive output 61, and otherwise (n-1).
The liquid crystal drive output terminals output the VOFF70 level, and the VOFF70 output test is similarly performed by outputting the VOFF70 level to the liquid crystal drive output 61, and the other (n-1) liquid crystal drive output terminals are VON69. Outputs the level. At the time of the VON 69 level output test, the control signal 60 is set to the “L” level, the test signal 62 is set to the “H” level, and the test signal 63 is set to the “H” level. At this time, the Pch transistor 54 controlled by the control signal 60 is on, the Nch transistor 55 is off, the test signal 62,
Since the Pch transistor 51 and the Nch transistor 52 controlled by 63 are turned off and on, respectively, VON
69 level is selected and the current from VON69 is Pch
Through the transistor 54 and the Nch transistor 52,
The current flows to the test ammeter 65 and the external power supply 66. By monitoring the test ammeter 65 at this time, Pc
The h transistor 54 is tested. Similarly, VOFF
At the time of the 70-level output test, the control signal 60 is at the “H” level, the test signal 62 is at the “L” level,
To the “L” level. At this time, the Pch transistor 54 controlled by the control signal 60 is off, the Nch transistor 55 is on, and Pc controlled by the test signals 62 and 63.
Since the h transistor 51 and the Nch transistor 52 are turned on and off, respectively, the VOFF 70 level is selected, and the current to the VOFF 70 is supplied from the external power supply 66 to the VOFF 70 via the test ammeter 64, the Pch transistor 51, and the Nch transistor 55. Flows to By monitoring the test ammeter 64 at this time, Nch
A test of the transistor 55 is performed.

By sequentially switching the liquid crystal drive output terminals to be measured by the control signal 60, all the liquid crystal drive output terminals can be tested.

In this embodiment, the liquid crystal driving power supply is VON6
9, two levels of VOFF70, but not limited to this,
Similar results can be obtained by using a multi-level liquid crystal drive power supply.

As described above, the present embodiment realizes a semiconductor device and a test circuit that can perform a test without probing the output terminal by using the off transistor of the electrostatic discharge protection circuit as a test circuit.

[0026]

According to the semiconductor device of the present invention,
The following effects can be obtained.

By not performing the probe to the output terminal, the failure due to the contact property of the probe needle is eliminated, the yield is improved, and the cost is reduced.

Further, since the off-transistor of the electrostatic discharge protection circuit is used as a test circuit, there is no need to provide a dedicated test terminal and a dedicated test circuit, so that there is an advantage that the chip size can be reduced.

By using the semiconductor device of the present invention,
The test can be performed without increasing the size of the semiconductor chip and without probing the output terminal, and a semiconductor device that is inexpensive and has high performance as compared with a conventional semiconductor device can be realized.

[Brief description of the drawings]

FIG. 1 is a diagram showing a first embodiment of a semiconductor device of the present invention.

FIG. 2 is a diagram showing a second embodiment of the semiconductor device of the present invention.

FIG. 3 is a diagram illustrating an example of a decoder circuit of the semiconductor device of the present invention.

FIG. 4 is a diagram showing a third embodiment of the semiconductor device of the present invention.

[Explanation of symbols]

 1, 4, 34, 51, 54 Pch transistor 2, 5, 35, 52, 55 Nch transistor 3, 53 Electrostatic discharge protection circuit 11, 61 Output terminal 12, 13, 31, 62, 63 Test signal 6, 56 Output stage transistor section 16, 66 IC power supply 14, 15, 64, 65 Ammeter 32 Decoder 10, 60 Control signal 36 Inverter 37, 38 Clocked inverter 17 VCC 18, 68 VGND 67 VHIGH 69 VON 70 VOFF

Claims (3)

[Claims] 1. A semiconductor device having an electrostatic discharge prevention circuit using an output off transistor in a semiconductor device, and a test circuit including means for using the off transistor of the electrostatic discharge prevention circuit. 2. The semiconductor device according to claim 1, further comprising a decoder for controlling an off transistor of the electrostatic discharge protection circuit. 3. The liquid crystal driving device according to claim 1, further comprising means for driving a liquid crystal display device.