JP2014130518A - Semiconductor device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To change operating conditions of a power supply IC, monitor voltage at the time of having a microcomputer operated, and in addition, enhance the reliability in failure diagnosis and abnormality detection.SOLUTION: A semiconductor device according to one embodiment comprises: a power supply IC 10 having a regulator circuit 11 that generates a power supply voltage; a microcomputer 20 having a core 21 that operates by receiving an operation voltage corresponding to the power supply voltage; and a microcomputer-side voltage monitoring circuit 22 that changes the operating conditions of the regulator circuit 11 and core 21 according to a diagnosis setting signal and monitors the power supply voltage or operation voltage.

Description

  The present invention relates to a semiconductor device, for example, a semiconductor device having a voltage monitoring function.

  Patent Document 1 describes a technique in which a voltage monitoring circuit for detecting an abnormality in an output voltage from the power supply IC is provided in the power supply IC. Patent Document 2 describes a technique in which a voltage monitoring circuit for detecting an abnormality of a voltage input to the microcomputer is provided in the microcomputer. As the voltage monitoring circuit, for example, a circuit having a reference voltage circuit, a comparator, an A / D converter and the like described in Patent Document 3 is used.

  In a semiconductor device including a power supply IC and a microcomputer that operates by receiving a voltage from the power supply IC, a voltage detection circuit may be provided on each of the power supply IC side and the microcomputer side. These voltage detection circuits individually monitor and diagnose the voltages of the power supply IC and the microcomputer.

JP 2001-160004 A JP 2008-171092 A JP 2006-209486 A

  The current load applied to the power supply IC varies according to the operation of the microcomputer. In addition, the output voltage from the power supply IC decreases due to a decrease in the drive capability of the output transistor provided in the power supply IC. That is, in a semiconductor device including a power supply IC and a microcomputer, the voltages on the power supply IC side and the microcomputer side are both affected by the operating conditions of both the power supply IC and the microcomputer. For this reason, it is desired to change the operating conditions of the power supply IC, monitor the voltage when the microcomputer is operated, and further improve the reliability of failure diagnosis and abnormality detection.

  Other problems and novel features will become apparent from the description of the specification and the accompanying drawings.

  According to one embodiment, the semiconductor device changes the operating conditions of the power supply device and the processing device according to the input diagnostic setting signal, and is used for the power supply voltage generated in the power supply device or the operation of the processing device. Monitor the operating voltage.

  Thereby, the voltage when the operating conditions of both the power supply device and the processing device are changed can be monitored, and the reliability can be further improved.

1 is a diagram showing a configuration of a semiconductor device according to a first embodiment. FIG. 6 is a diagram showing another configuration of the semiconductor device according to the first embodiment. FIG. 4 is a diagram showing a configuration of a semiconductor device according to a second embodiment. It is a figure which shows the preferable aspect of the node A in the semiconductor device shown in FIG. FIG. 6 is a diagram showing a configuration of a semiconductor device according to a third embodiment. FIG. 6 is a diagram showing a preferred mode of node A in the semiconductor device shown in FIG. 5. FIG. 6 is a diagram showing a configuration of a semiconductor device according to a fourth embodiment.

  The present embodiment relates to a semiconductor device including a power supply device and a processing device that operates by receiving a power supply voltage generated by the power supply device. The semiconductor device according to the embodiment changes the operating conditions of the power supply device and the processing device according to the diagnosis setting signal, and monitors and diagnoses the output voltage generated in the power supply device or the operating voltage used for the operation of the processing device. To do.

  As a result, it is possible to monitor the voltage when the operating conditions of both the power supply device and the processing device are changed in conjunction with each other and further improve the reliability of failure diagnosis and abnormality detection. Hereinafter, embodiments will be described in detail with reference to the drawings. In the following drawings, the same components are denoted by the same reference numerals, and description thereof will be omitted as appropriate.

Embodiment 1 FIG.
A semiconductor device according to the first embodiment will be described with reference to FIG. FIG. 1 is a diagram illustrating a configuration of the semiconductor device according to the first embodiment. As shown in FIG. 1, the semiconductor device 100 includes two IC chips, a power supply IC 10 that is a power supply device and a microcomputer 20 that is a processing device. The power supply IC 10 is provided with a regulator circuit 11 and terminals T11 and T12. The regulator circuit 11 is a voltage generation circuit that generates a power supply voltage Vo based on an external voltage supplied from the outside. As the regulator circuit 11, for example, an LDO (Low Drop Out) regulator, a DC-DC converter, or the like can be used.

  An example of the regulator circuit 11 includes a reference voltage generation circuit, an error amplifier, an output transistor, an output voltage setting resistor, and the like. An external voltage is supplied to the source of the output transistor, and the power supply voltage Vo is output from the drain. The gate of the output transistor is connected to the output of the error amplifier. The reference voltage from the reference voltage generation circuit is input to the inverting input terminal of the error amplifier, and the power supply voltage Vo is fed back to the non-inverting input terminal via the output voltage setting resistor. The error amplifier compares two input signals. Based on the comparison result, the output transistor is controlled. The power supply voltage Vo is output from the terminal T11 via a parasitic impedance R1 such as wiring or a package inside the power supply IC10.

  The microcomputer 20 is provided with a core 21, which is an arithmetic circuit, a microcomputer side voltage monitoring circuit 22, and terminals T21 and T22. The voltage output from the terminal T11 is input to the terminal T21 via the board wiring impedance R2 between the power supply IC 10 and the microcomputer 20. In addition, the microcomputer 20 includes a built-in RAM (Random Access Memory), a memory controller, and the like (not shown). The built-in RAM stores a control program transferred from an external ROM (Read Only Memory) by the memory controller. The core 21 receives the operating voltage and executes processing in the microcomputer 20 according to a control program stored in the built-in RAM.

  The voltage input from the terminal T21 is supplied as an operating voltage to the core 21 via a parasitic impedance R3 such as a wiring or package inside the microcomputer 20. In the first embodiment, the core 21 is an operation circuit that operates by receiving an operation voltage. The core 21 receives the operating voltage and executes the control program. A node to which the operating voltage is supplied is referred to as node A. The microcomputer side voltage monitoring circuit 22 is connected to the node A. In the first embodiment, the microcomputer side voltage monitoring circuit 22 monitors the operating voltage.

  In the first embodiment, the diagnosis setting signal is generated by the core 21. The diagnosis setting signal is input to the memory in the core 21. Further, the diagnosis setting signal is input to the terminal T12 of the power supply IC 10 via the terminal T22 of the microcomputer 20. The diagnostic setting signal input to the terminal T12 is input to the regulator circuit 11 in the power supply IC 10.

  The diagnosis setting signal changes the operating condition in the core 21 and changes the operating condition of the regulator circuit 11. That is, the diagnosis setting signal causes the regulator circuit 11 and the core 21 to simultaneously enter the diagnosis mode.

  The operating conditions in the diagnostic mode of the core 21 can be set so that, for example, the operating speed, the operating rate, etc. are maximized, and the current Idd flowing through the node A is maximized. That is, in the diagnosis mode, the power supply IC 10 is subjected to the maximum current load by the operation of the core 21. That is, the core 21 is an arithmetic circuit that operates according to the diagnosis setting signal and generates a load current.

  As an operation condition in the diagnostic mode of the regulator circuit 11, for example, an external voltage and temperature related to the output current capability can be taken into consideration, and the condition can be intentionally set to be a severe condition in the circuit. For example, the driver capability can be reduced, the circuit current can be reduced to deteriorate the transient response, the output voltage standard can be set to the minimum value, or the judgment criteria of the output voltage judgment circuit can be tightened.

  As described above, in the first embodiment, the most severe combination of conditions for both the power supply IC 10 and the microcomputer 20 is created at the same time. The microcomputer side voltage monitoring circuit 22 monitors and diagnoses the operating voltage of the node A in the diagnosis mode. Thereby, it is possible to further improve the reliability of failure diagnosis and abnormality detection. Note that the operating conditions in the diagnostic mode of the regulator circuit 11 and the core 21 are not limited to one. For example, a plurality of diagnoses can be performed by a combination of the various operating conditions described above.

  The terminals T12 and T22 may be specific terminals that output a diagnosis setting signal. The diagnosis setting signal and an I / F signal to other circuits such as a test register, a timer, and a sequencer in the power supply IC 10 are output. Alternatively, a dual-purpose terminal that switches and outputs based on the diagnosis setting signal may be used.

  FIG. 2 is a diagram illustrating another configuration of the semiconductor device according to the first embodiment. In the semiconductor device 100 ′ illustrated in FIG. 2, a power supply side voltage monitoring circuit 12 is further provided in the power supply IC 10. The diagnosis setting signal is directly input to the core 21 and the regulator circuit 11 from the outside.

  In the semiconductor device 100 ′ shown in FIG. 2, the microcomputer side voltage monitoring circuit 22 monitors the operating voltage of the node A in the diagnosis mode, and the power supply side voltage monitoring circuit 12 monitors the power supply voltage Vo. In other words, the diagnosis of the power supply IC 10 and the microcomputer 20 can be performed simultaneously in the combination of the most severe conditions for both the power supply IC 10 and the microcomputer 20.

Embodiment 2. FIG.
A semiconductor device 100A according to the second embodiment will be described with reference to FIG. FIG. 3 is a diagram illustrating a configuration of the semiconductor device 100A. As shown in FIG. 3, the semiconductor device 100A includes two IC chips, a power supply IC 10A and a microcomputer 20A. The power supply IC 10 </ b> A includes a regulator circuit 11, a power supply side voltage monitoring circuit 12, a watchdog timer 13, and a selector 14. The microcomputer 20 </ b> A has a core 21, an IO buffer circuit 23, and a selector 24.

  In the second embodiment, the operating voltage of the IO buffer circuit 23 which is an output circuit is fed back to the power supply IC 10A side, and diagnosis is performed by the power supply side voltage monitoring circuit 12. The power supply side voltage monitoring circuit 12 performs switching between diagnosis of the power supply voltage Vo and diagnosis of the operating voltage of the node A.

  As in the first embodiment, the power supply voltage Vo output from the regulator circuit 11 reaches the node A via the impedances R1, R2, and R3. The voltage at the node A is supplied as an operating voltage for the IO buffer circuit 23. That is, in the second embodiment, the IO buffer circuit 23 is an operation circuit that operates in response to an operation voltage.

  A diagnostic setting signal from the outside is input to the core 21 of the microcomputer 20A, the IO buffer circuit 23, and the selector 24 via the terminal T22. The operating conditions of the core 21 are set so that, for example, the current Idd flowing through the node A becomes a maximum value in accordance with the diagnosis setting signal. That is, the core 21 generates a load current according to the diagnosis setting signal. The selector 24 outputs the operation result from the core 21 to the IO buffer circuit 23 in the normal operation mode, and fixes and outputs the high level Hi signal in the diagnosis mode.

  The IO buffer circuit 23 has a plurality of output buffers that output the operation results output from the core 21. One of the plurality of output buffers of the IO buffer circuit 23 is configured to output the Hi signal from the selector 24 in the diagnosis mode. In the example shown in FIG. 3, the output buffer BUF <b> 1 is connected to the output of the selector 24. The output buffer BUF1 outputs a Hi signal using the operating voltage in the diagnostic mode.

  That is, the output buffer BUF1 outputs a Hi signal as a voltage monitor signal when the core 21 operates and a load current is generated according to the diagnosis setting signal. The output buffers other than the output buffer BUF1 output a rectangular wave signal in which the Hi signal and the low level Low signal are alternately repeated.

  The voltage monitor signal is output from the terminal T23 and input from the terminal T13 to the power supply IC 10A. In the second embodiment, the terminals T13 and T23 are shared with the I / F signal input to the watchdog timer 13 and the voltage monitor signal. In the normal operation mode, an I / F signal is output from the terminal T23 and input to the watchdog timer 13 via the terminal T13. On the other hand, in the diagnosis mode, a voltage monitor signal is output from the terminal T23 and input to the selector 14. Thus, by using the terminal also, it becomes unnecessary to add a new dedicated pin to the power supply IC 10A and the microcomputer 20A.

  The diagnosis setting signal is input to one input terminal of the selector 14 of the power supply IC 10A via the terminal T12. Further, the power supply voltage Vo from the regulator circuit 11 is input to the other input terminal of the selector 14. The selector 14 is a selection circuit that switches between a first monitoring mode for diagnosing the power supply voltage Vo and a second monitoring mode for diagnosing the voltage monitor signal in accordance with the diagnosis setting signal. In the normal operation mode, the selector 14 outputs the power supply voltage Vo to the power supply side voltage monitoring circuit 12. In the diagnosis mode, the selector 14 outputs a voltage monitor signal to the power supply side voltage monitoring circuit 12.

  In the above embodiment, the power supply voltage Vo and the voltage monitor signal are switched and monitored alternately. However, the present invention is not limited to this. For example, it is possible to provide two comparators on the power supply IC 10A side and monitor the difference voltage constantly with one comparator.

  Therefore, the power supply side voltage monitoring circuit 12 monitors the power supply voltage Vo in the normal operation mode and monitors the voltage monitor signal in the diagnosis mode. In other words, the power supply side voltage monitoring circuit 12 monitors the power supply voltage and the voltage monitor signal by switching according to the diagnosis setting signal. Thus, by having a configuration in which the operating voltage in the microcomputer 20A is fed back to the power supply IC 10A side, the voltage monitoring of the power supply IC 10A and the microcomputer 20A can be performed by a single voltage monitoring circuit. Thereby, compared with the example in which the voltage monitoring circuit is provided on each of the power supply IC and the microcomputer side, the cost can be reduced and the chip area can be reduced.

  In addition, when a voltage monitoring circuit is provided for each of the power supply IC and the microcomputer and voltage monitoring is performed individually, in addition to the problem of cost increase caused by providing a plurality of voltage monitoring circuits, load current is not generated. In the case where only voltage monitoring is performed, abnormality in the substrate wiring impedance between the power supply IC and the microcomputer, or abnormality in the parasitic impedance such as the wiring in the power supply IC and the microcomputer cannot be detected.

  In the second embodiment, the operating voltage of the node A is a voltage that passes through the parasitic impedances R1 and R3 and the substrate wiring impedance R2. In a state where the core 21 is operated and a load current is generated, the voltage VA of the node A is VA = Vo−Id × (R1 + R2 + R3). The power supply side voltage monitoring circuit 12 can monitor the voltage monitor signal output from the output buffer BUF1 that operates using the operating voltage of the node A.

  Thereby, it is possible to realize diagnosis including abnormality of parasitic impedances R1 and R3 in each IC and substrate wiring impedance R2 between the ICs. After completion of the diagnosis, the diagnosis mode is canceled and the core 21 and the IO buffer circuit 23 are set to normal operation. At this time, the power supply side voltage monitoring circuit 12 monitors the power supply voltage Vo output from the regulator circuit 11.

  In the second embodiment, the example in which the terminal that outputs the control signal to the watchdog timer 13 is used as the output terminal of the voltage monitor signal is shown, but the present invention is not limited to this. For example, any terminal that outputs an I / F signal between the power supply IC 10A and the microcomputer 20A, such as a power control signal, can also be used as an output terminal for the voltage monitor signal. The terminal T13 may be a terminal that can receive both an analog signal and a digital signal.

  The diagnosis setting signal can also be applied by register control using a serial I / F such as SPI or I2C. Further, the input source of the diagnosis setting signal is not limited from the outside, but from the microcomputer side or the power supply IC side.

  Here, with reference to FIG. 4, the preferable aspect of the node A is demonstrated. FIG. 4 shows the configuration of the IO buffer circuit 23 of FIG. As shown in FIG. 4, the IO buffer circuit 23 is provided with a plurality of output buffers BUF1, BUF2,... BUFn, an IO power supply point 26, and a power line 27. An operating voltage is supplied to the IO buffer circuit 23 from an IO power supply point 26. The plurality of output buffers BUF1, BUF2,... BUFn are connected by the same power line 27.

  The operating voltage supplied from the IO power supply point 26 is supplied to the plurality of output buffers BUF1, BUF2,... BUFn via the power supply line 27, respectively. The node A is a place where the voltage drop is greatest from the IO power supply point 26. In the example shown in FIG. 4, the operating voltage input to the output buffer having the highest impedance of the power supply line 27 to the output buffer BUF is supplied from among the plurality of output buffers BUF1, BUF2,. Can be node A. That is, the output buffer in which the physical length of the power supply line 27 from the IO power supply point 26 to the output buffer is the longest can be obtained.

  The node A may be a location where the voltage specification of the output buffer is critical. For example, in the same power supply line 27 to which a plurality of output buffers are connected, a node A may be a portion where the driving voltage is large and the operation voltage input to the output buffer that outputs AC is supplied. Further, a node A can be a place where a plurality of output buffers BUF1, BUF2,... BUFn are connected. As a result, it becomes possible to monitor a voltage monitor signal under more severe conditions, and it is possible to improve the reliability of abnormality detection.

Embodiment 3 FIG.
A semiconductor device according to the third embodiment will be described with reference to FIG. FIG. 5 is a diagram showing a configuration of the semiconductor device 100B according to the third embodiment. As shown in FIG. 5, the semiconductor device 100B includes two IC chips, a power supply IC 10B and a microcomputer 20B. The power supply IC 10B includes a regulator circuit 11, a power supply side voltage monitoring circuit 12, and a selector 14. The microcomputer 20A includes a core 21, a selector 24, and an internal circuit 25.

  In the third embodiment, the operating voltage of the core 21 (the voltage at the node A) is fed back to the power supply IC 10A side as a voltage monitor signal, and diagnosis is performed by the power supply side voltage monitoring circuit 12. The power supply side voltage monitoring circuit 12 performs switching between diagnosis of the power supply voltage Vo and diagnosis of the operating voltage of the node A.

  As in the first embodiment, the power supply voltage Vo output from the regulator circuit 11 reaches the node A via the impedances R1, R2, and R3. The voltage at the node A is supplied as the operating voltage for the core 21. That is, in the third embodiment, the core 21 is an operation circuit that operates by receiving an operation voltage. This operating voltage is input to one input terminal of the selector 24.

  The internal circuit 25 is a circuit that outputs an analog signal such as a DA converter or OPAMP. The analog signal output from the internal circuit 25 is input to the other input terminal of the selector 24. The terminal T23 is a terminal that outputs an analog signal from the internal circuit 25. In the third embodiment, the terminal T23 is shared by the analog signal from the internal circuit 25 and the voltage monitor signal. In this way, it is not necessary to add a new dedicated pin by using the terminal also.

  A diagnostic setting signal from the outside is input to the core 21 and the selector 24 of the microcomputer 20A via the terminal T22. For example, the operating condition is set so that the current Idd flowing through the node A becomes the maximum value, and the core 21 generates a load current according to the diagnosis setting signal. The selector 24 outputs an analog signal from the internal circuit 25 in the normal operation mode, and outputs a voltage monitor signal in the diagnosis mode. An analog signal from the internal circuit 25 is output to the outside.

  The terminal T13 of the power supply IC 10B receives a voltage monitor signal in the diagnostic mode, but is controlled to have a high impedance in the normal operation mode so as not to affect the output of the internal circuit 25. As in the second embodiment, the diagnosis setting signal can be applied by register control using a serial I / F such as SPI or I2C. Further, the input source of the diagnosis setting signal is not limited from the outside, but from the microcomputer side or the power supply IC side.

  The diagnosis setting signal is input to one input terminal of the selector 14 via the terminal T12. Further, the power supply voltage Vo from the regulator circuit 11 is input to the selector 14. Similar to the second embodiment, the selector 14 outputs the power supply voltage Vo in the normal operation mode, and outputs a voltage monitor signal in the diagnosis mode. The power supply side voltage monitoring circuit 12 can switch and monitor the power supply voltage Vo and the voltage monitor signal according to the diagnosis setting signal.

  As described above, in the third embodiment, it is possible to eliminate the need for a comparator circuit, a reference voltage generation circuit, an AD converter, and the like constituting the voltage monitoring circuit without providing a voltage monitoring circuit on the microcomputer 20B side. Thereby, the cost can be reduced and the chip area can be reduced. Further, by operating the core 21 according to the diagnosis setting signal and diagnosing the voltage monitor signal in a state where the load current is generated, the parasitic impedances R1 and R3 in each IC and the substrate wiring impedance R2 between the ICs are abnormal. Diagnosis including can be realized.

  Here, with reference to FIG. 6, the preferable aspect of the node A is demonstrated. FIG. 6 is a diagram illustrating another configuration example of a part of the semiconductor device illustrated in FIG. 5. In the example shown in FIG. 6, a plurality of cores 21A and 21B are provided. An operating voltage is supplied to each of the cores 21A and 21B from the core power supply point 28 via the power line 27.

  The node A is a place where the voltage drop is greatest from the core power supply point 28. In the example shown in FIG. 6, the node A can be a portion to which the operating voltage of the core 21 </ b> B having the highest impedance of the power supply line 27 to the core among the plurality of cores 21 </ b> A and 21 </ b> B is supplied. That is, the core 21 </ b> B can have the longest physical length of the power supply line 27 from the core power supply point 28 to the core.

  The node A may be a location where the core voltage specification is critical. For example, among the plurality of cores, a node A may be a portion to which an operation voltage input to a core whose gate scale, operation speed, or operation rate is higher than other cores is supplied. As a result, it becomes possible to monitor a voltage monitor signal under more severe conditions, and it is possible to improve the reliability of abnormality detection. Note that this node A selection method can also be combined with the first embodiment.

Embodiment 4 FIG.
A semiconductor device according to the fourth embodiment will be described with reference to FIG. FIG. 7 is a diagram showing a configuration of the semiconductor device according to the fourth embodiment. The fourth embodiment is an example of diagnosing operating voltages of a plurality of microcomputers 20a, 20b,..., 20n with one power supply IC 10a. Since the configurations of the power supply IC 10a, the microcomputers 20a, 20b,..., 20n are the same as those of the power supply IC 10A and the microcomputer 20A described in the second embodiment, detailed description thereof is omitted.

  The power supply IC 10a is provided with a plurality of terminals T13, T14,... For receiving operation monitor signals from the microcomputers according to the number of the microcomputers 20a, 20b,. . Diagnosis can be performed sequentially with the microcomputers 20a, 20a, 20b,.

  With such a configuration, the voltage monitoring circuit can be completely deleted from all the microcomputers 20a, 20b,. Further, diagnosis including the impedance in each microcomputer is possible by performing diagnosis in a state where load current is generated by operating each of the cores 21a, 21b,..., 21n. The microcomputers 20a, 20b,..., 20n are not limited to the example shown in the second embodiment, and the microcomputer 20B shown in the third embodiment can also be used.

  As mentioned above, the invention made by the present inventor has been specifically described based on the embodiments. However, the present invention is not limited to the embodiments already described, and various modifications can be made without departing from the scope of the invention. It goes without saying that it is possible.

10 Power IC
10A, 10B power IC
10a Power IC
DESCRIPTION OF SYMBOLS 11 Regulator circuit 12 Power supply side voltage monitoring circuit 13 Watchdog timer 14 Selector 20 Microcomputer 20A, 20B Microcomputer 20a, 20b, ..., 20n Microcomputer 21a, 21b, ..., 21n Core 21 Core 21A, 21B Core 22 Microcomputer side Voltage monitoring circuit 23 IO buffer circuit 24 Selector 25 Internal circuit 26 IO power supply point 27 Power supply line 28 Core power supply point 100 Semiconductor device 100 ′, 100A, 100B Semiconductor device Vo Power supply voltage A node T11, T12, T13, T14, T15 , T21, T22, T23 Terminal R1 Parasitic impedance R2 Board wiring impedance R3 Parasitic impedance BUF Output buffer

Claims (15)

A power supply device having a voltage generation circuit for generating a power supply voltage;
A processing apparatus having an operating circuit that operates in response to an operating voltage corresponding to the power supply voltage;
A voltage monitoring circuit that changes operating conditions of the voltage generation circuit and the operating circuit according to a diagnostic setting signal, and monitors the power supply voltage or the operating voltage;
A semiconductor device.   The semiconductor device according to claim 1, wherein the voltage monitoring circuit is provided in the power supply device and monitors the power supply voltage. An arithmetic circuit that is provided in the processing device and operates according to the diagnostic setting signal to generate a load current;
The operation circuit is an output circuit provided in the processing device,
The output circuit outputs the operating voltage when the load current is generated as a voltage monitor signal to the voltage monitoring circuit according to the diagnosis setting signal,
The semiconductor device according to claim 2, wherein the voltage monitoring circuit monitors the power supply voltage and the voltage monitor signal.   A selection circuit provided in the power supply device, wherein the voltage monitoring circuit switches between a first monitoring mode for monitoring the power supply voltage and a second monitoring mode for monitoring the voltage monitor signal according to the diagnosis setting signal; The semiconductor device according to claim 3 further provided. A first circuit provided in the power supply device;
A first terminal for outputting a first signal from the processing device to the first circuit;
The semiconductor device according to claim 3, wherein the voltage monitor signal is output to the voltage monitoring circuit using the first terminal according to the diagnosis setting signal. The operating voltage is supplied to the output circuit from a power supply point,
The semiconductor device according to claim 3, wherein the voltage monitor signal is output from a location where the voltage drop is the largest from the power supply point. The output circuit has a plurality of output buffers for outputting the calculation results from the calculation circuit,
The operating voltage is supplied to each of the plurality of output buffers via a power line,
The semiconductor device according to claim 6, wherein the voltage monitor signal is output from an output buffer having the largest impedance of the power supply line among the plurality of output buffers. The output circuit has a plurality of output buffers for outputting the calculation results from the calculation circuit,
4. The semiconductor device according to claim 3, wherein the voltage monitor signal is the operating voltage at a location where voltage specifications of the plurality of output buffers are critical. The output circuit has a plurality of output buffers for outputting the calculation results from the calculation circuit,
The operating voltage is supplied to the plurality of output buffers through the same power line,
The semiconductor device according to claim 8, wherein the voltage monitor signal is output from an output buffer having the largest driving capability among the plurality of output buffers. The operation circuit is an arithmetic circuit provided in the processing device,
The arithmetic circuit operates according to the diagnostic setting signal and outputs the operating voltage when the load current is generated to the voltage monitoring circuit as a voltage monitor signal,
The semiconductor device according to claim 2, wherein the voltage monitoring circuit monitors the power supply voltage and the voltage monitor signal. The operating voltage is supplied to the arithmetic circuit from a power supply point,
The semiconductor device according to claim 10, wherein the voltage monitor signal is output from a portion where the voltage drop is greatest from the power supply point. The processing device includes a plurality of arithmetic circuits,
The operating voltage is supplied to each of the plurality of arithmetic circuits via a power line,
The semiconductor device according to claim 11, wherein the voltage monitor signal is output from among the plurality of arithmetic circuits. The processing device includes a plurality of arithmetic circuits,
11. The voltage monitor signal according to claim 10, wherein the voltage monitor signal corresponds to an operating voltage input to an arithmetic circuit in which any of a gate scale, an operation speed, and an operation rate is larger than other arithmetic circuits among the plurality of arithmetic circuits. Semiconductor device.   The semiconductor device according to claim 1, wherein the voltage monitoring circuit is provided in the processing apparatus and monitors an operating voltage input to the operating circuit. The processing device includes a plurality of arithmetic circuits,
The semiconductor device according to claim 14, wherein the voltage monitoring circuit monitors a voltage of a power supply line having the highest impedance among power supply lines that respectively supply the operation voltages to the plurality of arithmetic circuits.

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