JP2013024777A - Test board for semiconductor integrated circuit - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a test board for a semiconductor integrated circuit, which reduces various power source noises that are generated during testing of the semiconductor integrated circuit.SOLUTION: A test board for a semiconductor integrated circuit comprises a power supply current control circuit which changes a value of current supplied to a device under test in synchronization with a clock supplied to the device under test. The power supply current control circuit changes the value of current supplied to the device under test in synchronization with the clock supplied to the device under test.

Description

  The present invention relates to a test board for a semiconductor integrated circuit.

  In recent years, with the progress of miniaturization of semiconductor integrated circuits, the circuit scale of semiconductor integrated circuits has continued to increase. Here, as a test method for a semiconductor integrated circuit, there are a scan test in which scan data is input from the outside and an output result is compared with an expected value, and a BIST (Built-in Self Test) using a self-test circuit.

  In the manufacturing process of a semiconductor integrated circuit, it is required to efficiently test a device to be inspected (a semiconductor integrated circuit to be inspected) using these test methods. Therefore, in the scan test and BIST, many logic circuits in the device to be inspected are often operated simultaneously. This is because if a large number of logic circuits can be operated simultaneously and the operations can be tested in parallel, the test efficiency can be improved.

  However, in the scan test and BIST, the logic circuit is operated in synchronization with the input clock. Therefore, when a large number of logic circuits operate simultaneously, the test of the device under test may not be executed correctly.

  When a large number of logic circuits operate simultaneously, the power supply current changes instantaneously and the voltage level of the power supply voltage VDD of the device under test varies (so-called ground bounce occurs). If the fluctuation range of the power supply voltage VDD is large, it may affect the logic level of the logic circuit included in the device under test, and the operation of the logic circuit may be unexpected. Therefore, such fluctuations in the power supply voltage VDD can be regarded as power supply noise generated in the power supplied to the device under test. In addition, the operation of the logic circuit may be unexpected because the voltage supplied to the logic circuit instantaneously decreases and the operation speed of the logic circuit decreases.

  Here, Patent Document 1 discloses a technique for reducing power supply noise by inserting a capacitor between a power supply unit that supplies a power supply voltage to a device under test and the device under test.

JP-T-2005-516226

  The disclosure of the above prior art document is incorporated herein by reference. The following analysis has been made from the viewpoint of the present invention.

  FIG. 2 is a diagram illustrating an example of the configuration of the test system disclosed in Patent Document 1. As illustrated in FIG. The test system shown in FIG. 2 includes a test board 1 and a tester 2.

  The test board 1 includes an inspected device 10. The tester 2 includes a power supply unit 20 and a clock driver unit 30. The power necessary for the operation of the device under test 10 is supplied from the power supply unit 20, and the clock is supplied from the clock driver unit 30. Furthermore, one end of the capacitor C01 is connected between the device under test 10 and the power supply unit 20, and the other end is connected to the ground voltage VSS.

  In the test system shown in FIG. 2, when power supply noise is generated in the power supply supplied from the power supply unit 20, the power supply noise is smoothed by the capacitor C01 to reduce the noise level. As a result, the influence of power supply noise on the device under test 10 is reduced.

  However, when taking measures against power supply noise by the capacitor C01, it is necessary to place the capacitor C01 as close as possible to the device under test 10. Further, there is a problem that the capacitor C01 alone cannot cope with the power supply noise generated when the device under test is tested. This is because there are various power noise levels and rise times generated during the test, and such power noise includes power noise that cannot be dealt with only by the characteristic (capacitance value) of the capacitor C01.

  As described above, there are problems to be solved for countermeasures against power supply noise generated on a test board of a semiconductor integrated circuit. Therefore, a test board for a semiconductor integrated circuit that reduces various power supply noises generated during testing is desired.

  According to a first aspect of the present invention, there is provided a test board for a semiconductor integrated circuit including a power supply current control circuit that changes a current value supplied to a device under test in synchronization with a clock supplied to the device under test. Is done.

  According to the present invention, there is provided a test board for a semiconductor integrated circuit that reduces various power supply noises generated during a test.

It is a figure for demonstrating the outline | summary of one Embodiment of this invention. It is a figure which shows an example of a structure of the test system of a semiconductor integrated circuit. It is a figure which shows an example of a structure of the test system containing the test board 3 which concerns on the 1st Embodiment of this invention. FIG. 4 is a diagram illustrating an example of an internal configuration of a power supply current control circuit 40 illustrated in FIG. 3. It is a figure which shows an example of the waveform at the time of operating the test system shown in FIG.

  First, an outline of an embodiment will be described with reference to FIG. Note that the reference numerals of the drawings attached to this summary are attached to the respective elements for convenience as an example for facilitating understanding, and are not intended to limit the present invention to the illustrated embodiment.

  As described above, there is a problem in the technique for reducing power supply noise generated on a test board of a semiconductor integrated circuit using a capacitor. This is because power supply noise generated at the time of testing varies widely, and power supply noise that cannot be dealt with only by changing the characteristics of the capacitor may also occur. Therefore, a test board for a semiconductor integrated circuit that reduces various power supply noises generated during testing is desired.

  Therefore, as an example, a test board for the semiconductor integrated circuit shown in FIG. 1 is provided. The semiconductor integrated circuit test board shown in FIG. 1 includes a power supply current control circuit that changes a current value supplied to a device under test in synchronization with a clock supplied to the device under test.

  This power supply current control circuit changes the current value supplied to the device under test in synchronization with the clock supplied to the device under test. At that time, the current supplied to the device under test is branched so that a constant current always flows through the power supply current control circuit. Further, the current flowing through the power supply current control circuit is cut off at the timing when a large current is required in the device under test (the timing when the device under test operates in synchronization with the clock).

  As a result, the current flowing in the power supply current control circuit is also supplied to the device under test, the fluctuation range of the power supply voltage VDD supplied to the device under test is reduced, and power supply noise can be reduced. .

  In the present invention, the following modes are possible.

  [Mode 1] A test board for a semiconductor integrated circuit comprising a power supply current control circuit for changing a current value supplied to a device under test in synchronization with a clock supplied to the device under test as in the first aspect.

  [Mode 2] A wiring for supplying a power supply voltage to the device under test branches at a first node, and a wiring for supplying a clock to the device under test branches at a second node, and the power supply current control circuit Is preferably connected to the first and second nodes.

  [Mode 3] Preferably, the first node is close to the device to be inspected as long as a test board layout of a semiconductor integrated circuit is possible.

  [Mode 4] The power supply current control circuit includes: a switch connected to the first node; and a delay element connected to the second node to delay a clock supplied to the second node. Preferably, the delay element controls a timing at which a current flowing through the power supply current control circuit changes by cutting off the switch for a certain period based on a change in the clock.

  [Mode 5] It is preferable that the power supply current control circuit further includes a resistor connected to the switch, and the current value of the current flowing through the power supply current control circuit is changed by changing the resistance.

  Hereinafter, specific embodiments will be described in more detail with reference to the drawings.

[First Embodiment]
The first embodiment of the present invention will be described in more detail with reference to the drawings.

  FIG. 3 is a diagram illustrating an example of a configuration of a test system including the test board 3 according to the present embodiment.

  The test system shown in FIG. 3 includes a tester 2 and a test board 3. The tester 2 has already been described with reference to FIG.

  The test board 3 includes a device under test 10 and a power supply current control circuit 40.

  The power supply current control circuit 40 is connected to a wiring connecting the power supply unit 20 and the device under test 10 (wiring for supplying the power supply voltage VDD to the device under test). A node that branches from the wiring connecting the power supply unit 20 and the device under test 10 to the power supply current control circuit 40 is referred to as a node S1. The node S1 is as close as possible to the device under test 10. This is because the shorter the wiring between the device under test 10 and the node S1, the more the influence of wiring resistance and the like can be eliminated.

  Further, the power supply current control circuit 40 is also connected to wiring (wiring for supplying a clock) that connects the clock driver unit 30 and the device under test 10. A node that branches from the wiring connecting the clock driver unit 30 and the device under test 10 to the power supply current control circuit 40 is referred to as a node S2.

  A current supplied from the power supply unit 20 to the test board 3 is a current Ia, and a current branched from the node S1 and flows to the power supply current control circuit 40 is a current Ib.

  Next, the power supply current control circuit 40 will be described.

  The power supply current control circuit 40 is a circuit for suppressing power supply noise generated in the power supplied to the device under test 10. The power supply current control circuit 40 controls the timing for increasing / decreasing the amount of current supplied to the device under test 10 and increasing / decreasing the current value.

  FIG. 4 is a diagram illustrating an example of the internal configuration of the power supply current control circuit 40.

  The power supply current control circuit 40 includes a NAND circuit NAND01, an N-channel MOS transistor N01, an inverter INV01, and a resistor R01.

  One end of the input of the NAND circuit NAND01 is connected to the node S2. The other end input of the NAND circuit NAND01 is connected to the node S2 via the inverter INV01. The output node of the NAND circuit NAND01 is connected to the gate terminal of the N-channel MOS transistor N01. The source terminal of the N-channel MOS transistor N01 is connected to the resistor R01, and the drain terminal is connected to the node S1. The other end of the resistor R01 is connected to the ground voltage VSS.

  The N-channel MOS transistor N01 functions as a switch, and a current Ib flows when the N-channel MOS transistor N01 is on. Note that the current value of the current Ib can be changed by changing the resistance value of the resistor R01.

  Next, the operation of the test system shown in FIG. 3 will be described.

  FIG. 5 is a diagram showing an example of a waveform when the test system shown in FIG. 3 is operated.

  FIG. 5 shows, sequentially from the top, the clock supplied by the clock driver unit 30, the change in voltage supplied from the power supply unit 20, the change in current Ia, the change in current Ib, and the change in voltage at the node S1.

  When the logic circuit included in the device under test 10 starts operating in synchronization with the clock supplied from the clock driver unit 30, the current required by the device under test 10 increases (time t1, t2, FIG. 5). t3). For this reason, the voltage and current Ia supplied from the power supply unit 20 vary greatly with the rising edge of the clock at time t1 or the like as a base point. The timing at which the voltage and current Ia supplied from the power supply unit 20 vary greatly coincides with the timing at which the clock is supplied to the device under test 10.

  Therefore, the N-channel MOS transistor N01 is switched from the on state to the off state with reference to the clock input from the node S2 to the power supply current control circuit 40. More specifically, during a period corresponding to the delay time in the inverter INV01 from the rising edge of the clock, the output of the NAND circuit NAND01 is at L level, and the N-channel MOS transistor N01 is turned off. As a result, the current Ib is temporarily interrupted, and the current Ib changes as shown in FIG.

  As the current Ib decreases, the current flowing into the device under test 10 increases. When the current flowing into the device under test 10 increases, the current supplied to the logic circuit included in the device under test 10 also increases, so that fluctuations in the power supply voltage VDD of the device under test 10 are alleviated. That is, the voltage fluctuation at the node S1 is reduced, and generation of power supply noise can be suppressed. As a result, the device under test 10 does not operate unexpectedly due to power supply noise. Therefore, even when a large number of logic circuits operate simultaneously in synchronization with the input clock in the scan test or BIST, the test of the device under test can be correctly executed.

  In this embodiment, the switch included in the power supply current control circuit 40 is realized using an N-channel MOS transistor, but the present invention is not limited to this. The switch included in the power supply current control circuit 40 only needs to be able to temporarily cut off the current Ib. Further, in the power supply current control circuit 40, the delay is realized by using the inverter INV01, but the delay can also be realized by other elements. Furthermore, although the case where the power supply unit 20 and the clock driver unit 30 are included in the tester 2 has been described, these may be included in the test board 3.

  As described above, the power supply current control circuit 40 is used to synchronize with the clock for operating the logic circuit included in the device under test 10 and at the timing when the current flowing into the power supply voltage VDD of the device under test 10 becomes maximum. The current Ib flowing through the power supply current control circuit 40 is controlled to be small. At this time, the current value of the current Ib can be changed by changing the resistance value of the resistor R01, and the timing for changing the current value Ib can be changed by changing the inverter INV01.

  Therefore, even if the power supply noise generated in the test system shown in FIG. 3 is various, various power supply noises can be reduced by appropriately selecting the resistor R01 and the inverter INV01.

  The disclosure of the cited patent document is incorporated herein by reference. Within the scope of the entire disclosure (including claims) of the present invention, the embodiment can be changed and adjusted based on the basic technical concept. Various combinations and selections of various disclosed elements are possible within the scope of the claims of the present invention. That is, the present invention of course includes various variations and modifications that could be made by those skilled in the art according to the entire disclosure including the claims and the technical idea.

1, 3 Test board 2 Tester 10 Device under test 20 Power supply unit 30 Clock driver unit 40 Power supply current control circuit C01 Capacitor INV01 Inverter N01 N-channel MOS transistor NAND01 Negative AND circuit R01 Resistance

Claims (5)

  A test board for a semiconductor integrated circuit, comprising: a power supply current control circuit that changes a current value supplied to a device under test in synchronization with a clock supplied to the device under test. A wiring for supplying a power supply voltage to the device under test branches at a first node, and a wiring for supplying a clock to the device under test branches at a second node;
2. The semiconductor integrated circuit test board according to claim 1, wherein the power supply current control circuit is connected to the first and second nodes.   3. The semiconductor integrated circuit test board according to claim 1, wherein the first node is close to the device under test within a range in which the layout of the test board of the semiconductor integrated circuit is possible. The power supply current control circuit is:
A switch connected to the first node;
A delay element connected to the second node and delaying a clock supplied to the second node;
4. The test board for a semiconductor integrated circuit according to claim 2, wherein the delay element controls a timing at which a current flowing in the power supply current control circuit changes by cutting off the switch for a certain period based on a change in the clock.   5. The test of a semiconductor integrated circuit according to claim 4, wherein the power supply current control circuit further includes a resistor connected to the switch, and the current value of the current flowing through the power supply current control circuit is changed by changing the resistance. board.

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