JP2007141882A - Semiconductor device, its testing device and method - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To prevent a voltage applied to other integrated circuit chip from falling even if a defective chip exists when a voltage is applied simultaneously to a plurality of integrated circuit chips formed on a wafer. <P>SOLUTION: Each of a plurality of integrated circuit chips 20 formed on a wafer 4 is provided with a circuit 3 to be tested characteristics of which are inspected by a voltage supplied from a voltage source 5 provided on the outside of a semiconductor device 10, and a circuit 1 for interrupting current supply to the circuit 3 to be tested when the current supplied from the voltage source 5 reaches a predetermined level. <P>COPYRIGHT: (C)2007,JPO&INPIT

Description

  The present invention relates to a wafer state semiconductor device having a plurality of integrated circuit chip regions, and a test apparatus and a test method for a wafer state semiconductor device having a plurality of integrated circuit chip regions.

  Inspection of a semiconductor device can be broadly divided into inspection in a wafer state and inspection in a product state. The inspection in the wafer state is, for example, a screening test (aging) for selecting a non-defective product / defective product of each integrated circuit chip, which is performed in a wafer state with respect to a plurality of integrated circuit chips formed on the wafer. Test, burn-in test).

  For example, in order to ensure the reliability of an integrated circuit chip in a wafer state, a voltage stress is applied to each integrated circuit chip, the defect symptom of the defective chip due to the wafer defect is revealed, and a non-defective / A test is conducted to select defective products.

  In this test, a probe card and a prober are used to screen each integrated circuit chip patterned on the wafer for defects. At this time, it is most efficient to apply a voltage stress by simultaneously bringing the probe card needles into contact with a voltage stress test pad for defect screening provided corresponding to each integrated circuit chip on the wafer. is there.

  However, with the current probe card technology, it is difficult to simultaneously bring the probe card needles into contact with all the chips on the wafer or the voltage stress test pads of a large number of chips. Therefore, in the conventional voltage stress test, it is necessary to perform the test by sequentially applying the voltage stress to each integrated circuit chip, and the voltage stress application time for all the chips on the wafer is added to the test time. There is a problem that the test time increases and the processing capacity decreases.

As a technique for reducing such a problem, for example, in Patent Document 1, voltage stress is applied to a plurality of circuits formed on a chip region using an input from a single voltage stress test terminal. Techniques for applying are disclosed.
JP-A-5-291368 (Publication date: November 5, 1993)

  However, in the above conventional technique, it is assumed that the voltage stress can be applied to all the integrated circuit pads even if it is assumed that the needles of the probe card can be simultaneously contacted to all the voltage stress test pads. Not exclusively. In the technique disclosed in Patent Document 1, voltage stress may not be applied to all integrated circuit pads.

  That is, when a defective chip exists in many chips to which voltage stress is applied, a large current may flow from the voltage stress test pad to the voltage supply source through the probe card needle. In such a case, the stress voltage applied to each integrated circuit chip is reduced by a large current flowing through the voltage supply source.

  In the technique disclosed in Patent Document 1, a control signal for controlling the operation of each integrated circuit chip is separately provided even though the number of voltage stress test terminals (voltage stress test pads) can be reduced. When it is necessary to supply, the number of terminals for supplying those control signals cannot be reduced.

  The present invention has been made in view of the above-described problems, and its purpose is that when a defective chip exists when a voltage is simultaneously applied to a plurality of integrated circuit chips formed on a wafer. Even if it exists, it is providing the semiconductor device which can prevent the voltage drop of the voltage applied to another integrated circuit chip, the test device of a semiconductor device, and a test method.

  Another object of the present invention is to supply a plurality of signals to a plurality of integrated circuit chips formed on the wafer to test the performance of each integrated circuit chip. It is an object of the present invention to provide a semiconductor device that can reduce the above.

  In order to solve the above problems, a semiconductor device according to the present invention is a semiconductor device in which a plurality of integrated circuit chips are formed on a semiconductor wafer, and the integrated circuit chip is a voltage supplied from an external voltage supply means. A circuit under test whose characteristics are to be inspected, and a current interrupt circuit for interrupting the current to the circuit under test when the current value of the current supplied from the voltage supply means exceeds a predetermined value; It is characterized by having.

  According to the above configuration, when the circuit under test provided in any of the plurality of integrated circuit chips is a defective product in which a large current flows when a voltage is applied, the current flowing through the circuit under test is separated by the current interrupt circuit. Can be blocked. Therefore, it is possible to prevent the current flowing from the voltage supply means provided outside the semiconductor device from flowing into the defective chip from exceeding the current supply capability of the voltage supply means, and to reduce the voltage applied to the circuit under test of another integrated circuit chip. Can be prevented.

  In addition, the current interrupt circuit includes a current detection unit that generates a potential according to a current value of a current supplied from the voltage supply unit, and a potential generated by the current detection unit becomes equal to or higher than a set value. It may be configured to include a cutoff means for cutting off the current to the circuit under test.

  For example, the current interruption means includes first to third three transistors and a resistance means, and the first transistor has a source connected to an input terminal for receiving a current supplied from the voltage supply means. The drain is connected to the source of the second transistor, and the gate is connected to the drain of the third transistor. The second transistor has a drain connected to the circuit under test, the gate of the second transistor itself, and the The third transistor is connected to the gate of the third transistor, and the third transistor has a source connected to an input terminal for receiving a current supplied from the voltage supply means, and a drain connected to the gate of the first transistor and the resistance means. And the other end of the resistance means is connected to a wiring having a constant potential. A configuration may be.

  According to the above configuration, by setting the set value appropriately, it is possible to detect that a current having a current value equal to or greater than a predetermined value flows in the circuit under test, and to block the current.

  The integrated circuit chip may include a signal generation circuit that generates a control signal for controlling the operation of the circuit under test based on a voltage supplied from the voltage supply means.

  For example, the signal generation circuit includes an oscillation circuit that oscillates a voltage supplied from the voltage supply unit to generate a clock signal, a clock signal generated by the oscillation circuit and / or a voltage supplied from the voltage supply unit. And a logic circuit that generates a control signal for controlling the operation of the circuit under test.

  According to the above configuration, since the signal generation circuit generates a control signal for controlling the operation of the circuit under test based on the voltage supplied from the voltage supply means, the circuit under test is connected to each integrated circuit chip. There is no need to input a control signal for controlling the operation. Therefore, it is not necessary to provide a terminal for inputting a control signal from the voltage supply means on the semiconductor wafer, so that the number of terminals formed on the semiconductor wafer can be reduced.

  Another semiconductor device of the present invention is a semiconductor device in which a plurality of integrated circuit chips are formed on a semiconductor wafer, and the integrated circuit chip is subjected to a characteristic inspection by a voltage supplied from an external voltage supply means. A circuit under test and a signal generation circuit for generating a control signal for controlling the operation of the circuit under test based on a voltage supplied from the voltage supply means are provided.

  For example, the signal generation circuit includes an oscillation circuit that oscillates a voltage supplied from the voltage supply unit to generate a clock signal, a clock signal generated by the oscillation circuit and / or a voltage supplied from the voltage supply unit. And a logic circuit that generates a control signal for controlling the operation of the circuit under test.

  According to the above configuration, since the signal generation circuit generates a control signal for controlling the operation of the circuit under test based on the voltage supplied from the voltage supply means, the circuit under test is connected to each integrated circuit chip. There is no need to input a control signal for controlling the operation. Accordingly, since it is not necessary to provide a terminal for inputting a control signal from the outside on the semiconductor wafer, the number of terminals formed on the semiconductor wafer can be reduced.

  In order to solve the above problems, the test apparatus of the present invention is a test apparatus for inspecting characteristics of each circuit under test by simultaneously applying voltages to a plurality of circuit under test formed on a semiconductor wafer. Voltage supply means for supplying a voltage to be applied to the circuit under test, an output terminal provided for each of the circuits under test, for outputting the voltage supplied from the voltage supply means to the circuit under test, and each of the outputs A current interrupt circuit provided between the terminal and the voltage supply means, and for interrupting the current to the output terminal when the current value of the current flowing through the output terminal exceeds a predetermined value; It is characterized by having.

  According to the above configuration, when the circuit under test provided in any of the plurality of integrated circuit chips is a defective product in which a large current flows when a voltage is applied, the current flowing through the circuit under test is separated by the current interrupt circuit. Can be blocked. Therefore, the current flowing from the voltage supply means to the defective chip can be prevented from exceeding the current supply capability of the voltage supply source, and the voltage drop of the voltage applied to the circuit under test of another integrated circuit chip can be prevented.

  In order to solve the above problems, the test method of the present invention is a test method for inspecting the characteristics of each circuit under test by simultaneously applying a voltage to a plurality of circuit under test formed on a semiconductor wafer. A voltage supply step for supplying a voltage to each circuit under test, a determination step for determining whether the current value of the current flowing through each circuit under test is equal to or greater than a predetermined value, and a current greater than a predetermined value in the determination step And a current interrupting step of interrupting the current to the circuit under test determined to be flowing.

  According to the above method, when the circuit under test provided in any of the plurality of integrated circuit chips is a defective product in which a large current flows when a voltage is applied, the current flowing through the circuit under test can be cut off. Accordingly, the current flowing from the voltage supply source provided outside the semiconductor device to the defective chip is prevented from exceeding the current supply capability of the voltage supply source, and the voltage drop of the voltage applied to the circuit under test of another integrated circuit chip Can be prevented.

  Further, the test method of the present invention includes the plurality of signal generation circuits formed on the semiconductor wafer so as to correspond to the respective circuits under test based on voltages supplied to the circuits under test. A signal generation step for generating a control signal for controlling the operation of the circuit may be included.

  According to the above method, the signal generation circuit formed on the semiconductor wafer generates a control signal for controlling the operation of the circuit under test based on the voltage supplied to the circuit under test. There is no need to provide a terminal for inputting a control signal from the outside on the wafer. Therefore, the number of terminals formed on the semiconductor wafer can be reduced.

  The test method of the present invention stops the supply of control signals from the signal generation circuit to the circuit under test when it is determined in the determination step that a current of a predetermined value or more is flowing through the circuit under test. The signal stop process to perform may be included. According to the above method, when a current of a predetermined value or more flows in the circuit under test, the supply of the control signal to the circuit under test can be stopped by the signal stop means.

  Another test method of the present invention is a test method for inspecting the characteristics of each circuit under test by simultaneously applying a voltage to a plurality of circuits under test formed on a semiconductor wafer in order to solve the above-mentioned problems. A voltage supply step for supplying a voltage to each of the circuits under test and a plurality of signal generation circuits formed on the semiconductor wafer so as to correspond to the circuits under test, respectively. And a signal generation step of generating a control signal for controlling the operation of the circuit under test based on the voltage.

  According to the above method, the signal generation circuit formed on the semiconductor wafer generates a control signal for controlling the operation of the circuit under test based on the voltage supplied to the circuit under test. There is no need to provide a terminal for inputting a control signal from the outside on the wafer. Therefore, the number of terminals formed on the semiconductor wafer can be reduced.

  As described above, the semiconductor device of the present invention is a semiconductor device in which a plurality of integrated circuit chips are formed on a semiconductor wafer, and the integrated circuit chip is characterized by a voltage supplied from an external voltage supply means. A circuit under test to be tested, and a current interrupt circuit for interrupting the current to the circuit under test when the current value of the current supplied from the voltage supply means exceeds a predetermined value. ing.

  The test apparatus of the present invention is a test apparatus for inspecting the characteristics of each circuit under test by simultaneously applying a voltage to a plurality of circuits under test formed on a semiconductor wafer, and applied to the circuit under test. Voltage supply means for supplying a voltage to be output, an output terminal provided for each of the circuits under test, for outputting the voltage supplied from the voltage supply means to the circuit under test, the output terminals, and the voltage supply And a current interrupting circuit for interrupting the current to the output terminal when the current value of the current flowing through the output terminal exceeds a predetermined value.

  The test method of the present invention is a test method for inspecting the characteristics of each circuit under test by simultaneously applying a voltage to a plurality of circuits under test formed on a semiconductor wafer. A voltage supply step for supplying a voltage; a determination step for determining whether a current value of a current flowing through each of the circuits under test is equal to or greater than a predetermined value; and a determination that a current equal to or greater than the predetermined value is flowing in the determination step A current interrupting step for interrupting current to the circuit under test.

  According to the semiconductor device, the test device, and the test method described above, the current flowing from the voltage supply source provided outside the semiconductor device to the defective chip is prevented from exceeding the current supply capability of the voltage supply source. It is possible to prevent the voltage drop applied to the circuit under test of the chip from occurring.

  Another semiconductor device of the present invention is a semiconductor device in which a plurality of integrated circuit chips are formed on a semiconductor wafer, and the integrated circuit chip has a characteristic depending on a voltage supplied from an external voltage supply means. A circuit under test to be inspected and a signal generation circuit for generating a control signal for controlling the operation of the circuit under test based on the voltage supplied from the voltage supply means.

  Another test method of the present invention is a test method for inspecting the characteristics of each circuit under test by simultaneously applying a voltage to a plurality of circuits under test formed on a semiconductor wafer. A voltage supply step for supplying a voltage to the circuit, and a plurality of signal generation circuits formed on the semiconductor wafer so as to correspond to the respective circuits under test, based on the voltages supplied to the circuits under test. A signal generation step of generating a control signal for controlling the operation of the circuit under test.

  According to the semiconductor device and the test method, the signal generation circuit formed on the semiconductor wafer generates a control signal for controlling the operation of the circuit under test based on the voltage supplied to the circuit under test. Therefore, it is not necessary to provide a terminal for inputting a control signal from the outside on the semiconductor wafer. Therefore, the number of terminals formed on the semiconductor wafer can be reduced.

  An embodiment of the present invention will be described. FIG. 1 is a block diagram showing a configuration of a semiconductor device 10 according to the present embodiment.

  As shown in this figure, the semiconductor device 10 includes a plurality of chips (integrated circuit chips) 20 on a wafer 4. Each chip 20 includes a current interrupt circuit 1, a test signal transmission circuit 2, and a circuit under test 3.

  The current cutoff circuit 1 cuts off the current when the current value of the current supplied from the voltage supply source 5 to the circuit under test 3 exceeds a predetermined value. In other words, the current interrupt circuit 1 has a function for detecting an overcurrent and between the voltage supply source 5 and the circuit under test 3 (the circuit under test 3 and the test signal transmission circuit 2) when the overcurrent is detected. It has a function to shut off. The voltage supply source 5 is a voltage supply source for applying voltage stress provided in the test apparatus 30 connected to the wafer 4. The voltage supply source 5 is connected to the current interrupt circuit 1 via a voltage stress test terminal (not shown) provided in the semiconductor device 10. The voltage stress test terminal may be provided for each chip or may be provided for each of a plurality of chips.

  FIG. 2 is a circuit diagram illustrating a configuration example of the current interrupt circuit 1. As shown in this figure, the current cutoff circuit 1 includes a current cutoff transistor 11, a current mirror circuit 12 composed of transistors 13a and 13b having the same characteristics, and a current detection resistor 14.

  The source of the current cutoff transistor 11 is connected to the voltage supply source 5 via a voltage stress test terminal (not shown), the drain is connected to the source of the transistor 13a, and the gate is the drain of the transistor 13b. It is connected to the.

  The source of the transistor 13 a is connected to the drain of the current cutoff transistor 11, and the drain is connected to the test signal transmission circuit 2 and the circuit under test 3. The drain of the transistor 13a is also connected to the gates of the transistors 13a and 13b.

  The source of the transistor 13 b is connected to the voltage supply source 5 via a voltage stress test terminal (not shown), and the drain is connected to one end of the current detection resistor 14 and the gate of the current cutoff transistor 11. The other end of the current detection resistor 14 is connected to a ground wiring (GND) (not shown).

  The test signal transmission circuit 2 activates a control signal (activates each member provided in the circuit under test 3) for controlling the operation of each member provided in the circuit under test 3 based on the voltage supplied from the voltage supply source 5. Signal for generating the signal to be generated and input to the circuit under test 3.

  FIG. 3 is a block diagram illustrating a configuration example of the test signal transmission circuit 2. As shown in this figure, the test signal transmission circuit 2 includes an oscillator 31 and a logic circuit 32.

  FIG. 7 shows the supply voltage supplied from the voltage supply source 5 to the test signal transmission circuit 2 via the current cutoff circuit 1, the oscillation output of the oscillator 31, and the control signal (test signal) output from the logic circuit 32. It is a waveform diagram.

  As shown in this figure, the oscillator 31 oscillates a voltage (current) supplied from the voltage supply source 5 via the current cutoff circuit 1 to generate a clock signal and outputs it to the logic circuit 32.

  The logic circuit 32 operates each member included in the circuit under test 3 based on the supply voltage supplied from the voltage supply source 5 through the current cutoff circuit 1 and / or the clock signal supplied from the oscillator 31. One or more control signals for controlling the control signal are generated, and the generated control signals are output to the circuit under test 3. Further, the logic circuit 32 has a function of detecting a voltage drop when the voltage supply from the voltage supply source 5 is stopped. When this voltage drop is detected, the output (each control signal) is fixed to a low state.

  Note that the waveform of each control signal may be appropriately set so that the circuit under test 3 performs a desired operation according to the configuration of the circuit under test 3. For example, control for causing each member provided in the circuit under test 3 to perform a desired operation according to the timing at which the voltage supply from the voltage supply source 5 is started, the number of oscillations of the oscillation signal output from the oscillator 31, and the like. The logic circuit 32 may be formed so as to generate a signal.

  Here, the operation of the current interrupt circuit 1 will be described. FIG. 4 is an explanatory diagram showing the operation of the current interrupt circuit 1 when the circuit under test 3 connected to the current interrupt circuit 1 is a non-defective product.

  The current cutoff transistor 11 has a gate voltage connected to GND via the current detection resistor 14 and is in an ON state as a semiconductor switch. At this time, the current value of the current 101 (current flowing through the point B shown in the figure) passing through the current cutoff transistor 11 and the transistor 13a is, for example, the μA level or less. Further, the current mirror circuit 12 causes a current 102 having the same current value as the current 101 (current flowing through the point A shown in the drawing) to flow from the voltage supply source 5 to the current detection resistor 14 via the transistor 13b. At this time, the potential at the end of the current detection resistor 14 on the transistor 13b side (the potential at the point A shown in the figure) is the product of the resistance value of the current 102 and the current detection resistor 14 according to Ohm's law. The potential is not a potential for turning off the current cutoff transistor 11 (semiconductor switch). That is, when the circuit under test 3 is a non-defective product, the current 101 is not an overcurrent (because it is a current of μA level or less, for example), so the potential of the gate of the current cutoff transistor 11 is the current cutoff transistor. The current cutoff transistor 11 is maintained in the ON state because the potential is lower than the potential for blocking the current 11. Therefore, a stress voltage is applied from the voltage supply source 5 to the test signal transmission circuit 2 and the circuit under test.

  Next, the operation of the current interrupt circuit 1 when the circuit under test 3 connected to the current interrupt circuit 1 is defective will be described. FIG. 5 is an explanatory diagram showing the operation of the current interrupting circuit 1 when there are defective chips that cause a large current to flow due to an internal failure in many integrated circuit chips 20 to which voltage stress is applied.

  When the circuit under test 3 connected to the current interrupt circuit 1 causes a large current to flow due to an internal failure or the like, the current 103 passes through the current interrupt transistor 11 and the transistor 13a (for example, a large current of several mA to several tens mA or more). Current (overcurrent)) flows. Then, the current 104 having the same current value as the current 103 flows through the current detection resistor 14 by the current mirror circuit 12.

  The potential at the end of the current detection resistor 14 on the transistor 13b side (the potential at point A shown in the figure) is the product of the current value of the current 104 and the resistance value of the current detection resistor 14 based on Ohm's law. Become. For this reason, the gate voltage of the current cutoff transistor 11 rises, and the semiconductor switch is turned off, and the voltage (current) supply from the voltage supply source 5 to the test signal transmission circuit 2 and the circuit under test 3 is cut off. In other words, the resistance value of the current detection resistor 14 is set such that the potential at the point A becomes a potential for blocking the current blocking transistor 11 when a current of a predetermined current value or more flows through the current detection resistor 14. By setting to, voltage (current) supply from the voltage supply source 5 to the test signal transmission circuit 2 and the circuit under test 3 can be cut off when a current of a predetermined current value or more flows.

  As a result, the current flowing from the voltage supply source 5 to the defective chip can be prevented from exceeding the current supply capability of the voltage supply source 5, and the voltage drop of the stress voltage applied to other integrated circuit chips can be prevented.

  As described above, in the semiconductor device 10 according to the present embodiment, the current interrupt circuit 1 is provided in each of the plurality of integrated circuit chips 20 formed on the wafer 4. Thereby, when the circuit under test 3 provided in any of the integrated circuit chips 20 is a defective product in which a large current flows when voltage stress is applied, the current flowing through the circuit under test 3 can be cut off. Therefore, the current flowing from the voltage supply source 5 to the defective chip is prevented from exceeding the current supply capability of the voltage supply source 5, and the voltage drop of the stress voltage applied to the circuit under test 3 of the other integrated circuit chip 20 is prevented. can do.

  Further, even if the integrated circuit chip 20 and the defective chip are non-defective, those in which a large current does not flow when voltage stress is applied can be appropriately applied with voltage stress.

  In addition, the semiconductor device 10 according to the present embodiment includes an oscillator 31 that generates a clock signal by oscillating a voltage supplied from the voltage supply source 5 via the current cutoff circuit 1, and a current cutoff circuit 1 from the voltage supply source 5. One or more control signals for controlling the operation of each member provided in the circuit under test 3 are generated based on the supply voltage supplied via the oscillator 31 and / or the clock signal supplied from the oscillator 31 The test signal transmission circuit 2 includes a logic circuit 32 that outputs the generated control signals to the circuit under test 3.

  As a result, the test signal transmission circuit 2 generates a signal for causing the internal oscillator 31 to generate a clock when the power supply voltage is supplied, and for the logic circuit 32 to activate the circuit under test 3 according to the clock (circuit under test). 3 is generated and output to the circuit under test 3. Therefore, it is not necessary to input a control signal for controlling the operation of the circuit under test 3 to each integrated circuit chip 20, and it is only necessary to input a stress voltage to each integrated circuit chip 20. The number of probe card needles to be brought into contact with each other (the number of input terminals necessary for inputting a control signal to each integrated circuit chip 20) is reduced, and a number of integrated circuit chips 20 are simultaneously activated to reduce voltage stress. Can be applied simultaneously.

  In the present embodiment, the configuration in which the current cutoff circuit 1 is provided in the integrated circuit chip 20 has been described. However, the present invention is not limited to this. For example, as shown in FIG. 6, you may provide the electric current interruption circuit 1 in the test apparatus 30 side. Also in this case, the same effect as the case where the integrated circuit chip 20 is provided with the current interrupt circuit 1 is obtained. In addition, since it is not necessary to build the current interrupt circuit 1 in each semiconductor device 10, the manufacturing process of the semiconductor device 10 can be simplified.

  In the present embodiment, the configuration in which each integrated circuit chip 20 includes the test signal transmission circuit 2 has been described. However, the configuration is not limited to this, and the integrated circuit chip 20 may not include the test signal transmission circuit 2. Good. In this case, when it is necessary to supply a control signal for controlling the operation of each member of the circuit under test 3, an input terminal for inputting the control signal to each integrated circuit chip 20 may be provided.

  In the present embodiment, each integrated circuit chip 20 is provided with an input terminal for inputting a supply voltage from the voltage supply source 5, but the present invention is not limited to this. For example, an input terminal for inputting a supply voltage from the voltage supply source 5 may be provided for each of the plurality of integrated circuit chips. In addition, when providing the input terminal for inputting the supply voltage from the voltage supply source 5 for every some integrated circuit chip, it is preferable to provide the electric current interruption circuit 1 in each integrated circuit chip.

  Further, the input terminal for inputting the supply voltage from the voltage supply source 5 to each integrated circuit chip 20 may be provided individually for testing in the wafer state, and the integrated circuit chip 20 is commercialized. In this case, a terminal for inputting a supply voltage from the outside may be used for a test in a web state.

  Further, according to the present invention, in a semiconductor device in a wafer state having a plurality of integrated circuit chips, the voltage stress application wiring is divided into scribe lines (dividing each integrated circuit chip) with respect to the integrated circuit chips having independent power supply systems. When the current from the voltage stress application wiring flows into the integrated circuit chip over a specified amount (specified current value), the current is cut off to cut off the current supplied to the integrated circuit chip. Each integrated circuit chip includes a circuit and a test signal generation circuit that is driven by a current (voltage) from the current cutoff circuit and generates a test signal (control signal) for the circuit under test provided in the integrated circuit chip. It can also be expressed as a configuration.

  In this embodiment, an example in which a stress voltage is applied to the circuit under test 3 has been described. However, the application target of the present invention is not limited to this, and a plurality of integrated circuit chips formed on the wafer 4 are simultaneously applied. Any configuration that applies a voltage is applicable.

  The present invention is not limited to the above-described embodiments, and various modifications can be made within the scope of the claims. That is, embodiments obtained by combining technical means appropriately changed within the scope of the claims are also included in the technical scope of the present invention.

  The present invention applies a voltage simultaneously to a semiconductor device in which a plurality of integrated circuit chips are formed on a wafer 4 and a plurality of integrated circuit chips formed on the wafer using a probe card and a prober. Applicable to testing equipment.

1 is a block diagram showing a configuration of a semiconductor device and a test apparatus according to an embodiment of the present invention. FIG. 2 is a circuit diagram showing a configuration of a current interrupt circuit provided in the semiconductor device shown in FIG. 1. FIG. 2 is a circuit diagram showing a configuration of a test signal transmission circuit provided in the semiconductor device shown in FIG. 1. FIG. 3 is an explanatory diagram showing an operation of the current interrupt circuit when the circuit under test is a non-defective product in the semiconductor device shown in FIG. 1. In the semiconductor device shown in FIG. 1, it is explanatory drawing which shows operation | movement of a current interruption circuit in case a to-be-tested circuit is a defective product through which a large current flows when voltage stress is applied. It is a block diagram which shows the modification of the semiconductor device and test device concerning one Embodiment of this invention. FIG. 4 is a waveform diagram of a supply voltage supplied to a test signal transmission circuit shown in FIG. 3, an oscillation output of an oscillator, and a control signal output from a logic circuit.

Explanation of symbols

1 Current interruption circuit 2 Test signal transmission circuit (signal generation circuit)
3 Circuit under test 4 Wafer (semiconductor wafer)
5 Voltage supply source (voltage supply means)
10 Semiconductor Device 11 Current Interrupting Transistor (First Transistor)
12 current mirror circuit 13a transistor (second transistor)
13b Transistor (third transistor)
14 Current detection resistor (resistance means)
20 Integrated Circuit Chip 30 Test Equipment 31 Oscillator (Transmission Circuit)
32 logic circuits

Claims (12)

In a semiconductor device in which a plurality of integrated circuit chips are formed on a semiconductor wafer,
The integrated circuit chip is
A circuit under test whose characteristics are inspected by a voltage supplied from an external voltage supply means;
A semiconductor device comprising: a current cutoff circuit for cutting off a current to the circuit under test when a current value of a current supplied from the voltage supply means exceeds a predetermined value. The current interrupt circuit is
Current detection means for generating a potential corresponding to the current value of the current supplied from the voltage supply means;
2. The semiconductor device according to claim 1, further comprising: a cutoff unit that cuts off a current to the circuit under test when a potential generated by the current detection unit exceeds a set value. The current interrupting means is
Comprising first to third three transistors and resistance means;
The first transistor has a source connected to an input terminal for receiving a current supplied from the voltage supply means, a drain connected to the source of the second transistor, and a gate connected to the drain of the third transistor. And
The drain of the second transistor is connected to the circuit under test, the gate of the second transistor itself, and the gate of the third transistor,
The third transistor has a source connected to an input terminal for receiving a current supplied from the voltage supply means, and a drain connected to the gate of the first transistor and one end of the resistance means.
2. The semiconductor device according to claim 1, wherein the other end of the resistance means is connected to a wiring having a constant potential. The integrated circuit chip is
4. A signal generation circuit for generating a control signal for controlling the operation of the circuit under test based on a voltage supplied from the voltage supply means. A semiconductor device according to 1. The signal generation circuit is
An oscillation circuit for generating a clock signal by oscillating the voltage supplied from the voltage supply means;
And a logic circuit that generates a control signal for controlling the operation of the circuit under test based on a clock signal generated by the oscillation circuit and / or a voltage supplied from the voltage supply means. The semiconductor device according to claim 4. In a semiconductor device in which a plurality of integrated circuit chips are formed on a semiconductor wafer,
The integrated circuit chip is
A circuit under test whose characteristics are inspected by a voltage supplied from an external voltage supply means;
A semiconductor device comprising a signal generation circuit for generating a control signal for controlling the operation of the circuit under test based on a voltage supplied from the voltage supply means. The signal generation circuit is
An oscillation circuit for generating a clock signal by oscillating the voltage supplied from the voltage supply means;
And a logic circuit that generates a control signal for controlling the operation of the circuit under test based on a clock signal generated by the oscillation circuit and / or a voltage supplied from the voltage supply means. The semiconductor device according to claim 6. In a test apparatus for inspecting the characteristics of each circuit under test by simultaneously applying a voltage to a plurality of circuits under test formed on a semiconductor wafer,
Voltage supply means for supplying a voltage to be applied to the circuit under test;
An output terminal provided for each of the circuits under test, for outputting a voltage supplied from the voltage supply means to the circuit under test;
A current cut-off circuit provided between each of the output terminals and the voltage supply means, for cutting off the current to the output terminal when the current value of the current flowing through the output terminal exceeds a predetermined value. And a test apparatus characterized by comprising: In a test method for inspecting characteristics of each circuit under test by simultaneously applying a voltage to a plurality of circuits under test formed on a semiconductor wafer,
A voltage supplying step for supplying a voltage to each of the circuits under test;
A determination step of determining whether the current value of the current flowing through each of the circuits under test is equal to or greater than a predetermined value;
A test method comprising: a current interrupting step of interrupting a current to a circuit under test determined that a current of a predetermined value or more is flowing in the determination step.   Control for controlling the operation of the circuit under test based on the voltage supplied to the circuit under test by a plurality of signal generation circuits formed on the semiconductor wafer so as to correspond to the circuit under test, respectively. The test method according to claim 9, further comprising a signal generation step of generating a signal.   Including a signal stop step of stopping supply of a control signal from the signal generation circuit to the circuit under test when it is determined in the determination step that a current of a predetermined value or more is flowing through the circuit under test. The test method according to claim 10. In a test method for inspecting characteristics of each circuit under test by simultaneously applying a voltage to a plurality of circuits under test formed on a semiconductor wafer,
A voltage supplying step for supplying a voltage to each of the circuits under test;
Control for controlling the operation of the circuit under test based on the voltage supplied to the circuit under test by a plurality of signal generation circuits formed on the semiconductor wafer so as to correspond to the circuit under test, respectively. And a signal generation step of generating a signal.

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