KR950015176B1 - Ic tester - Google Patents
Ic tester Download PDFInfo
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- KR950015176B1 KR950015176B1 KR1019910023766A KR910023766A KR950015176B1 KR 950015176 B1 KR950015176 B1 KR 950015176B1 KR 1019910023766 A KR1019910023766 A KR 1019910023766A KR 910023766 A KR910023766 A KR 910023766A KR 950015176 B1 KR950015176 B1 KR 950015176B1
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- South Korea
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- signal
- chip
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- transistor
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- G—PHYSICS
- G01—MEASURING; TESTING
- G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
- G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
- G01R31/26—Testing of individual semiconductor devices
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L22/00—Testing or measuring during manufacture or treatment; Reliability measurements, i.e. testing of parts without further processing to modify the parts as such; Structural arrangements therefor
Abstract
Description
제1도는 종래 반도체 집적회로의 시험장치를 나타낸 개략도.1 is a schematic diagram showing a test apparatus for a conventional semiconductor integrated circuit.
제2도는 본 발명의 테스트가 용이한 반도체 칩을 나타낸 회로도.2 is a circuit diagram showing a semiconductor chip that is easy to test the present invention.
* 도면의 주요부분에 대한 부호의 설명* Explanation of symbols for main parts of the drawings
1 : 외부패드 2 : 래치회로1: external pad 2: latch circuit
3 : 신호인가부 4 : 구동부3: signal applying unit 4: driving unit
본 발명은 반도체 집적호로(Integrated Circuit)에 관한 것으로, 특히 테스트를 용이하게 하여 테스트 시간을 단축할 수 있도록 한 반도체 칩에 관한 것이다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor integrated circuit, and more particularly, to a semiconductor chip capable of shortening test time by facilitating testing.
일반적으로 웨이퍼가 팹(Fab)에서 나오게 되면 칩(Chip)마다 테스트를 하게 되는데 프리테스트(Pretest)는 웨이퍼상의 여러개(수십~수백개)의 칩(Chip)중에서 동작을 할 수 있는 칩인가 아닌가를 결정하는 테스트이고, 동작을 하지 못하는 칩(Fail Chip)이 나오면 레이져 리페어(Laser Repair)를 하여 복구할 수 있는 것인가 아닌가를 결정하는 테스트를 포함한다.In general, when a wafer comes out of a fab, each chip is tested. Pretest is a chip capable of operating among several (hundreds to hundreds) of chips on the wafer. It is a test to determine, and if a chip (Fail Chip) that does not work, it includes a test to determine whether it can be repaired by laser repair (Laser Repair).
그리고, 레이져 리페어에 의해 복구된 칩과 완전히 실패(Fail)된 칩, 정상동작을 하는 칩(Good Chip)은 모두 EDS(Electrical Die Sorting) 테스트를 받게 되는데 EDS 테스트는 웨이퍼상의 모든 칩의 전기적 함수적 특성을 체크하게 된다.In addition, chips repaired by laser repair, chips that fail completely, and chips that operate normally are subjected to an electrical die sorting (EDS) test, which is an electrical functional test of all chips on a wafer. The property is checked.
여기서 본 발명은 레이저 리페어를 하여 복구할 수 있느냐 없느냐를 테스트하는 장치이다.Herein, the present invention is a device for testing whether or not laser repair can be performed.
즉, 종래의 리페어블한 직접회로의 시험장치는 제1도와 같이 메모리의 레이져 리페어(Laser Refair) 공정에서 특정회로의 퓨즈 절단여부에 따라 전류가 발생되어 리페어된 칩(Chip)인지 또는 리페어 되지 않은 칩인지를 판단하는 레이저 리페어회로(20), 트랜지스터(Q20), 데이타 아웃 패드(Data Out Pad)(21)로 구성되었다. 이와 같이 구성된 종래 기술은 레이저 리페어 공정에서 메모리의 특정 퓨즈를 절단하면 레이저 리페어회로(20)는 일정신호를 발생하여 트랜지스터(Q20)가 온되므로 데이타 아웃 패드(21)의 전류는 트랜지스터(Q20)를 통해 접지되어 일정칩이 레이저 리페어 공정을 실시하였는지의 구분이 가능했다.That is, in the conventional repair apparatus for a repairable integrated circuit, as shown in FIG. 1, a current is generated depending on whether a fuse is blown in a specific circuit in the laser repair process of a memory, or is it a repaired chip or not repaired. The laser repair circuit 20 determines whether the chip is a chip, a transistor Q 20 , and a data out pad 21. In the conventional technology configured as described above, when the specific fuse of the memory is cut in the laser repair process, the laser repair circuit 20 generates a predetermined signal and the transistor Q 20 is turned on, so that the current of the data out pad 21 is changed to the transistor Q 20. ), It was possible to distinguish whether or not a certain chip performed the laser repair process.
그런데 이와 같은 종래 기술은 단지 집적회로에서 레이저 리페어 공정을 거친 칩인지 아닌지를 구분할 수 있는 일정 칩에 대해서만 검출작업을 할 수 있으므로 정상칩과, 리페어에 의해 복구된 칩, 완전실패된 칩을 구분하기 위해서는 EDS 테스트를 받아야만 한다. 따라서 완전히 실패된 칩도 EDS 테스트를 받아야 하는 문제점이 있었다.However, such a conventional technology can detect only a chip that can distinguish whether or not a chip has undergone a laser repair process in an integrated circuit, and thus, distinguishes between a normal chip, a chip recovered by a repair, and a chip that has failed completely. You must have an EDS test. Therefore, even a completely failed chip had a problem of undergoing an EDS test.
본 발명은 이와 같은 종래의 결점을 감안하여 안출한 것으로 별도로 전기적 퓨즈를 형성하여 불량칩은 퓨즈를 절단하여 표시하여 주므로 불량칩은 EDS테스트를 하지 않도록 하여 테스트 시간을 단축하는데 그 목적이 있다.The present invention has been made in view of the above-mentioned drawbacks. Therefore, since an electric fuse is formed separately and a defective chip is displayed by cutting the fuse, the purpose of the test is to shorten the test time by preventing the defective chip from performing an EDS test.
제2도는 본 발명의 테스트가 용이한 반도체 칩을 나타낸 회로도로서, 저항(R1), 트랜지스터(Q1), 퓨즈(F)로 이루어져 소정의 외부신호인가에 따라 스위칭 수단에 의해 일정신호를 발생하는 신호인가부(3)와, 트랜지스터(Q2~Q4)로 이루어져 신호인가부(3)의 신호를 래치(Ratch)시키는 래치부(2)와, 트랜지스터(Q5~Q6)로 이루어져, 상기 신호인가부(3)의 일정신호 및 소정신호에 따라 데이타 아웃 패드(21)에 일정전류가 흐르거나 그렇지 않도록 동작하는 구동부(4)로 구동된다.2 is a circuit diagram showing a semiconductor chip that can be easily tested according to an embodiment of the present invention, and includes a resistor R 1 , a transistor Q 1 , and a fuse F to generate a predetermined signal by a switching means according to application of a predetermined external signal. It consists of a signal applying section (3), a transistor (Q 2 ~ Q 4 ), a latch unit (2) for latching the signal of the signal applying section (3), and a transistor (Q 5 ~ Q 6 ) In response to the predetermined signal and the predetermined signal of the signal applying unit 3, the driving unit 4 is driven by the driving unit 4 so that a constant current flows in or out of the data out pad 21.
이와 같이 구성된 본 발명은 신호인가부(3)의 외부패드(1)에 전원(Vcc)을 인가하면 트랜지스터(Q1)가 온되어 전원(Vcc)이 접지되므로 퓨즈(F)가 절단되는데, 이를 상세히 설명하면 다음과 같다.According to the present invention configured as described above, when the power supply Vcc is applied to the external pad 1 of the signal applying unit 3, the transistor Q 1 is turned on and the power supply Vcc is grounded, so that the fuse F is cut. It will be described in detail as follows.
먼저 외부 패드(1)에 로우신호를 인가하면 트랜지스터(Q1)는 오프되어 전원(Vcc)이 구동부(4)의 트랜지스터(Q6)에 인가되므로 트랜지스터(Q6)가 온되며 이때, 신호(øt)가 하이이면 트랜지스터(Q5)는 온되어 데이타 아웃 패드(21)가 접지되므로 상기 데이타 아웃 패드(21)에 전압을 인가하면 전류의 흐름을 측정할 수 있다.First, when a low signal is applied to the external pad 1, the transistor Q1 is turned off so that the power supply Vcc is applied to the transistor Q 6 of the driving unit 4, so that the transistor Q 6 is turned on. Is high, the transistor Q 5 is turned on and the data out pad 21 is grounded. Therefore, when a voltage is applied to the data out pad 21, the flow of current can be measured.
상기에 반해서 외부패드(1)에 전원(Vcc)을 인가하면 퓨즈(F)가 절단되어 래치회로(2)에 의해 구동부(4)의 트랜지스터(Q6) 게이트는 접지되므로 신호(øt)에 관계없이 데이타 아웃 패드(21)는 전류경로가 차단되어 데이타 아웃 패드(21)에 전압을 인가해도 전류의 흐름을 측정할 수 없다.On the contrary, when the power supply Vcc is applied to the external pad 1, the fuse F is cut and the gate of the transistor Q 6 of the driving unit 4 is grounded by the latch circuit 2 so that it is related to the signal? T. Without the data out pad 21, the current path is cut off, and even if a voltage is applied to the data out pad 21, the current flow cannot be measured.
또한, 본 발명에서의 래치회로(2)는 저항으로 바꿀 수 있고 저항(R1)도 래치회로로 대치가능하다.In addition, the latch circuit 2 in the present invention can be replaced with a resistor, and the resistor R 1 can also be replaced with a latch circuit.
이상에서 설명한 바와 같이 본 발명은 별도로 전기적 퓨즈(F)를 형성하여 집적회로의 전체 칩을 검출할 수 있도록 함으로써 칩의 특성에 따라 기록/검출이 가능하며 메모리의 경우 프리테스트(Pretest)에서 패일(Fail)된 칩을 EDS(Electrical Die Sorting)에서는 전류의 측정만으로 패일판정이 가능하기 때문에 EDS 시간절약이 가능하며 그레이드(Grade)의 기록/검출에 응용할 수 있는 효과가 있는 것이다.As described above, according to the present invention, an electric fuse F can be separately formed so that the entire chip of the integrated circuit can be detected, and thus recording / detecting can be performed according to the characteristics of the chip. Failed chip can be failed by EDS (Electrical Die Sorting) to measure fail only by measuring current, so it is possible to save EDS time and apply to recording / detecting grade.
Claims (1)
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| KR1019910023766A KR950015176B1 (en) | 1991-12-21 | 1991-12-21 | Ic tester |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| KR1019910023766A KR950015176B1 (en) | 1991-12-21 | 1991-12-21 | Ic tester |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| KR930013750A KR930013750A (en) | 1993-07-22 |
| KR950015176B1 true KR950015176B1 (en) | 1995-12-23 |
Family
ID=19325455
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| KR1019910023766A KR950015176B1 (en) | 1991-12-21 | 1991-12-21 | Ic tester |
Country Status (1)
| Country | Link |
|---|---|
| KR (1) | KR950015176B1 (en) |
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1991
- 1991-12-21 KR KR1019910023766A patent/KR950015176B1/en not_active IP Right Cessation
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| Publication number | Publication date |
|---|---|
| KR930013750A (en) | 1993-07-22 |
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