KR20070002599A - Test device of semiconductor device - Google Patents

Abstract

A test apparatus of a semiconductor device is provided to analyze characteristics and failures of the semiconductor device in a package level by performing EPM(Electric Parameter Monitor) on a test pattern using a pad or input/output pins. A test apparatus of a semiconductor device includes a test pattern, a measuring unit, a selecting unit and a test mode controlling unit. The test pattern is formed on a main chip of the semiconductor device. The test pattern includes predetermined parameters related to device characteristics. The measuring unit is applied with a bias for measuring the predetermined parameters in a package level. The selecting unit(40) is used for applying selectively the bias to the test pattern according to a test mode signal state. The test mode controlling unit(30) is used for controlling a switching operation of the selecting unit by outputting a test mode signal.

Description

Test device of semiconductor device

1 is a block diagram of a test apparatus for a semiconductor device according to the present invention.

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a test device for a semiconductor device, and is a technology for analyzing characteristics and defects of a semiconductor device using a test pattern at a package level of the semiconductor device.

In general, when a defect occurs in any one of a number of fine cells, semiconductor devices such as DRAM and SRAM cannot be used as a defective part and are treated as defective products. However, despite the high probability that defects may occur in only a small number of cells as the degree of integration of semiconductor memory devices increases, discarding them as defective products is an inefficient treatment method that lowers yield.

Accordingly, a conventional DRAM has a test pattern that can test for abnormalities in its manufacturing process. The test pattern described above detects an abnormality in the DRAM fabrication process by analyzing electrical characteristics of each device constituting the DRAM.

In addition, the burn-in test method of the chip test method in the high-frequency semiconductor memory can be largely divided into a wafer level test and a package level test. In the burn-in test method, a word line is enabled by inserting a chip into a chamber having a condition of high voltage and high temperature (83-125 ° C.) higher than the normal operating voltage and temperature, stressing the cell, and then normal again. In this mode, a cell test is performed to determine a pass or fail of a chip state.

Here, in the wafer level test, when the test mode signal becomes high, the test mode enters the test mode, stops the internal voltage generators, and then applies a test voltage of a desired level through the pad from the outside.

In particular, in the prior art, an EPM (Electric Parameter Monitor) evaluation is performed at the wafer level by forming a test pattern on a scribe lane. However, during the package flow, since die sawing is performed based on the scribe lane, it is impossible to perform the EPM evaluation at the package level.

In addition, even if the EPM evaluation is performed at the wafer level, one test pattern is provided per frame rather than one per die. Accordingly, the EPM data evaluated at the wafer level and the data according to the package characteristics do not match with each other, which may cause a problem in collation.

The present invention has been made to solve the above problems, and forms a test pattern related to the characteristics of the device in the main chip of the semiconductor device, and in the test mode of the semiconductor device by using a pad or an input / output pin The purpose is to analyze the characteristics and defects of semiconductor devices at the package level by performing EPM (Electric Parameter Monitor) measurements.

In order to achieve the above object, a semiconductor device testing apparatus includes: a test pattern formed on a main chip of a semiconductor device and including parameters related to characteristics of the device; Measuring means to which a bias is applied for measuring a parameter including a characteristic of a test pattern at a package level; A selector for selectively applying a bias to a test pattern in a state of the test mode signal; And a test mode controller for controlling a switching operation of the selector by outputting a test mode signal having a different state depending on whether the test mode is in the test mode.

In addition, the present invention includes a test pattern formed on the main chip of the semiconductor device comprising parameters related to the characteristics of the device; Measuring means to which a bias is applied for measuring a parameter including a characteristic of a test pattern upon blowing of a fuse at a package level; And an antifuse for selectively applying a bias to the test pattern according to the blowing state of the fuse.

Hereinafter, with reference to the accompanying drawings will be described in detail an embodiment of the present invention.

1 is a block diagram of a test apparatus for a semiconductor device according to the present invention.

The present invention includes pads 10 and 20, a test mode controller 30, a selector 40, and a test pattern 50.

The pads 10 and 20 are used as a means for measuring an electric parameter monitor (EPM) in the test pattern 50 formed on the main chip of the semiconductor device in a specific operation mode. Here, the pads 10 and 20 are provided in the DRAM chip to receive power, an address, data DQ, or a control signal.

In addition, the test mode controller 30 controls the switching operation of the selection unit 40 when the test mode enters, and controls the desired bias to be applied to the test pattern 50 from the specific pads 10 and 20 to control the EPM. Make the measurement possible.

In addition, the selector 40 includes switches SW1 to SW4 for interconnecting the pads 10 and 20 and the test pattern 50. Here, the switch SW1 is connected to the pad 10 and the drain terminal of the NMOS transistor N1, and the switch SW2 is connected to the ground voltage terminal and the drain terminal of the NMOS transistor N1. The switch SW3 is connected to the pad 20 and the gate terminal of the NMOS transistor N1, and the switch SW4 is connected to the ground voltage terminal and the gate terminal of the NMOS transistor N1.

In addition, a test pattern 50 is formed on the main chip of the semiconductor device for key parameters related to the device's characteristics. Here, the test pattern 50 may be formed of the NMOS transistor N1. In the present invention, the EPM for measuring the threshold voltage VT of the NMOS transistor N1 will be described as an embodiment.

The drain terminal of the NMOS transistor N1 is connected to the switches SW1 and SW2, the gate terminal of the NMOS transistor N1 is connected to the switches SW3 and SW4, and the source terminal of the NMOS transistor N1 is connected to the ground voltage terminal.

Referring to the operation of the present invention having such a configuration as follows.

First, in the normal operation mode, the ground voltage is applied to each node of the test pattern 50 to prevent the EPM measurement.

To this end, the test mode control unit 30 outputs the test mode signal TM low in the normal operation mode instead of the test mode. The selector 40 turns off the switches SW1 and SW3 and turns on the switches SW2 and SW4 when the test mode signal TM is applied low. Accordingly, the ground voltage is applied to the gate terminal and the drain terminal of the NMOS transistor N1.

On the other hand, when entering the test mode for measuring the EPM, the test mode controller 30 outputs the test mode signal TM high. Accordingly, when the test mode signal TM is applied high, the selector 40 turns on the switches SW1 and SW3 and turns off the switches SW2 and SW4. Accordingly, bias voltages applied from the specific pads 10 and 20 are applied to the NMOS transistors N1 of the test pattern 50, respectively, so that the EPM measurement can be performed.

Meanwhile, in the exemplary embodiment of the present invention, the pads 10 and 20 have been described as means for measuring the EPM of the test pattern 50. However, the present invention is not limited thereto, and the present invention is not limited thereto. The device's characteristics and failures can also be analyzed by measuring EPM parameters using input / output pins.

In addition, although the test mode is used as a method for measuring the EPM in the embodiment of the present invention, the present invention is not limited thereto, and an anti-fuse method may be used as the method for measuring the EPM.

That is, when blowing the anti-fuse, the pads 10 and 20 and the test pattern 50 are always connected so that the EPM measurement is possible. The EPM measurement method using the antifuse may be usefully used for failure analysis when the post process flow is not performed.

In addition, the EPM measuring method using the anti-fuse enables the EPM data of the test pattern 50 to be always measured through the pads 10 and 20 even if the test mode is not entered after the fuse is blown. Accordingly, there is an advantage that can be monitored in the bench (Bench) equipment for measuring the EPM.

The present invention tests the main parameters through the EPM directly on the DRAM chip to match the AC / DC characteristic data and the EPM data at the package level in a chip-to-chip manner. Will be available. In addition, it is possible to directly test the EPM properties of the defective material at the package level.

As described above, the present invention provides the following effects.

First, a test pattern is formed in a main chip of a semiconductor device to measure EPM so that EPM characteristics of the chip can be directly matched.

Second, by measuring the EPM in test mode or anti-fuse using the pad used for DRAM, it is easy to measure the chip's EPM at the package level.

Third, it is possible to directly compare and analyze the AC / DC characteristics and EPM characteristics data at the package level to analyze the characteristics and defects of the semiconductor device to improve the characteristics and reliability of the device.

In addition, a preferred embodiment of the present invention is for the purpose of illustration, those skilled in the art will be able to various modifications, changes, substitutions and additions through the spirit and scope of the appended claims, such modifications and changes are the following claims It should be seen as belonging to a range.

Claims (9)

A test pattern formed on a main chip of a semiconductor device, the test pattern including parameters related to characteristics of the device; Measuring means to which a bias is applied for measuring a parameter including a characteristic of said test pattern at a package level; A selector configured to selectively apply the bias to the test pattern according to a state of a test mode signal; And And a test mode controller configured to control a switching operation of the selector by outputting a test mode signal having a different state depending on whether the test mode is in a test mode. The test apparatus of claim 1, wherein the measuring means is an input / output pad provided in the semiconductor device. The test apparatus of claim 1, wherein the measuring means is an input / output pin provided in the semiconductor device. The test apparatus of claim 1, wherein the test pattern is an NMOS transistor device. The method of claim 4, wherein the selection unit A first switch connecting the measurement means and a drain terminal of the NMOS transistor element when the test mode signal is activated; A second switch connecting the measurement means and a gate terminal of the NMOS transistor element when the test mode signal is activated; A third switch connecting a ground voltage terminal and a drain terminal of the NMOS transistor element when the test mode signal is inactivated; And And a fourth switch connecting the ground voltage terminal and the gate terminal of the NMOS transistor element when the test mode signal is inactivated. A test pattern formed on a main chip of a semiconductor device, the test pattern including parameters related to characteristics of the device; Measuring means to which a bias is applied for measuring a parameter including a characteristic of said test pattern when blowing a fuse at a package level; And And an antifuse for selectively applying the bias to the test pattern according to the blowing state of the fuse. The test apparatus of claim 6, wherein the measuring means is an input / output pad provided in the semiconductor device. The test apparatus of claim 6, wherein the measuring means is an input / output pin provided in the semiconductor device. The semiconductor device test apparatus of claim 6, wherein the test pattern is an NMOS transistor device.

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