JP2005140759A - Semiconductor integrated circuit and failure detection method for semiconductor integrated circuit - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a semiconductor integrated circuit that highly accurately detects a leak current component due to failure with variations reduced in a background current without cutting off the supply of power to functional circuit blocks, when performing IDDQ test on the integrated circuit using a micro-process, and to provide a test method. <P>SOLUTION: A block supply selection circuit 10 is provided for selecting a specific functional circuit block based on a control signal from among the plurality of functional circuit blocks constituting the semiconductor integrated circuit, and for outputting, as an internal clock, a clock signal inputted from an external terminal to the selected functional circuit block. When performing IDDQ test, transistors toggled by an external clock signal input are limited only to transistors in the functional circuit block selected by the selection circuit 10 to reduce variations in the background current caused by a change of state of unselected functional circuit blocks. <P>COPYRIGHT: (C)2005,JPO&NCIPI

Description

  The present invention relates to a structure of a semiconductor integrated circuit and a failure detection method for the semiconductor integrated circuit, and more particularly to a structure capable of easily detecting a failure of a fine CMOS integrated circuit.

  In recent years, along with process miniaturization and gate scale expansion of CMOS (Complementary Metal Oxide Semiconductor) integrated circuits, failure modes such as inter-wire short-circuits and transistor leaks, which are difficult to detect by inspection using test patterns such as scan and function test, have occurred. It has become prominent. The IDDQ test is effective as a method for detecting such a failure, and a more accurate IDDQ test method has been developed.

  In the CMOS circuit in the steady state, the IDDQ test usually has a very small power supply current (hereinafter referred to as a quiescent power supply current) flowing. If there is a fault in the circuit, the IDDQ test is several times that in the steady state. Using the characteristic that current flows, the static power supply current is measured at several measurement points while changing the internal state of the CMOS circuit, and the measurement result is compared with a predetermined reference value to be present in the circuit. The failure to be detected is detected.

  In the IDDQ test, all transistors to which power is supplied are to be tested, so it is possible to detect failures that cannot be detected by the function test. In addition, by performing as many internal nodes as possible during the IDDQ test and increasing the number of measurement points for measuring the quiescent power supply current, it is possible to detect a failure with very high accuracy.

  However, due to further progress in process miniaturization technology in recent years, semiconductor integrated circuits in which transistors exceeding 10 million are integrated using transistors having a channel length of 0.15 micrometers or less have been developed. In semiconductor integrated circuits, the power supply voltage has been lowered due to miniaturization, the leakage current generated due to the failure in the circuit has been reduced, and there has been a failure in the circuit due to the increase in the off-current of the transistor. Even if it does not, the increase of the background current which flows is remarkable. When the IDDQ test is executed using such a semiconductor integrated circuit, the following problems may occur.

  For example, FIGS. 18A, 18B, and 18C show, in a semiconductor integrated circuit composed of a plurality of functional circuit blocks, the internal states of the plurality of functional circuit blocks are changed, and seven measurement points are used. It is a figure showing the dispersion | variation in the measured value for each functional circuit block at the time of measuring a stationary power supply current. In the following, the case where the quiescent power supply current is measured at one measurement point is defined as one cycle. Further, FIG. 18D is obtained by adding the measured values for each cycle of FIGS. 18A to 18C, and in the actual IDDQ test, the measured value is measured for each cycle. Comparison with a predetermined reference value is performed.

  Here, in the internal state at the time of the third cycle measurement of the functional circuit block shown in FIG. 18B, the measured value of the quiescent power supply current is prominent, and there is a failure in the functional circuit block in which the abnormal current is detected. Can be determined.

  However, during the IDDQ test, since all the transistors are the test targets as described above, actually, the quiescent power supply current of the entire circuit is measured as shown in FIG. Will do. At this time, if the ratio of the background current component to the current flowing in the steady state of the CMOS circuit becomes larger than the leakage current component due to the failure, the stationary power supply in the third cycle in FIG. Although the measured value of the current should be prominent compared with the measured value of the other cycle in which no failure is detected, the variation of the background current measured in the other cycle as shown in FIG. It can happen to be hidden.

  In such a state, it becomes difficult to set a determination standard for the measured quiescent power supply current, and it is necessary to set a determination standard with a certain margin. If a failure inspection is performed under such a criterion, an outflow of defective products is inevitably increased. Further, another problem of such IDDQ test is that even if a failure is detected in the semiconductor integrated circuit under test because all the transistors supplied with the power to be measured are the test target, The point is that it is difficult to specify the location.

  As a conventional countermeasure for the above problem, for example, as described in Patent Document 1, when performing an IDDQ test in a semiconductor integrated circuit composed of a plurality of functional circuit blocks, each functional circuit block There is one that reduces the influence of the background current when measuring the quiescent power supply current by controlling the power supply to the power supply, and identifies the faulty functional circuit block. Hereinafter, a conventional IDDQ test circuit described in Patent Document 1 will be described with reference to FIG.

  In FIG. 19, 100A is a semiconductor integrated circuit composed of a plurality of functional circuit blocks, 101 is an integrated circuit to be tested, 102 to 104 are functional circuit blocks constituting the integrated circuit to be measured 101, and 500 is a power supply path. Each of the current detection circuits that measure the current flowing through 200 is shown.

  The functional circuit blocks 102 to 104 are connected to the external power supply terminal 302 via the power supply path 200 and are connected to the GND terminal 303 via the GND path 201. The functional circuit blocks 102 to 104 are connected to the clock supply terminal 301 via the clock supply path 202 and are connected to the data input terminal 300 via the data input path 203. When the power supply path 200 of the semiconductor integrated circuit 100A is connected to the functional circuit blocks 102 to 104, they are connected via the power supply cutoff circuits 1 to 3, respectively. It is connected to the cutoff circuit control device 4 via 204-206. Further, the connection between the functional circuit blocks 102 to 104 is connected through circuit separation devices 5 and 6.

Next, the operation of the IDDQ test circuit configured as described above will be described.
First, when the IDDQ test is executed, the power supply cutoff circuits 1 to 3 are controlled using the cutoff control device 4 to select a functional circuit block that supplies power.
Next, after the current flowing through the power supply path 200 is measured by the current detection circuit 500, the function circuit block that supplies power is switched, and the current measurement is performed in the same manner.
For example, the current is measured in a state where the cutoff control device 4 is controlled so that only the functional circuit block 102 is supplied with power, and then the cutoff control device 4 is set so that only the functional circuit block 103 is supplied with power. In the same manner, the current is measured, and finally, only the functional circuit block 104 is supplied with power and the current is measured.

By performing the IDDQ test according to such a procedure, it is possible to limit the test target to the functional circuit block unit from all the transistors, and as a result, the proportion of the background current component in the measured current value decreases. Therefore, it becomes possible to detect a leakage current component due to a failure with high accuracy. Further, the failure location can be easily identified by narrowing the test target to the functional circuit block.
JP-A-8-271484

  However, in the conventional IDDQ test, when there is a signal exchange between functional circuit blocks, it is a major premise that the functional circuit block whose power is cut off does not affect other functional circuit blocks.

  For example, when a signal is exchanged between functional circuit blocks, it is predicted that a through current will flow in the test target functional circuit block in the subsequent stage because the output of the functional circuit block whose power is cut off is in a floating state. For this reason, in order to prevent the through current from flowing, it is necessary to install circuit separating devices 5 and 6 that perform operations such as bus hold.

  Further, according to the conventional example, a power supply cutoff circuit is required for each power supply path of each functional circuit block, and it is necessary to take measures to minimize the influence of the voltage drop due to the added power supply cutoff circuit. . As described above, if the means for reducing the influence of the background current during the IDDQ test is to cut off the power supply to the functional circuit block, the configuration of the semiconductor integrated circuit may be complicated.

  The present invention has been made in order to solve the above-described problems. In the IDDQ test of a semiconductor integrated circuit using a fine process, particularly a semiconductor integrated circuit having a channel length of 0.15 micrometers or less, An object of the present invention is to provide a semiconductor integrated circuit capable of performing an IDDQ test with high accuracy by reducing the influence of a background current with a simpler configuration than that of a semiconductor integrated circuit, and a failure detection method for the semiconductor integrated circuit. .

  In order to solve the above problems, a semiconductor integrated circuit according to claim 1 of the present invention is a semiconductor integrated circuit including a plurality of functional circuit blocks that operate in synchronization with an internal clock signal. Clock supply selection that selects one or more functional circuit blocks based on a control signal input from an external terminal and outputs a clock signal input from the external terminal as an internal clock to the selected functional circuit block A circuit is provided.

  A semiconductor integrated circuit according to claim 2 of the present invention operates in synchronization with a clock signal input from an external terminal in a semiconductor integrated circuit composed of a plurality of functional circuit blocks operating in synchronization with an internal clock signal. And a control signal generation circuit that generates and outputs a control signal that controls selection of a functional circuit block, receives an output from the counter, and switches an output content of the control signal every predetermined period; In response to the output of the control signal, one or more functional circuit blocks are selected from the plurality of functional circuit blocks, and a clock signal input from an external terminal is used as an internal clock for the selected functional circuit block. And an output clock supply selection circuit.

  A semiconductor integrated circuit according to a third aspect of the present invention is the semiconductor integrated circuit according to the second aspect, further comprising a control signal output terminal for outputting a control signal output from the control signal generation circuit to the outside. It is characterized by that.

  According to a fourth aspect of the present invention, there is provided a semiconductor integrated circuit according to the second aspect, wherein the semiconductor integrated circuit according to the second aspect generates an address signal indicating a cycle setting value to be output from the memory circuit, and the address signal is And an address generation circuit that outputs the control signal and one or more cycle setting values as an output cycle of the control signal, and a memory that outputs any of the cycle setting values to the control signal generation circuit according to the address signal And a circuit.

  According to a fifth aspect of the present invention, in the semiconductor integrated circuit according to the first aspect, each of the plurality of functional circuit blocks is an independent scan chain.

  A semiconductor integrated circuit according to claim 6 of the present invention is the semiconductor integrated circuit according to claim 5, wherein two or more scan chains among the plurality of independent scan chains share a scan-in terminal. It is characterized by that.

  The semiconductor integrated circuit according to claim 7 of the present invention is the semiconductor integrated circuit according to claim 5, wherein each of the plurality of independent scan chains is a scan of a flip-flop at a final stage constituting each scan chain. The out terminal is feedback-connected to the first scan-in terminal of the scan chain, and each scan chain receives a capture signal input from the outside and performs a capture operation.

  The semiconductor integrated circuit according to an eighth aspect of the present invention is the semiconductor integrated circuit according to the fifth aspect, wherein each of the plurality of independent scan chains is a scan of a flip-flop at a final stage constituting each scan chain. The out terminal is connected to the first scan-in terminal of the scan chain in a feedback manner, and each scan chain receives a capture signal generated by a counter provided in the semiconductor and performs a capture operation.

  A semiconductor integrated circuit according to a ninth aspect of the present invention is the semiconductor integrated circuit according to any one of the first to eighth aspects, wherein the stationary circuit flows through a power supply path that supplies power to the plurality of functional circuit blocks. A current detection circuit that measures a power supply current; a comparator that compares a measurement value of the current detection circuit with a predetermined reference value; and a comparison result output terminal that outputs a comparison result of the comparator to the outside. Features.

  A semiconductor integrated circuit according to a tenth aspect of the present invention is the semiconductor integrated circuit according to the ninth aspect, wherein a trigger signal for controlling a timing at which the current detection circuit measures a quiescent power supply current is generated, and the trigger signal is generated. Is further provided to the current detection circuit.

  A semiconductor integrated circuit according to an eleventh aspect of the present invention is the semiconductor integrated circuit according to the ninth aspect, further comprising a storage circuit that stores the predetermined reference value and outputs the reference value to the comparator. It is characterized by providing.

  A semiconductor integrated circuit according to a twelfth aspect of the present invention is the semiconductor integrated circuit according to the ninth aspect, wherein the storage circuit stores the maximum value and the minimum value of the measurement values measured by the current detection circuit, and the storage And an arithmetic circuit for calculating a difference between a maximum value and a minimum value stored in the circuit and outputting the difference value as a measurement result of the current detection circuit to the comparator.

  According to a thirteenth aspect of the present invention, in the semiconductor integrated circuit according to the ninth aspect, the amount of change in the quiescent power supply current flowing through the power supply path is measured, and the amount of change is equal to or less than a predetermined value. And a current change amount detection circuit that outputs a measurement permission signal for allowing the current detection circuit to perform current measurement when the current detection circuit reaches the current detection circuit.

  A semiconductor integrated circuit according to a fourteenth aspect of the present invention is the semiconductor integrated circuit according to the ninth aspect, wherein an internal temperature of the semiconductor integrated circuit is measured, and the semiconductor integrated circuit is based on the measured temperature and a predetermined temperature correction coefficient. It further comprises a temperature correction circuit that corrects the measurement value of the current detection circuit and outputs the correction value to the comparator as a measurement result of the current detection circuit.

  According to a fifteenth aspect of the present invention, there is provided a semiconductor integrated circuit that measures a quiescent power supply current of a semiconductor integrated circuit composed of a plurality of functional circuit blocks operating in synchronization with an internal clock signal. In a failure detection method for a semiconductor integrated circuit that detects a failure, one or more functional circuit blocks that supply an internal clock are selected, and a predetermined data signal is applied to change the internal state of only the selected functional circuit block. Measure the quiescent power supply current in a predetermined internal state and compare the measured value of the quiescent power supply current with a predetermined reference value to determine pass / fail of the semiconductor integrated circuit to be inspected. A functional circuit block in which a circuit failure is detected or all predetermined functional circuit blocks supply an internal clock Until the quality determination is performed is selected by, and performs the operation to quality judgment of the inspected semiconductor integrated circuit from a selection of said functional circuit blocks.

  According to a sixteenth aspect of the present invention, in the semiconductor integrated circuit test method according to the fifteenth aspect, the pass / fail judgment of the semiconductor integrated circuit to be inspected is determined by the maximum value of the measured value of the quiescent power supply current. The minimum value is stored, a difference value between the maximum value and the minimum value is obtained, and the difference value is compared with a predetermined reference value.

  According to the semiconductor integrated circuit of the first aspect of the present invention, the functional circuit block whose internal state is changed during the IDDQ test is selected and the operation clock is supplied only to the functional circuit block. The influence of the background current on the measurement of the quiescent power supply current can be eliminated with a simple structure as compared with the semiconductor integrated circuit, and a highly accurate IDDQ test can be performed. Further, since only the selected functional circuit block is a test target, it is possible to easily identify the failure location when a failure is detected.

  According to a second aspect of the present invention, in the semiconductor integrated circuit according to the first aspect, the control signal used as an external input in the semiconductor integrated circuit according to the first aspect is generated inside the semiconductor integrated circuit, and is generated at a predetermined cycle. Since the output of the control signal is switched, external input terminals for control signal input can be reduced.

  According to the semiconductor integrated circuit of claim 3 of the present invention, in the invention of claim 2, since the output state of the control signal can be externally output, it is output at the time of pass / fail judgment of the IDDQ test. By detecting the control signal, it is possible to easily identify the malfunctioning functional circuit block.

  According to a semiconductor integrated circuit of a fourth aspect of the present invention, in the invention of the second aspect, the output period of the control signal is variably controlled for each functional circuit block. The internal state of a block can be changed for a long time, and the internal state of a simple functional circuit block can be changed for a short time. This can improve the toggle rate during IDDQ testing and shorten the test time. It becomes.

  According to the semiconductor integrated circuit of claim 5 of the present invention, since each of the functional circuit blocks is configured as a scan chain in the invention according to any one of claims 1 to 4, the target The number of times of quiescent power supply current measurement for achieving the toggle rate can be reduced, and the test time can be shortened.

  According to the semiconductor integrated circuit of the sixth aspect of the present invention, in the invention of the fifth aspect, the scan-in terminal is shared for two or more functional circuit blocks. By providing independent scan-in terminals for functional circuit blocks, and sharing multiple scan-in terminals when there are multiple simple functional circuit blocks, the number of scan-in terminals can be increased without increasing the length of scan data. It can be deleted.

  According to a seventh aspect of the present invention, in the semiconductor integrated circuit according to the fifth aspect, the scan data is generated by the functional circuit block itself, and each functional circuit block receives a capture signal. Since the capture operation is performed, a pattern generator for creating scan data becomes unnecessary, and external input terminals and external output terminals required for scan-in and scan-out can be reduced.

  According to the semiconductor integrated circuit of claim 8 of the present invention, since the capture signal is generated internally in the invention of claim 7, the number of capture signal input terminals can be reduced.

  According to a ninth aspect of the present invention, in the semiconductor integrated circuit according to any one of the first to eighth aspects, the current detection circuit used for the IDDQ test and the measured value of the current detection circuit And a predetermined reference value are built in, and the current detection circuit receives the output of the trigger signal and measures the quiescent power supply current at a predetermined timing. The inductance component can be suppressed as compared with the case of using it, and the quiescent power supply current can be measured faster than the conventional case. Further, since an external current detection circuit is not required, the IDDQ test can be performed even in an environment where it is difficult to connect the current detection circuit for each integrated circuit, such as after MCM packaging or after mounting on a substrate.

  According to the semiconductor integrated circuit of claim 10 of the present invention, in the invention of claim 9, since the trigger signal is generated inside the semiconductor integrated circuit, the external input terminal of the semiconductor integrated circuit Can be reduced.

  According to the semiconductor integrated circuit of claim 11 of the present invention, in the invention of claim 9, the reference value output to the comparator is stored in a memory circuit in the semiconductor integrated circuit. Thus, the number of external input terminals of the semiconductor integrated circuit can be reduced.

  According to the semiconductor integrated circuit of the twelfth aspect of the present invention, in the invention of the ninth aspect, the IDDQ test is performed using a difference value between the maximum value and the minimum value of the measured quiescent power supply current. As a result, the influence of the background current on the measured value of the quiescent power supply current is large, and even when it is difficult to set the pass / fail judgment criteria of the IDDQ test for the measured value of the quiescent power supply current itself, it is highly accurate. IDDQ test can be performed.

  Further, according to a semiconductor integrated circuit of a thirteenth aspect of the present invention, in the invention according to the ninth aspect, a stationary power supply is generated by a measurement permission signal output when the amount of change in the power supply current reaches a predetermined value or less. Since the current measurement is started, it is not necessary to wait unnecessarily for a long time until the steady state suitable for the measurement of the quiescent power supply current is reached, and the IDDQ test time can be greatly shortened.

  According to a fourteenth aspect of the present invention, in the semiconductor integrated circuit according to the ninth aspect, the temperature correction is performed on the measured value of the quiescent power supply current by measuring the temperature inside the semiconductor integrated circuit. Therefore, the IDDQ test can be performed without considering the temperature characteristics of the quiescent power supply current.

Embodiments of the present invention will be described below with reference to the drawings.
(Embodiment 1)
FIG. 1 is a block diagram showing a configuration of a semiconductor integrated circuit 100A according to the first embodiment of the present invention. In addition, the same code | symbol is used about the same component as FIG. 19 demonstrated previously, and description is abbreviate | omitted.

  In FIG. 1, the clock supply selection circuit 10 externally inputs one or more functional circuit blocks for supplying a clock signal taken in via an external terminal from among a plurality of functional circuit blocks constituting the semiconductor integrated circuit 100A. A selection is made based on the control signal, and a clock signal is supplied to the selected functional circuit block. The clock supply selection circuit 10 is provided on a clock supply path from the clock supply terminal 301 to the functional circuit blocks 102 to 104, and takes in an external clock signal from the clock supply terminal 301 via the clock supply path 202. In addition, in order to supply the external clock signal thus fetched to the functional circuit blocks 102 to 104 as an internal clock, via independent functional circuit block clock supply paths (hereinafter referred to as block clock supply paths) 207 to 209. The functional circuit blocks 102 to 104 are connected.

  The clock supply control terminals 304 and 305 output control signals from the terminals to the clock supply selection circuit 10. In the first embodiment, each of the clock supply control terminals 304 and 305 outputs a 1-bit signal, and controls the clock supply selection circuit 10 based on a 2-bit control signal based on a combination of the two signals. . The clock supply control terminals 304 and 305 are connected to the clock supply selection circuit 10 via clock supply control paths 210 and 211.

Next, the operation of the semiconductor integrated circuit 100A configured as described above will be described with reference to FIG.
FIG. 2 is a timing chart showing the operation of the semiconductor integrated circuit 100A described in the first embodiment. In FIG. 2, CLK 202 is a clock signal input from the clock supply terminal 301, CLKCNT 210 and 211 are output contents of control signals output from the clock supply control terminals 304 and 305, and 207, 208 and 209 are clock supplies. The output state of the clock signal output from the selection circuit 10 to the functional circuit blocks 102, 103, 104 is shown. The internal state of 102, 103, 104 is a schematic diagram of the internal state of the functional circuit blocks 102-104. , Points for measuring the IDDQ test are shown.

  First, the clock supply selection circuit 10 selects a functional circuit block that supplies an external clock signal fetched from the clock supply terminal 301 based on a combination of control signals input from the clock supply control terminals 304 and 305.

  For example, when the control signal input from the clock supply control terminals 304 and 305 is 305: 304 = 00 as indicated by CLKCNT 210 and 211, the functional circuit block selected by the clock supply selection circuit 10 is 102 in advance. Similarly, when the clock supply selection circuit 10 is set, the function circuit block 103 is selected when 305: 304 = 01, and the function circuit block 104 is selected when 305: 304 = 10.

  Thus, if the control signals from the clock supply control terminals 304 and 305 are 00, the clock supply selection circuit 10 can supply the internal clock only to the functional circuit block 102 and change its internal state. If the control signal is switched to 01, the clock supply selection circuit 10 stops supplying the clock signal to the functional circuit block 102, and instead supplies the internal clock only to the functional circuit block 103 to change its internal state. It becomes possible. Similarly, when the control signal is switched to 10, the clock supply selection circuit 10 stops the supply of the clock signal to the functional circuit block 103, and instead supplies the internal clock only to the functional circuit block 104 to change its internal state. It becomes possible.

Next, an IDDQ test method using the semiconductor integrated circuit 100A having the above configuration will be described with reference to FIG.
First, as step 1 (hereinafter referred to as S1. The same applies to step 2 and subsequent steps), a predetermined control signal is applied to clock supply control terminals 304 and 305 to select a functional circuit block to which an external clock is supplied. For example, 305: 304 = 01 is applied to the clock supply control terminals 304 and 305. As a result, the functional circuit block 103 is selected as the clock supply destination.

  Next, in S2, a test pattern is applied from the outside via the data input terminal 300, and a clock signal and a data signal are supplied to the functional circuit block 103 selected in S1. As a result, only the functional circuit block 103 changes its internal state, and the functional circuit blocks 102 and 104 to which no clock signal is supplied are kept in a steady state.

  Next, as S <b> 3, a point at which the quiescent power supply current is measured in a state where the internal state of the functional circuit block 103 is changed is determined in advance, and the quiescent power supply current at the measurement point is measured by the current detection circuit 500. For example, in the first embodiment, measurement at seven measurement points is scheduled, and the quiescent power supply current in each cycle is measured.

Next, as S4, the quality of the semiconductor integrated circuit 100A to be measured is determined based on the measurement result of the quiescent power supply current in S3. The pass / fail judgment is performed by comparing the measurement result of the current detection circuit 500 with a predetermined reference value.
If the determination result is negative, it is determined that there is a failure in the semiconductor integrated circuit 100A to be measured, and the IDDQ test is terminated as a defective product. Here, since only the functional circuit block 103 selected in S1 exists toggling when a failure is detected, the location where the failure occurs also exists in the functional circuit block 103. Can be identified. On the other hand, if the determination result is good, the procedure proceeds to the next step.

  Next, in S5, it is confirmed whether or not the quiescent power supply current has been measured in all internal states previously determined as measurement points when only the functional circuit block 103 is internally changed. For example, in the first embodiment, it is confirmed whether or not all seven cycles of measurement are performed in advance. If the measurement in all the planned internal states has been completed, the process proceeds to the next step. If the measurement has not been completed, the process returns to S2 until the quiescent power supply current is measured in all the planned internal states. , S3, and S4. The procedure after returning to S2 is the same as the procedure described above, and thus the description thereof is omitted.

  Next, in S6, it is confirmed whether or not all of the planned functional circuit blocks have been selected. For example, in the above description, the functional circuit block to which the clock signal is supplied is the functional circuit block 103. However, when the IDDQ test is scheduled even in the state where only the functional circuit block 104 is changed, the clock supply is performed. The functional circuit block selected by the selection circuit 10 is switched to 104. In this case, as described above, 305: 304 = 10 is applied to the clock supply control terminals 304 and 305. As a result, the functional circuit block 104 is selected as the clock supply destination. Since the procedure after the selection of the functional circuit block 104 is the same as the procedure described above, the description thereof is omitted.

  As described above, when the selection of the functional circuit blocks extends to a plurality of functional circuit blocks, it is confirmed whether or not all the selections are completed. If not, the process returns to S1 and the external clock is supplied. Steps S1 to S6 are repeated until all the functional circuit blocks to be scheduled are selected, and all the functional circuit blocks to be planned are selected and a pass / fail judgment is made. On the other hand, when selection of all functional circuit blocks is completed, it is determined that the semiconductor integrated circuit 100A to be measured is a non-defective product, and the IDDQ test is terminated.

Next, the effect when the IDDQ test is performed using the semiconductor integrated circuit 100A having the above-described configuration will be described with reference to FIGS. 4 (a) to 4 (d).
4A, 4 </ b> B, and 4 </ b> C show the values of the static power supply currents flowing in the functional circuit blocks 102, 103, and 104 when the internal state of only the functional circuit block 103 is changed. Yes, the number of internal states (number of measurement cycles) is taken on the horizontal axis, and the quiescent power supply current value in each measurement cycle is taken on the vertical axis. FIG. 4 (d) shows the value of the quiescent power supply current flowing through the integrated circuit to be measured 101 obtained by adding FIGS. 4 (a), (b), and (c), and this value is measured during the IDDQ test. The quality of the semiconductor integrated circuit 100A is determined.

  As described in the previous description of the operation, the internal state only changes in the functional circuit block 103 even when the clock signal and the data signal 300 are applied from the outside, and therefore, as shown in FIGS. 4 (a), 4 (b), and 4 (c). Thus, the measurement variation of the quiescent power supply current occurs only in the functional circuit block 103, and the functional circuit blocks 102 and 104 in which the internal state does not change does not cause a large variation based on the background current. Therefore, as shown in FIG. 4D, the variation in the quiescent power supply current value generated in the functional circuit block 103 is directly reflected in the variation in the quiescent power supply current value measured during the IDDQ test. It is not affected by variations in the background current generated in the circuit block.

  For this reason, as shown in FIG. 4B, even when an increase in leakage current due to a failure occurs in the functional circuit block 103 during the third cycle measurement, it is acceptable without taking a margin as shown in FIG. Since the determination reference value can be set, a highly accurate IDDQ test can be realized.

  As described above, according to the semiconductor integrated circuit 100A of the first embodiment, when performing the IDDQ test, the operation clock is supplied only to a specific functional circuit block, and only the internal state of the functional circuit block is determined. Since the quiescent power supply current is measured while being changed, the influence due to the variation in the background current can be easily removed, and a highly accurate IDDQ test can be performed. Further, since only the selected functional circuit block is a test target, it is possible to easily identify the failure location when a failure is detected.

  In the first embodiment, the case where the number of functional circuit blocks constituting the semiconductor integrated circuit 100A is three has been described. However, even if the semiconductor integrated circuit is composed of N functional circuit blocks, clock supply selection is performed. By increasing the number of bits of the control signal output to the circuit 10 and the block clock supply path, the same effect as in the present embodiment can be obtained.

  Further, although two clock supply control terminals are provided for controlling the clock supply selection circuit 10, the number of clock supply control terminals may be reduced by means such as serially transmitting a control signal.

  In the first embodiment, the case where the clock supply selection circuit 10 selects one functional circuit block has been described. However, a plurality of functional circuit blocks may be selected in order to shorten the test time.

(Embodiment 2)
FIG. 5 is a block diagram showing a configuration of the semiconductor integrated circuit 100B according to the second embodiment of the present invention. In FIG. 5, the same components as those in FIG.
In FIG. 5, reference numeral 12 denotes a counter that operates in synchronization with a clock signal input from the clock supply terminal 301. A control signal generation circuit 11 generates a 2-bit control signal and outputs the control signal to the clock supply selection circuit 10. The output value of the counter 12 is input via the counter output path 213. The control signal performs the same control as the control signal described in the first embodiment.

Next, the operation of the semiconductor integrated circuit 100B configured as described above will be described with reference to FIG.
FIG. 6 is a timing chart showing the operation of the second embodiment. CLK202 represents the clock signal input from the clock supply terminal 301, COUNTER represents the output value of the counter 12, and CLKCNT212 represents the output content of the control signal output from the control signal generation circuit 11.

  First, the counter 12 counts up in synchronization with a clock signal fetched from the outside, and outputs the value to the control signal generation circuit 11. The control signal generation circuit 11 generates a 2-bit control signal from 00 to 11, and every time the count value output from the counter 12 reaches a predetermined value, the control to the clock supply selection circuit 10 is performed. Switches the signal output contents.

  For example, if N is set as the output cycle of the control signal, the control signal generation circuit 11 outputs 00 during the period in which the output value of the counter 12 indicates 0 to N−1, as indicated by CLKCNT212, and N to 2N. -1 is output during the period −1, and 10 is output during the period 2N to 2N−1.

  Here, regarding the combination of the 2-bit control signals, 00 selects the functional circuit block 102, 01 selects the functional clock circuit 103, 10 selects the functional clock circuit 104, and the clock supply selection device 10 in advance. The clock supply selection device 10 switches the functional circuit block that supplies the internal clock from the functional circuit blocks 102 to 103 to 104 every cycle N. Since the subsequent operation of the semiconductor integrated circuit 100B is the same as that of the first embodiment of the present invention, the description thereof is omitted.

  As described above, according to the semiconductor integrated circuit 100B of the second embodiment, the control signal is generated inside the semiconductor integrated circuit 100B, and the output of the control signal is switched at a predetermined cycle. It is possible to reduce the number of control signal input terminals required in the first embodiment, and it is not necessary to input control signals from the outside.

In the second embodiment, since the clock supply selection circuit 10 outputs a 2-bit clock supply control signal, there are four combinations of functional circuit blocks to be selected. By outputting a control signal, 2 ^N selection combinations can be realized.

  In the second embodiment, the up counter is used as the timing generation means for switching the output of the control signal to the clock supply selection circuit 10, but a down counter can also be used. For example, it is possible to set an initial set value N in advance, count down from N, and switch the output of the clock supply control signal when the countdown is completed.

(Embodiment 3)
FIG. 7 is a block diagram showing a configuration of a semiconductor integrated circuit 100C in the third embodiment of the present invention. In FIG. 7, the same components as those in FIG.
In FIG. 7, reference numeral 306 denotes a clock control signal output terminal that allows the control signal output from the control signal generation circuit 11 to the clock supply selection circuit 10 to be externally output, and a signal indicated by CLKCNT 212 in FIG. 6 is output.

  Next, the operation of the semiconductor integrated circuit 100C having the above configuration will be described. First, when the control signal input from the clock supply control terminals 304 and 305 is 305: 304 = 00, the clock supply selection circuit 10 selects the functional circuit block 102, and when 305: 304 = 01, the functional circuit block is selected. 103 and 305: 304 = 10, the function circuit block 104 is selected and the clock supply selection device 10 is set, and the IDDQ test described in the first embodiment is performed based on such setting.

  When it is determined that the semiconductor integrated circuit 100C is defective in the quality determination of the IDDQ test, the control signal output from the clock supply control terminals 304 and 305 when the defect is detected is detected from the clock control signal output terminal 306. To do. At this time, for example, if the control signal 01 is detected, it is determined that the abnormal quiescent power supply current that is the basis for the failure determination is caused by a failure inside the functional block 103 whose internal state is changing. Therefore, it is possible to easily specify that the failure location of the semiconductor integrated circuit 100C to be inspected also exists in the functional circuit block 103.

  As described above, according to the semiconductor integrated circuit of the third embodiment, when a failure is detected in the quality determination of the IDDQ test, the control signal output at the time when the failure is detected is used as the clock control signal output terminal. By detecting from 306, it becomes possible to easily identify the failure location of the semiconductor integrated circuit.

(Embodiment 4)
FIG. 8 is a block diagram showing a configuration of a semiconductor integrated circuit 100D in the third embodiment of the present invention. 8, the same components as those in FIG. 5 are denoted by the same reference numerals, and the description thereof is omitted.
In FIG. 8, the storage circuit 13 stores one or more period setting values indicating periods during which the control signal generation circuit 11 outputs a control signal. The storage circuit 13 receives an address signal output at a predetermined timing from an address generation circuit 14 to be described later, and sends a cycle setting value corresponding to the address signal to the control signal generation circuit 11 and the address generation circuit 14. Output. The storage circuit 13 is connected to the control signal generation circuit 11 and the address generation circuit 14 through a data path 214.

  The address generation circuit 14 receives the output signal of the counter 12 and the cycle setting value output from the storage circuit 13 and outputs an address signal to the storage circuit 13 at a predetermined timing. The address signal is an address corresponding to each cycle setting value stored in the memory circuit 13, and the cycle setting value output from the memory circuit 13 is switched by switching the address signal output from the address generation circuit 14. The address generation circuit 14 is connected to the storage circuit 13 via the address path 215.

The operation of the semiconductor integrated circuit 100D having the above configuration will be described with reference to FIG.
FIG. 9 is a timing chart showing the operation of the fourth embodiment. The following description explains one process in which the semiconductor integrated circuit 100D according to the fourth embodiment is operating, and the start point of the timing chart does not indicate the operation start point of the semiconductor integrated circuit 100D. .

  In FIG. 9, CLK 202 is a clock signal input from the clock supply terminal 301, COUNTER is an output value of the counter 12, and ROM ADR 215 is a content of the address signal output from the address generation circuit 14 to the storage circuit 13. ROM DATA 214 represents a cycle setting value output from the storage circuit 13 to the control signal generation circuit 11 and the address generation circuit 14, and CLKCNT represents the content of the control signal output from the control signal generation circuit 11.

  First, the address generation circuit 14 outputs, for example, an address signal 0 to the storage circuit 13. When the cycle setting value N is stored at address 0 of the storage circuit 13, the storage circuit 13 receives the address signal 0 output from the address generation circuit 14 and sets N as the cycle setting value to the control signal generation circuit 11. And output to the address generation circuit 14.

  The control signal generation circuit 11 receives the output of the cycle setting value N from the storage circuit 13, sets N as the control signal output period, and indicates the value in CLKCNT until the count value output from the counter 12 reaches N-1. Thus, the control signal 01 is continuously output. Therefore, when the bit data 01 of the control signal is set to select the functional circuit block 102, only the functional circuit block 102 can change its internal state until the count value reaches N-1.

On the other hand, when the count value reaches N, the control signal generation circuit 11 switches the output of the control signal as described below.
That is, since the data N output from the storage circuit 13 is also output to the address generation circuit 14 at the same time, the address generation circuit 14 can generate a new address signal when the count value output from the counter 12 reaches N. For example, a new address signal 1 is output to the memory circuit 13.
When data N + M is stored at address 1 of the storage circuit 13, the storage circuit 13 receives the address signal 1 newly output by the address generation circuit 14, and sets N + M as the cycle setting value to the control signal generation circuit 11, And output to the address generation circuit 14.

  The control signal generation circuit 11 sets N + M as the control signal output period, and continues to output the control signal 10 until the count value output from the counter 12 reaches N + M-1. Therefore, if the bit data 10 of the control signal is set to select the functional circuit block 103, only the functional circuit block 103 can change its internal state until the count value reaches N + N + M-1. .

On the other hand, when the count value reaches N + M, the control signal generation circuit 11 switches the output of the control signal in the same manner as described above.
That is, since the data N + M output from the storage circuit 13 is also output to the address generation circuit 14 at the same time, when the count value output from the counter 12 reaches N + M, the address generation circuit 14 generates a new address signal. For example, a new address signal 2 is output to the storage circuit 13. Here, when the cycle setting value corresponding to the address 2 is N + M + L and the functional circuit block corresponding to the bit data 11 of the control signal is the functional circuit block 104, the count value output by the counter 12 is from N + M to N + M + L−. Until it reaches 1, only the functional circuit block 104 can change its internal state.

  When an IDDQ test is performed using the semiconductor integrated circuit 100D of the fourth embodiment as described above, an arbitrary cycle set value is stored in advance in the storage circuit 13, and the clock supply selection circuit 10 outputs a control signal. This period can be variably controlled for each functional circuit block. Therefore, for example, when supplying a clock to a functional circuit block composed of complex circuits, we want to measure the quiescent power supply current in a number of internal states. When supplying a clock to a functional circuit block with a circuit configuration, there is no need to measure the quiescent power supply current in multiple internal states, so the clock supply period can be set by setting a small value as the cycle setting value. It is possible to reduce the useless internal state change and improve the toggle rate during the IDDQ test.

  In the fourth embodiment, the case where the data stored in the storage circuit 13 is a cycle setting value that represents the period during which the control signal generation circuit 11 outputs the control signal has been described. Is also stored in the storage circuit 13 together with the signal CLKCNT indicating which functional circuit block to select, and the control signal generation circuit 11 outputs the signal together with the period setting value to supply a clock. The order of selecting circuit blocks can also be controlled.

(Embodiment 5)
FIG. 10 is a block diagram showing a configuration of a semiconductor integrated circuit 100E according to the fifth embodiment of the present invention. 10, the same components as those in FIG. 1 are denoted by the same reference numerals, and description thereof is omitted.
In FIG. 10, reference numerals 105, 106, and 107 denote scan chain blocks when the integrated circuit to be measured 101 is divided into a plurality of scan chains. The scan chain blocks 105, 106, and 107 are connected to scan-in terminals 307 to 309 via scan-in paths 216 to 218 to input scan-in data and scan-out terminals via scan-out paths 219 to 221. Connected to 310 to 312 and outputs scan-out data to the outside. Further, it is connected to the clock supply selection circuit 10 via the scan shift clock paths 222, 223, and 224, and receives an internal clock signal.

Next, an operation of the semiconductor integrated circuit 100E configured as described above and an IDDQ test procedure using the semiconductor integrated circuit 100E will be described.
First, a functional circuit block (hereinafter referred to as a scan chain block in the fifth embodiment) that changes the internal state is selected according to the procedure described in the first embodiment. For example, the scan chain block 106 is selected.

  Next, predetermined scan data is input to the selected functional circuit block 106. The scan chain block 106 receives supply of scan data and a scan shift clock, sequentially shifts the internal flip-flop circuit, and changes the internal state of the theoretical circuit constituting the scan chain block.

  When performing the IDDQ test using the semiconductor integrated circuit 100E, the current detection circuit 500 measures the quiescent power supply current at a predetermined measurement point after changing the internal state of the scan chain block as described above. Since the following procedure is the same as that of the first embodiment described above, the description thereof is omitted.

  As described above, according to the semiconductor integrated circuit 100E of the fifth embodiment, since each functional circuit block is configured as a scan chain, changes in the internal state of the functional circuit block can be easily controlled by an input scan pattern. Will be able to. Therefore, the toggle rate can be easily improved as compared with the case where the internal state is changed by the function operation, the number of times of measurement of the quiescent power supply current required to reach the target toggle rate can be reduced, and the time required for the IDDQ test Can be shortened.

(Embodiment 6)
FIG. 11 is a block diagram showing a configuration of a semiconductor integrated circuit 100F in the sixth embodiment of the present invention. In FIG. 11, the same components as those in FIG.
In FIG. 11, the scan chain block 105 includes an independent scan-in terminal 307, and the scan chain blocks 106 and 107 share the scan-in terminal 313 via the scan-in path 225.

  In the semiconductor integrated device 100F according to the sixth embodiment, a scan chain in which the scan-in terminals are provided in the semiconductor integrated device 100E according to the fifth embodiment, where the scan-in terminals are provided for each scan chain. Is included. Since the operation is the same as that of the fifth embodiment, the description thereof is omitted.

According to the semiconductor integrated circuit 100F of the sixth embodiment as described above, when a scan chain composed of a complicated combination circuit and a scan chain composed of a relatively simple combination circuit coexist, a scan composed of a complex combination circuit. While supplying independent scan data for the chain, for scan chains consisting of relatively simple combinational circuits, create scan data that combines the scan data input to each scan chain and use the aggregated scan-in terminal You will be able to enter. This makes it possible to reduce the number of scan-in terminals without increasing the length of the scan data.
In the sixth embodiment, the two scan-in terminals are collected. However, the scan-in terminals can also be gathered.

(Embodiment 7)
FIG. 12 is a block diagram showing a configuration of a semiconductor integrated circuit 100G in the seventh embodiment of the present invention. In FIG. 12, the same components as those of FIG.
In FIG. 12, the scan-out signal output from the second stage of the flip-flop circuit constituting each of the scan chain blocks 105, 106, and 107 is the first stage of each scan chain block via the loopback paths 227, 228, and 229. Is fed back as a scan-in signal of the flip-flop circuit. The scan chain blocks 105 to 107 are connected to a capture signal input terminal 314 via a scan capture path 226.

Next, the operation of the semiconductor integrated circuit 100G configured as described above will be described.
Each shift register constituting the scan chain blocks 105, 106, 107 set in a predetermined steady state in advance shifts its own signal to a flip-flop at the subsequent stage when a clock is supplied from the clock supply selection circuit 10. Alternatively, inversion shift is performed, and the output signal of the final stage flip-flop is fed back to the first stage flip-flop of each scan chain block.

  At that time, it is difficult to improve the toggle rate of the selected scan chain block only by performing the loop shift operation without any external input. Therefore, in order to change the scan chain shift data and improve the toggle rate, a capture signal is input from the capture signal input terminal 314 at a predetermined timing, and each flip-flop performs a capture operation.

According to the semiconductor integrated circuit 100G of the seventh embodiment as described above, the input data for changing the internal state is generated by the functional circuit block itself configured as a scan chain. When an IDDQ test is performed using the integrated circuit 100G, a pattern generator for creating a scan data signal is not necessary, and external input terminals and external output terminals required for scan-in and scan-out can be reduced.
Although the capture signal is input from the external terminal 314 in the seventh embodiment, the capture signal input terminal 314 is further reduced by providing a counter or the like in the semiconductor integrated circuit to generate the capture signal internally. be able to.

(Embodiment 8)
FIG. 13 is a block diagram showing a configuration of a semiconductor integrated circuit 100H according to the eighth embodiment of the present invention. In FIG. 13, the same components as those in FIG.
In FIG. 13, reference numeral 15 denotes a current detection circuit that is arranged on the power supply path 200 and detects a current flowing on the power supply path 200. A trigger signal for controlling the timing of current detection is externally input from the measurement trigger input terminal 315, and the clock signal input from the clock supply terminal 301 as an operation clock is fetched from the clock supply path 230 without passing through the clock supply selection circuit 10. .

  Reference numeral 16 denotes a comparator that compares the measurement result output from the current detection circuit 15 with the reference signal input from the reference signal input terminal 317, and outputs the comparison result to the comparison result output terminal 316.

The operation of the semiconductor integrated circuit 100H configured as described above will be described.
Upon receiving an externally input trigger signal from the measurement trigger input terminal 315, the current detection circuit 15 measures a predetermined number of cycles of the current flowing on the power supply path 200 triggered by the input of the trigger signal, and compares the measurement result with the comparator. 16 is output.
The comparator 16 compares the measurement result with the reference value input from the reference signal input terminal 317 and outputs the comparison result to the comparison result output terminal 316 externally. In the IDDQ test, the quality of the semiconductor integrated circuit 100H to be inspected is determined based on the comparison result.

  According to the semiconductor integrated circuit 100H of the eighth embodiment as described above, the generation of the inductance component caused by the connection of the power supply detection circuit can be suppressed compared with the case where the power supply detection circuit is installed outside, and the high speed can be achieved. It becomes possible to measure the quiescent power supply current.

In addition, since there is no need to connect the current detection circuit, a plurality of integrated circuits are aggregated after MCM packaging or after mounting on a board, and it is difficult to connect the current detection circuit for each integrated circuit. In addition, the IDDQ test can be performed.
In the present embodiment, the reference signal is input from the reference signal input terminal 317. However, the reference signal is stored in advance in the memory circuit, and the memory circuit is incorporated in the semiconductor integrated circuit 100H, whereby the reference signal is input. The number of signal input terminals 317 can be reduced.

  In this embodiment, the measurement trigger signal is input from the measurement trigger input terminal 315. However, the measurement trigger signal is input by providing a counter or the like in the semiconductor integrated circuit and generating the measurement trigger signal internally. The number of terminals 315 can be reduced.

(Embodiment 9)
FIG. 14 is a block diagram showing a configuration of a semiconductor integrated circuit 100I according to the ninth embodiment of the present invention. 14, the same components as those in FIG. 13 are denoted by the same reference numerals, and description thereof is omitted.
In FIG. 14, an arithmetic circuit 17 obtains a difference value between the maximum value and the minimum value of the detection result of the current detection circuit 15 and outputs the difference value to the comparator 16 as the detection result of the current detection circuit 15. The arithmetic circuit 17 includes a storage circuit for storing the maximum value and the minimum value, and a subtraction circuit for obtaining a difference value, but none of them is drawn on the drawing.

The operation of the semiconductor integrated circuit 100I configured as described above will be described.
According to the procedure described in the eighth embodiment, the current detection circuit 15 measures the quiescent power supply current for a predetermined number of cycles. The detection result is output to the detection result processing circuit 17.

For example, when the measurement value of the quiescent power supply current for seven cycles as shown in FIG. 4D is output from the current detection circuit 15, the detection result processing circuit 17 sets the quiescent power supply current value in the third cycle as the maximum value. Recognizing and storing in the storage circuit, the quiescent power supply current value in the fifth cycle is recognized as the minimum value and stored in the storage circuit 13, and the difference value between the maximum value and the minimum value is calculated and the difference result is sent to the comparator 16. Output.
The comparator 16 compares the difference value with a predetermined reference value, and outputs the comparison result to the comparison result output terminal 316.

  According to the semiconductor integrated circuit 100I of the ninth embodiment as described above, it is possible to provide an IDDQ test pass / fail criterion for the measured relative value of the quiescent power supply current. For this reason, even if the influence of the background current on the measured value of the quiescent power supply current is large, and it is difficult to provide a pass / fail judgment criterion for the IDDQ test with respect to the measured value of the quiescent power supply current itself, it is highly accurate. An IDDQ test can be performed.

(Embodiment 10)
FIG. 15 is a block diagram showing a configuration of a semiconductor integrated circuit 100J according to the tenth embodiment of the present invention. 15, the same components as those in FIG. 13 are denoted by the same reference numerals, and the description thereof is omitted.
In FIG. 15, reference numeral 18 denotes a current change amount detection circuit that is arranged on the power supply path 200 and detects the change amount of the power supply current flowing on the power supply current path 200. The current change amount detection circuit 18 outputs a measurement permission signal 231 that permits the current detection circuit 15 to measure the quiescent power supply current when the current change amount becomes a predetermined value or less. The current change amount detection circuit 18 is connected to the current detection circuit 15 via the measurement permission signal path 231.

Next, the operation of the semiconductor integrated circuit 100J configured as described above will be described with reference to FIG.
FIG. 16 is a timing chart showing the operation of the tenth embodiment. CLK230 is an external input clock, power supply current is the amount of current flowing on the power supply path 200, current change is the amount of change of the current indicated by the power supply current, and measurement permission signal 231 is the current change detection circuit 18. , The measurement trigger signal represents the input state of the measurement trigger signal input from the trigger input terminal 315, and the detection timing represents the stationary power supply current detection timing of the current detection circuit 15. .

  First, the current change amount detection circuit 18 measures the change amount of the current flowing through the power supply path 200. When the amount of change is smaller than a predetermined reference value, the measurement permission signal 231 is output to the current detection circuit 15 assuming that the internal state of the semiconductor integrated circuit 100J is in a steady state.

When the measurement permission signal 231 is input together with the measurement trigger signal input from the measurement trigger input terminal 315, the detection device 15 detects the current flowing on the power supply path 200 and outputs the detection result to the comparator 16.
The comparator 16 receives the output of the detection result, compares the reference value input from the reference signal input terminal 317 with the detection result, and outputs the comparison result to the comparison result output terminal 316 externally.

Next, the effect when the IDDQ test is performed using the semiconductor integrated circuit 100J of the present embodiment will be described below.
As shown by the power supply current in FIG. 16, the current flowing through the power supply path 200 follows the input of the external clock, and a through current due to the toggle of the transistor in the integrated circuit 101 to be measured is instantaneously generated, and then settles to a steady state. . Since the quiescent power supply current indicates the power supply current in the steady state, the timing for measuring the quiescent power supply current needs to wait sufficiently until the steady state is reached.

  However, since the time until the steady state is settled varies depending on the inspection conditions and process conditions, it is necessary to input the measurement trigger signal with a margin when measuring the quiescent power supply current. For this reason, the test pattern for improving the toggle rate and the input frequency of the external clock must be very slow, from several hundred Hz to several tens kHz, and the test time becomes very long.

  In this regard, if an IDDQ test is performed using the semiconductor integrated circuit 100J of the tenth embodiment, the current detection circuit 15 indicates that the current flowing through the power supply path 200 is in a steady state together with the measurement trigger signal. Since the measurement of the quiescent power supply current is started when the output of the measurement permission signal 231 is received, it is not necessary to input a measurement trigger signal with a time margin when measuring the quiescent power supply current as in the prior art, and the input frequency of the test pattern The test time can be greatly shortened.

(Embodiment 11)
FIG. 17 is a block diagram showing a configuration of a semiconductor integrated circuit 100K in the eleventh embodiment of the present invention. In FIG. 17, the same components as those in FIG.
In FIG. 17, reference numeral 19 denotes a temperature correction circuit that outputs a correction result to the subsequent comparator 16 after performing temperature correction on the detection result of the current detection circuit 15, and outputs a signal from the current detection circuit 15 to the comparator 16. It is installed on the route.

Next, the operation of the semiconductor integrated circuit 100K configured as described above will be described.
First, the current detection circuit 15 measures the predetermined number of cycles of the quiescent power supply current flowing through the power supply path 200 as described in the eighth embodiment.
The temperature correction circuit 19 measures the internal temperature of the semiconductor integrated circuit 100K using a temperature detection device built in the device, and measures the quiescent power supply current output from the current detection circuit 15 based on the temperature correction coefficient corresponding to the measurement temperature. A predetermined correction is performed on the result, and the correction value is output to the comparator 16. In the figure, the temperature detection device is not drawn.
The comparator 16 receives the output of the correction value, compares the predetermined reference value input from the reference signal input terminal 317 with the correction value, and outputs the comparison result to the comparison result output terminal 316 externally.

  According to the semiconductor integrated circuit 100K of the eleventh embodiment as described above, the effects described below can be obtained. That is, the measured value of the quiescent power supply current has a characteristic that it greatly varies depending on the internal temperature of the semiconductor integrated circuit when the quiescent power supply current is measured. For this reason, when performing the IDDQ test, it is not possible to perform the IDDQ test with high accuracy unless the determination reference value for determining pass / fail is provided in consideration of the temperature of the semiconductor integrated circuit and its surroundings.

In this regard, according to the semiconductor integrated circuit 100K of the eleventh embodiment, it is possible to perform an appropriate temperature correction on the measured value of the quiescent power supply current, and to perform an IDDQ test based on the correction value. The determination criterion can be determined without considering the internal temperature of the semiconductor integrated circuit during the test.
In the eleventh embodiment, a predetermined reference value is input from the reference signal input terminal 317. However, the reference value may be stored in advance in a memory circuit provided in the semiconductor integrated circuit.

  By using the semiconductor integrated circuit according to the present invention, it becomes possible to detect a failure with high accuracy and speed, so that it is possible to provide a semiconductor integrated circuit with stable operation, and as a result, various devices using the semiconductor integrated circuit can be provided. It is useful in providing market quality when it is provided.

1 is a block diagram showing a configuration of a semiconductor integrated circuit according to a first embodiment of the present invention. 3 is a timing chart showing an operation of the semiconductor integrated circuit according to the first embodiment of the present invention. It is a flowchart which shows the measuring method of the IDDQ test in Embodiment 1 of this invention. It is explanatory drawing which shows the dispersion | variation in the static power supply current in Embodiment 1 of this invention. It is explanatory drawing which shows the dispersion | variation in the static power supply current in Embodiment 1 of this invention. It is explanatory drawing which shows the dispersion | variation in the static power supply current in Embodiment 1 of this invention. It is explanatory drawing which shows the dispersion | variation in the static power supply current in Embodiment 1 of this invention. It is a block diagram which shows the structure of the semiconductor integrated circuit in Embodiment 2 of this invention. 6 is a timing chart illustrating an operation of the semiconductor integrated circuit according to the second embodiment of the present invention. It is a block diagram which shows the structure of the semiconductor integrated circuit in Embodiment 3 of this invention. It is a block diagram which shows the structure of the semiconductor integrated circuit in Embodiment 4 of this invention. 10 is a timing chart showing an operation of the semiconductor integrated circuit according to the fourth embodiment of the present invention. It is a block diagram which shows the structure of the semiconductor integrated circuit in Embodiment 5 of this invention. It is a block diagram which shows the structure of the semiconductor integrated circuit in Embodiment 6 of this invention. It is a block diagram which shows the structure of the semiconductor integrated circuit in Embodiment 7 of this invention. It is a block diagram which shows the structure of the semiconductor integrated circuit in Embodiment 8 of this invention. It is a block diagram which shows the structure of the semiconductor integrated circuit in Embodiment 9 of this invention. It is a block diagram which shows the structure of the semiconductor integrated circuit in Embodiment 10 of this invention. It is a timing chart which shows the operation | movement of the semiconductor integrated circuit in Embodiment 10 of this invention. It is a block diagram which shows the structure of the semiconductor integrated circuit in Embodiment 11 of this invention. It is a figure which shows the dispersion | variation in the static power supply current in the conventional IDDQ measuring method. It is a figure which shows the dispersion | variation in the static power supply current in the conventional IDDQ measuring method. It is a figure which shows the dispersion | variation in the static power supply current in the conventional IDDQ measuring method. It is a figure which shows the dispersion | variation in the static power supply current in the conventional IDDQ measuring method. It is a block diagram which shows the structural example of the conventional semiconductor integrated circuit.

Explanation of symbols

1, 2, 3 Power supply cut-off circuit 4 Cut-off control device 5, 6 Circuit separation device 10 Clock supply selection circuit 11 Control signal generation circuit 12 Counter 13 Storage circuit 14 Address generation circuit 15 Current detection circuit 16 Comparator 17 Detection result processing circuit 18 Current change detection circuit 19 Temperature correction circuit 100, 100A to 100K Semiconductor integrated circuit 101 Integrated circuit under test 102, 103, 104 Functional circuit block 105, 106, 107 Scan chain block 200 Power supply path 201 GND path 202 Clock supply path 203 Data input path 204, 205, 206 Control path 207, 208, 209 Block clock supply path 210, 211 Clock supply control path 212 Clock supply control path 213 Counter output path 214 Data transmission Path 215 Address signal path 216, 217, 218 Scan-in path 219, 220, 221 Scan-out path 222, 223, 224 Scan shift clock path 225 Scan-in path 226 Scan capture path 227, 228, 229 Loopback path 230 Clock supply path 300 Data input terminal 301 Clock supply terminal 302 External power supply terminal 303 GND terminal 304, 305 Clock supply control terminal 306 Clock control signal output terminal 307, 308, 309 Scan-in terminal 310, 311, 312 Scan-out terminal 313 Scan-in terminal 314 Capture Signal input terminal 315 Measurement trigger input terminal 316 Comparison result output terminal 317 Reference signal input terminal 500 Current detection circuit

Claims (16)

In a semiconductor integrated circuit composed of a plurality of functional circuit blocks that operate in synchronization with an internal clock signal,
Among the plurality of functional circuit blocks, one or more functional circuit blocks are selected based on a control signal input from an external terminal, and a clock signal input from the external terminal is internal to the selected functional circuit block. A clock supply selection circuit for outputting as a clock;
A semiconductor integrated circuit. In a semiconductor integrated circuit composed of a plurality of functional circuit blocks that operate in synchronization with an internal clock signal,
A counter that operates in synchronization with a clock signal input from an external terminal;
A control signal generation circuit that generates and outputs a control signal for controlling selection of a functional circuit block, receives an output from the counter, and switches an output content of the control signal every predetermined cycle;
In response to the output of the control signal, one or more functional circuit blocks are selected from the plurality of functional circuit blocks, and a clock signal input from an external terminal is used as an internal clock for the selected functional circuit block. A clock supply selection circuit for outputting,
A semiconductor integrated circuit. The semiconductor integrated circuit according to claim 2,
A control signal output terminal for outputting the control signal output from the control signal generation circuit to the outside;
A semiconductor integrated circuit. The semiconductor integrated circuit according to claim 2,
An address signal for instructing a cycle setting value to be output by the memory circuit is generated, an address generation circuit for outputting the address signal to the memory circuit, and one or more cycle setting values are stored as an output cycle of the control signal. A storage circuit that outputs any one of the cycle setting values to the control signal generation circuit according to the address signal;
A semiconductor integrated circuit. The semiconductor integrated circuit according to claim 1,
Each of the plurality of functional circuit blocks is an independent scan chain.
A semiconductor integrated circuit. The semiconductor integrated circuit according to claim 5,
Of the plurality of independent scan chains, two or more scan chains share a scan-in terminal.
A semiconductor integrated circuit. The semiconductor integrated circuit according to claim 5,
In each of the plurality of independent scan chains, the scan-out terminal of the final stage flip-flop constituting each scan chain is feedback-connected to the scan-in terminal of the first stage of the scan chain, and each scan chain is externally connected. The capture operation is performed in response to the input capture signal.
A semiconductor integrated circuit. The semiconductor integrated circuit according to claim 5,
In each of the plurality of independent scan chains, the scan-out terminal of the final stage flip-flop constituting each scan chain is feedback-connected to the scan-in terminal of the first stage of the scan chain. Receiving a capture signal generated by a counter provided to perform a capture operation,
A semiconductor integrated circuit. The semiconductor integrated circuit according to any one of claims 1 to 8,
A current detection circuit for measuring a quiescent power supply current flowing through a power supply path for supplying power to the plurality of functional circuit blocks;
A comparator that compares the measured value of the current detection circuit with a predetermined reference value;
A comparison result output terminal for outputting the comparison result of the comparator to the outside;
A semiconductor integrated circuit. The semiconductor integrated circuit according to claim 9, wherein
A counter that generates a trigger signal for controlling the timing at which the current detection circuit measures the quiescent power supply current, and outputs the trigger signal to the current detection circuit;
A semiconductor integrated circuit. The semiconductor integrated circuit according to claim 9, wherein
A storage circuit that stores the predetermined reference value and outputs the reference value to the comparator;
A semiconductor integrated circuit. The semiconductor integrated circuit according to claim 9, wherein
A storage circuit for storing a maximum value and a minimum value of measurement values measured by the current detection circuit;
An arithmetic circuit that calculates a difference between the maximum value and the minimum value stored in the storage circuit and outputs the difference value to the comparator as a measurement result of the current detection circuit;
A semiconductor integrated circuit. The semiconductor integrated circuit according to claim 9, wherein
The amount of change in the quiescent power supply current that flows through the power supply path is measured, and when the amount of change reaches a predetermined value or less, a measurement permission signal that permits the current detection circuit to perform current measurement, A current change amount detection circuit that outputs to the detection circuit;
A semiconductor integrated circuit. The semiconductor integrated circuit according to claim 9, wherein
Measuring the internal temperature of the semiconductor integrated circuit, correcting the measurement value of the current detection circuit based on the measurement temperature and a predetermined temperature correction coefficient, and using the correction value as the measurement result of the current detection circuit A semiconductor integrated circuit, further comprising a temperature correction circuit that outputs to the comparator. In a semiconductor integrated circuit failure detection method for detecting a failure of a semiconductor integrated circuit by measuring a quiescent power supply current of the semiconductor integrated circuit configured by a plurality of functional circuit blocks operating in synchronization with an internal clock signal,
Select one or more functional circuit blocks that supply the internal clock,
Only the selected functional circuit block by applying a predetermined data signal changes the internal state, and measures the quiescent power supply current in the predetermined internal state,
By comparing the measured value of the quiescent power supply current with a predetermined reference value, the quality of the semiconductor integrated circuit to be inspected is judged.
The function is detected until a failure of the semiconductor integrated circuit to be inspected is detected in the pass / fail judgment, or until all the predetermined functional circuit blocks are selected as the functional circuit block supplying an internal clock and the pass / fail judgment is performed. Performs operations from selection of circuit blocks to pass / fail judgment of the semiconductor integrated circuit under test.
A fault detection method for a semiconductor integrated circuit. The failure detection method for a semiconductor integrated circuit according to claim 15,
The pass / fail judgment of the semiconductor integrated circuit to be inspected stores the maximum value and the minimum value of the measured value of the quiescent power supply current,
Find the difference value between the maximum and minimum values,
The difference value is compared with a predetermined reference value.
A fault detection method for a semiconductor integrated circuit.

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