JP2008275337A - Testing device and method - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a testing device and a test method capable of measuring efficiently an input/output characteristic of a test object circuit equipped with a plurality of input terminals, synchronously with a clock. <P>SOLUTION: A clock CLK is applied to flip-flops 5a, 5b as resistor circuits into which output data from a test circuit 4 are input together with a circuit block 3, and an output signal changing synchronously with the clock CLK is inputted into a buffer circuit 6 as a test object circuit. The test circuit 4 is set in a test operation mode including a plurality of modes by switching internal multiplexers 11a, 11b corresponding to a test signal TST[a:b] used as a mode switching signal. An output value of the test circuit 4 is changed by a plurality of combinations by switching setting to each of the plurality of modes, and thereby the input/output characteristics during an AC test time of the buffer circuit 6 can be measured efficiently. <P>COPYRIGHT: (C)2009,JPO&INPIT

Description

  The present invention relates to a test apparatus and a test method for testing AC characteristics and DC characteristics of a test target circuit such as a buffer circuit.

DC (direct current) test that checks the static characteristics of LSI and other chips to be tested (inspected) by measurement in order to confirm the characteristics of various electronic circuit elements, ICs, LSIs, etc. designed and manufactured Then, an AC (alternating current) test or an AC specification test for inspecting dynamic characteristics by measurement is performed.
By measuring the static characteristic by the DC test, that is, the DC characteristic excluding the temporal change, the voltage and current characteristics of the test target circuit such as the buffer circuit can be guaranteed. In the AC test, when a change occurs at a certain input terminal, the time until the change propagates to the output terminal, specifically, a clock is input and changes transiently from the rising or falling edge of the clock. Thus, the delay time required to reach a certain value is measured.

In this case, various different conditions occur as the internal structure of the LSI becomes complicated. For this reason, conventionally, when measuring the delay time for an AC test, a test pattern that is as complex as possible is created as a measurement condition, and the measurement is performed on an actual machine.
Naturally, depending on the contents of the circuit configuration, there is a drawback that it takes time to create a test pattern for transitioning to or setting the transition state immediately before the measurement target state to be actually measured.
In addition, when there are a plurality of measurement target states, it is difficult to efficiently set the measurement target states for each of the plurality of measurement target states, so that it takes time to perform the measurement.
In recent years, an improvement in operation speed has been desired, and a clock synchronization design has become the mainstream circuit configuration.
If the clock is synchronized, the test can be facilitated, and if the scan shift when the one-phase scanning is inserted is used, the clock synchronization changes, so that it can be used as a test circuit.

However, in creating a test pattern, it is necessary to understand the configuration of the data shift path and the time until the transition to the measurement target state depends on the number of scan shift stages.
Also, as the circuit configuration, the conditions of the output change path are not the same as the actual operation due to the restrictions of the scanning rule, and when the pattern generation circuit is incorporated, the scan shift data cannot be manipulated by the test pattern It ’s not a good idea.
On the other hand, Patent Document 1 discloses a scan test circuit that makes it easy to identify a failure location in an LSI or the like. In this scan test circuit, the logic circuit in the combinational logic circuit block is a logic circuit with a select function, and the select terminal and at least one input terminal can be controlled from outside the scan test circuit.

However, in Patent Document 1, since the signal to be selected is a 1-bit signal, when the combinational logic circuit block has a plurality of output terminals, the output levels of the plurality of output terminals cannot be controlled by a plurality of combinations.
Thus, if the output levels of a plurality of output terminals cannot be controlled by a plurality of combinations, for example, a test target circuit such as a buffer circuit having a plurality of input terminals in the subsequent stage is connected and an attempt is made to measure its characteristics. It cannot be set to a plurality of measurement target states.
JP 2006-242781 A

  The present invention has been made in view of the above-described points, and is capable of efficiently measuring input / output characteristics of a test target circuit having a plurality of input terminals such as a buffer circuit in synchronization with a clock. An object is to provide an apparatus and a test method.

  A test apparatus according to an embodiment of the present invention includes a first operation mode corresponding to a normal operation mode in which digital signals input to a plurality of input terminals are output from a plurality of output terminals, and the plurality of output terminals. A test circuit including an external input terminal to which a mode switching signal for switching between a second operation mode corresponding to a test operation mode in which a plurality of output levels can be controlled by a plurality of combinations, and an output from the plurality of output terminals Each of the output data is input to a plurality of input terminals, and each output data corresponding to each data is output from a plurality of output terminals in synchronization with a clock, and a plurality of each output data of the register circuit And a test target circuit for outputting a corresponding output signal from an output terminal as an input signal.

  A test method according to an embodiment of the present invention includes a register circuit in which a plurality of digital signals input to a plurality of input terminals of a test circuit change in output from a plurality of output terminals in synchronization with a clock. A switching step of switching from a first operation mode corresponding to a normal operation mode input to a plurality of input terminals to a second operation mode corresponding to a test operation mode, and a second operation switched by the switching step In the mode, in the mode switching step for temporally switching the output levels of the plurality of output terminals of the test circuit with at least a plurality of combinations, and in each mode switching step, the test is performed through the register circuit to which a clock is applied. Measurement to measure the signal level of the output terminal that changes in synchronization with the clock in the target circuit Characterized in that it comprises a step, a.

  According to the present invention, it is possible to efficiently measure input / output characteristics of a test target circuit having a plurality of input terminals in synchronization with a clock.

Hereinafter, embodiments of the present invention will be described with reference to the drawings.
Before describing an embodiment of the present invention, a test apparatus of a reference example related to this embodiment will be described first. FIG. 8 shows a test apparatus 51 of a reference example.
The test apparatus 51 is incorporated in an LSI circuit 52 having a predetermined function. That is, the LSI circuit 52 includes a circuit block 3 made of random logic or the like having a plurality of input / output terminals, and a test device 51 to which a digital output signal of the circuit block 3 is input.
The test apparatus 51 includes two D-type flip-flops 5a and 5b as register circuits connected to a plurality of (specifically two) output terminals of the circuit block 3, and two flip-flops 5a and 5b. A test circuit 54 that receives output data and a buffer circuit 6 that is a test target circuit that outputs two output data of the test circuit 54 as input data.

A clock CLK and a reset signal RST are applied to the circuit block 3 and the flip-flops 5a and 5b from the clock terminal 7 and the reset terminal 8, respectively.
The circuit block 3 and the flip-flops 5a and 5b are reset, for example, when the reset signal RST is set to the L level.
Further, the terminals such as the clock terminal 7 in FIG. 8 (the same applies to FIG. 1 and the like to be described later) are also indicated by the clock CLK or the like to which a signal is applied.
The output data output from the two output terminals of the circuit block 3 is input as input data to the data input terminals D of the flip-flops 5a and 5b, respectively.
The flip-flops 5a and 5b output input data input from the output terminal Q to the data input terminal D in synchronization with the clock CLK applied to the clock input terminal CK.

The output data of the output terminals Q of the flip-flops 5a and 5b are input to, for example, input terminals I_EN and I_OUT of the test circuit 54, respectively.
The test circuit 54 includes two output terminals O_EN and O_OUT corresponding to the input terminals I_EN and I_OUT. These output terminals O_EN and O_OUT are the input terminal A of the buffer circuit 6 and the (3-state) control signal input terminal EN. Connected to.
The output terminal Z of the buffer circuit 6 is connected to the output terminal 59 of the test apparatus 51 (or LSI circuit 52). An output signal OUT of the LSI circuit 52 is output from the output terminal 59.
The test circuit 54 incorporates a switching circuit (not shown) that switches input / output characteristics between two input / output terminals in the test circuit 54 from the outside.

This switching circuit can be switched from the external input terminal 10 connected to the test input terminals TSTa and TSTb provided in the test circuit 54 by a test signal TST [a: b] as an operation mode switching signal.
Note that the test signal TST [a: b] indicates that the test signal TST is formed of 2-bit signals a and b. For example, when a = 0 and b = 0, that is, when [a: b] is [0: 0], the first operation mode is set. In other cases, the second operation mode (consisting of a plurality of modes) is set.
For this reason, the test signal TST [a: b] has a function of a mode switching signal for switching between the first and second operation modes and a function of an in-mode switching signal for switching a plurality of modes in the second operation mode.

In the first operation mode, the test circuit 54 directly passes the signals input to the two input terminals I_EN and I_OUT and outputs the signals from the two output terminals O_EN and O_OUT.
On the other hand, in cases other than the above (a = 0 and b = 0), switching to the second operation mode is set. In the second operation mode, the output levels of the two output terminals O_EN and O_OUT can be controlled by a plurality of combinations at least at a binary level.
Here, as a test target circuit, a three-state buffer circuit having one input terminal A and one output terminal Z, and a control signal input terminal EN that validates / invalidates a signal input to the input terminal A 6 is adopted. That is, the buffer circuit 6 includes a plurality of input terminals A and EN.

The buffer circuit 6 enables the signal applied to the control signal input terminal EN at the L level, but when the signal is at the H level, the output terminal Z has a high impedance (regardless of the signal to the input terminal A). It becomes a state.
Therefore, the test circuit 54 in this reference example is set to operate in an operation mode such as the truth table shown in FIG. In FIG. 9 (the same applies to FIG. 2 described later), the 2-bit signal [a: b] in the test signal TST [a: b] is 0 for [0: 0], 1 for [0: 1], [ 1: 0] is represented as 2, and [1: 1] is represented as 3, that is, a notation of quaternary or higher.
Only when the 2-bit signal [a: b] in the test signal TST [a: b] is 0, the LSI circuit 52 directly uses the two signals input to the test circuit 54 as two output terminals O_EN, The first operation mode corresponding to the normal system operation mode output from O_OUT is set.

On the other hand, in the case of a plurality of remaining values, that is, when the 2-bit values in the test signal TST [a: b] are 1, 2, and 3, the LSI circuit 52 has two output terminals O_EN and O_OUT. Are set to L, L, L, H, H, and X, and the second operation mode corresponding to the test mode for testing the input / output characteristics of the buffer circuit 6 to be tested is set.
Note that the test signal TST [a: b] for switching to different modes in the second operation mode is also referred to as an in-mode switching signal, including the case of the embodiments described later.
The output levels H and X are independent of the signal level (from the output terminal O_OUT) applied to the input terminal A of the buffer circuit 6 by applying an H level signal to the control signal input terminal EN. The buffer circuit 6 is set to a high impedance state.
When the LSI circuit 52 of FIG. 8 is operated in the system operation mode, for example, a timing diagram is obtained as shown in FIG.

As shown in this timing diagram, the test signal TST [a: b] is always set to a value 0 corresponding to the first operation mode, and the reset signal RST is set to the H level, so that the circuit block 3 and the flip-flop 5a, 5b is set to the operating state.
Then, the circuit block 3 constituting the LSI circuit 52 operates in synchronization with the clock CLK, and the output signal of the circuit block 3 passes through flip-flops 5a and 5b as register circuits that operate in synchronization with the clock CLK. Input to the test circuit 54. The input signal to the test circuit 54 is substantially passed through the test circuit 54 and input to the buffer circuit 6, and the output signal OUT is output from the output terminal 59.
Therefore, the output signal OUT changes depending on the internal circuit of the circuit block 3, for example, as shown in this timing diagram. In FIG. 10, for example, the output signal OUT in which the output signal OUT is set from the H level to the high impedance state is indicated by Hiz.

On the other hand, when the LSI circuit 52 is operated in a test mode for performing a DC test, for example, a timing diagram as shown in FIG. 11 is obtained. In this case, the input / output relationship of the LSI circuit 52 is as shown in the table of FIG.
As shown in FIG. 11, as the 2-bit signals a and b of the test signal TST [a: b] are sequentially switched from 0 to 1, 1 to 2, and 2 to 3 from the state of the system operation mode, the output signal OUT is It changes to L level, H level, and high impedance (Hiz) level. In these changes and each state, the DC characteristics of the buffer circuit 6 can be tested. In FIG. 10, the output signal OUT changes in synchronization with the clock CLK. However, in the case of FIG. 11, the output signal OUT changes without being synchronized with the clock CLK. This relationship can also be seen from the table of FIG. In FIG. 12, − indicates that it does not depend on the clock CLK.

Therefore, in the configuration of the reference example of FIG. 8, in order to measure the dynamic characteristics of the buffer circuit 6, the output signal OUT is L in synchronization with the clock CLK in the system operation mode as shown in FIG. The delay time ta rising from the level to the H level, the delay time tb falling from the H level to the high impedance level, and the delay time tc falling from the high impedance level to the L level are measured.
As described above, in the case of the circuit configuration of the reference example of FIG. 8, when the LSI circuit 52 is configured and a DC test and an AC test of the buffer circuit 6 as a test target circuit are to be performed, In this operating state, the delay time of AC test cannot be measured.
It would be convenient to improve this point and to measure the delay time required as the dynamic characteristic of the AC test even in the test operation mode state of the DC test. An embodiment according to the present invention in which this point is improved will be described below.
FIG. 1 shows a configuration of a test apparatus 1 according to an embodiment. The test apparatus 1 has a configuration similar to the test apparatus 51 of FIG.

The test apparatus 1 is incorporated in the LSI circuit 2. The LSI circuit 2 includes a circuit block 3 having a plurality of input / output terminals such as random logic, and a test apparatus 1 to which a digital output signal of the circuit block 3 is input.
The test apparatus 1 includes a test circuit 4 connected to a plurality (specifically, two) of output terminals of the circuit block 3, and a register circuit that uses two output data of the test circuit 4 as two input data. Two D-type flip-flops 5a and 5b, and a buffer circuit 6 serving as a test target circuit that outputs output signals corresponding to the two input signals by using two output data of the flip-flops 5a and 5b as two input signals; Consists of.
A clock CLK and a reset signal RST are applied to the circuit block 3 and the flip-flops 5a and 5b from the clock terminal 7 and the reset terminal 8, respectively.

The circuit block 3 and the flip-flops 5a and 5b are reset when the reset signal RST is set to the L level.
The output data output from the two output terminals of the circuit block 3 is input to the two input terminals I_EN and I_OUT of the test circuit 4, respectively.
The test circuit 4 includes two output terminals O_EN and O_OUT corresponding to the input terminals I_EN and I_OUT, and these output terminals O_EN and O_OUT are connected to the data input terminals D of the flip-flops 5a and 5b, respectively.
The flip-flops 5a and 5b output input data from the output terminal Q to the data input terminal D, respectively, in synchronization with the clock CLK applied to the clock input terminal CK.

The output data of each output terminal Q of the flip-flops 5a and 5b is connected to the control signal input terminal EN and the input terminal A of the three-state buffer circuit 6. When the signal to the control signal input terminal EN is at L level, the buffer circuit 6 amplifies the signal to the input terminal A, for example, and outputs it from the output terminal Z.
The output terminal Z of the buffer circuit 6 is connected to the output terminal 9 of the test apparatus 1 (or LSI circuit 2). The output signal OUT of the LSI circuit 2 is output from the output terminal 9.
Further, the test circuit 4 according to the present embodiment incorporates multiplexers 11a and 11b, for example, as a switching circuit that switches input / output characteristics between two input / output terminals in the test circuit 4 from the outside.
The two multiplexers 11a and 11b can be changed by a test signal TST [a: b] as an operation mode switching signal from an external input terminal 10 connected to the test input terminals TSTa and TSTb provided in the test circuit 4. Yes. As described above, the test signal TST [a: b] indicates that the test signal TST is formed of the 2-bit signals a and b.

In response to the test signal TST [a: b], the multiplexer 11a changes the common terminal connected to the output terminal O_EN into three selection terminals, that is, a terminal connected to the input terminal I_EN, a terminal corresponding to the H level, and L Select and connect one of the terminals corresponding to the level.
Similarly, the multiplexer 11b uses a test signal TST [a: b] to connect a common terminal connected to the output terminal I_OUT to three selection terminals, that is, a terminal connected to the input terminal O_OUT, and a terminal corresponding to the H level. , One of the terminals corresponding to the L level is selected and connected.
For example, when the 2-bit signals a and b of the test signal TST [a: b] are a = 0 and b = 0, that is, [a: b] is [0: 0], the first operation mode is set. Is done. In the first operation mode, signals input to the two input terminals I_EN and I_OUT of the test circuit 4 are directly (or substantially) passed through and output from the two output terminals O_EN and O_OUT (this selected state). Is shown in FIG.

On the other hand, in cases other than the above (a = 0 and b = 0), switching to the second operation mode is set. In the second operation mode, the output levels of the two output terminals O_EN and O_OUT are at least a binary level and can be controlled in a plurality of combinations.
Here, as a circuit to be tested, 3 provided with one input terminal A and one output terminal Z as described above, and with a control signal input terminal EN that validates / invalidates a signal input to the input terminal A. A state buffer circuit 6 is employed. That is, the buffer circuit 6 includes a plurality of input terminals A and EN.
In this embodiment, the input signal is input to the buffer circuit 6 through the flip-flops 5a and 5b in which the output signal of the output terminal Q changes in synchronization with the clock CLK. The input / output characteristics of the buffer circuit 6 can be measured in synchronization with the clock CLK, and the measurement results can be obtained efficiently.

Although D-type flip-flops 5a and 5b whose output changes in synchronization with the rising edge of the clock CLK are employed here, the output may be changed in synchronization with the falling edge.
The test circuit 4 in the present embodiment is set to operate in an operation mode such as a truth table shown in FIG. The truth table shown in FIG. 2 is the same as FIG. In FIG. 2, the 2-bit signals a and b in the test signal TST [a: b] are represented by 0 and 0 as 0 and 0 and 1 as 1 as in the case of 2 bits. That is, the same notation as in FIG. 8 is used.
Only when the 2-bit signals a and b of the test signal TST [a: b] have a single value 0, 0 (= 0), the LSI circuit 2 receives the two signals input to the test circuit 4. Is output from the two output terminals O_EN and O_OUT as it is to the first operation mode corresponding to the normal system operation mode.

On the other hand, in the case of the remaining plural values, that is, 1, 2, and 3, the LSI circuit 2 sets the output levels of the two output terminals O_EN and O_OUT to L, L; L, H; H, When set to X, the second operation mode corresponding to the test operation mode in which the required input / output characteristics are normally tested for the buffer circuit 6 to be tested is set.
The operation timing chart in the system operation mode in this embodiment is as shown in FIG. This operation timing has the same waveform as that in FIG. 10 in the reference example. FIG. 3 shows a part of the operation timing chart in the system operation mode.
On the other hand, the operation timing chart in the test operation mode in this embodiment is as shown in FIG. Further, the input / output relationship of the LSI circuit 2 in this test operation mode is as shown in FIG. As can be seen from FIGS. 4 and 5, the input / output relationship of the LSI circuit 2 in this test operation mode changes in synchronization with the clock CLK.

This feature can be better understood with reference to FIG. In the LSI circuit 2 shown in FIG. 1, the clock CLK is also applied to the flip-flops 5a and 5b provided on the output side (rear stage side) of the test circuit 4 together with the circuit block 3, and the outputs of the flip-flops 5a and 5b. A buffer circuit 6 having a signal as an input signal is provided.
Therefore, in FIG. 1, for example, in the system operation mode, the test circuit 4 configuring the LSI circuit 2 simply passes through the output signal of the circuit block 3 and outputs it to the flip-flops 5a and 5b.
When the system operation mode is switched to the test operation mode, the input signal for the flip-flops 5a and 5b is changed from the output signal of the circuit block 3 to the output signal from the test circuit 4 (set by the mode switching signal). It becomes a change that can be switched.

In other words, the buffer circuit 6 to be tested and the flip-flops 5a and 5b that input the output signal that changes in synchronization with the clock CLK to the buffer circuit 6 are switched from the system operation mode to the test operation mode. In this case, a common signal path is secured.
Therefore, if the signal at the output terminal Q of the flip-flops 5a and 5b has a characteristic (characteristic) that changes in synchronization with the clock CLK, the LSI circuit 2 even if the operation mode of the test circuit 4 is switched by the mode switching signal. Alternatively, the input / output unit of the buffer circuit 6 maintains its characteristics (features).
In the state of switching to the test operation mode, the output signal of the test circuit 4 is switched in a plurality of combinations by the in-mode switching signal, whereby the input / output of the buffer circuit 6 using the output signals of the flip-flops 5a and 5b as input signals. The characteristics can be tested easily or efficiently.

In the LSI circuit 52 of the reference example, the input / output has a characteristic that changes in synchronization with the clock CLK in the system operation mode. However, when the LSI circuit 52 is switched to the test operation mode, the input / output is synchronized with the clock CLK. Does not have the characteristics to change.
On the other hand, as described above, in the present embodiment, the input / output of the LSI circuit 2 has a characteristic that changes in synchronization with the clock CLK in both the system operation mode and the test operation mode.
That is, the LSI circuit 2 in which the test apparatus 1 according to this embodiment is incorporated changes in synchronization with the clock CLK in the system operation mode even when the operation state in the system operation mode is switched to the test operation mode. The characteristics to be maintained are maintained (maintained) as they are.

For this reason, in the LSI circuit 2 in which the test apparatus 1 according to this embodiment is incorporated, when testing the input / output characteristics of the buffer circuit 6 serving as a test target circuit, for example, both the DC test and the AC test are performed in the test operation mode. Can also be performed. Of course, an AC test can be performed in the system operation mode shown in FIG.
In the case of the DC operation mode of FIG. 4, for example, the clock CLK is, for example, L at the timing near the center in each period when the 2-bit signals a and b of the test signal TST [a: b] as the in-mode switching signal are switched. It is set to change from level to H level. Further, for example, by switching between 2-bit signals a and b as shown in FIG. 4, the delay times ta to tf required as AC characteristics can be measured, and the measured values can be easily obtained (or efficiently). To be able to.

That is, in the reference example, in order to perform the AC test, it is necessary to perform in the system operation mode. In this case, it is not possible to freely set the transition state to be measured, and it takes time. End up.
On the other hand, in the present embodiment, in the second operation mode corresponding to the test operation mode, the change in the input / output state of the buffer circuit 6 is synchronized with the clock CLK similarly to the state of the system operation mode. It can be controlled by changing the value of TST [a: b]. For this reason, in this embodiment, it can set to the state immediately before the measuring object state to be measured, and can perform a measurement efficiently.
Specifically, as shown in FIG. 4, the delay time ta of rising from the L level to the H level, the delay time tb of falling from the H level to the high impedance level, and the transition from the high impedance level to the L level. The falling delay time tc can be measured efficiently.

In addition, the delay time Td from the L level to the high impedance level, the delay time te from the high impedance level to H, and the delay time tf from the H level to the L level can be measured. And the measurement results of the delay times ta to tf desired to be measured can be obtained efficiently.
FIG. 6 shows a processing procedure of a test method for testing an AC characteristic (dynamic characteristic) and a DC characteristic (static characteristic) for the buffer circuit 6 as a test target circuit by the test apparatus 1 according to the present embodiment.
In this case, a measurement device (not shown) is connected to the LSI circuit 2 in FIG. This measuring apparatus includes, for example, a signal generator that generates a signal such as a clock CLK under the control of a CPU as control means, and a waveform measuring apparatus that observes or measures a waveform. A signal generator is connected to the input terminal of the LSI circuit 2, and a digital oscilloscope or the like as a waveform measuring device is connected to the output terminal 9 of the LSI circuit 2.

Then, the LSI circuit 2 and the measuring apparatus are turned on. For example, as shown in FIG. 4, the operation is initially performed in the first operation mode.
When the test is started, as shown in step S1 of FIG. 6, the CPU switches from the signal generator to the second operation mode by the test signal TST as the operation mode switching signal.
Further, at the time of this switching, the CPU causes the generation of the clock CLK to interlock with the intra-mode switching signal in the second operation mode. Specifically, after switching to the in-mode switching signal as shown in FIG. 4, the CPU controls to generate one clock CLK after a certain time, for example. Then, as shown in step S2, the in-mode switching signal is switched at a predetermined time interval, for example, to switch to a plurality of mode states in the second operation mode.

In the case of FIG. 4, the in-mode switching signal is sequentially switched as 1, 2, 3, 1, 3, 2, 1,. As shown in step S3, one clock CLK is generated in each mode.
Then, as shown in step S4, the CPU controls the waveform measurement operation of the waveform measurement device, measures the signal level of the output terminal 59 of the buffer circuit 6 from the timing of the rising edge of the clock CLK, and outputs the result as the measurement result. .
In this case, the delay time can be calculated and the dynamic characteristics can be measured by calculating the response time until the signal level of the output terminal 59 reaches a certain value from the timing of the rising edge of the clock CLK from the measurement result.
Further, as shown in step S5, the static characteristic can be measured from the value of the constant value after the signal level reaches the constant value.

When measuring the dynamic characteristics, for example, as shown in FIG. 4, when switching the intra-mode switching signal at a relatively short period and measuring the static characteristics, when measuring the dynamic characteristics The in-mode switching signal may be switched at a longer cycle. Then, the required static characteristics may be measured with a long period.
As described above, according to the present embodiment, the input / output characteristics of the buffer circuit 6 serving as the test target circuit can be efficiently measured in synchronism with the clock CLK, in other words, can be measured easily and in a short time.
In the configuration example of FIG. 1, the case where there is one three-state buffer circuit 6 as the circuit to be measured has been described. Therefore, for this buffer circuit 6, a 2-bit signal is used as the test signal TST [a: b]. [A: b] was sufficient.

The present embodiment may be configured such that in the case of two input / output terminals, the two input / output terminals can be independently controlled. For example, in FIG. 2, when the test signal TST [a: b] is 3, H and X are set as H and X in the case of 3, as shown in FIG. A configuration that can be controlled independently is also possible. In this case, the test signal TST [a: b: c] has a bit number larger than 2 bits.
Further, a test signal of 3 bits or more may be used so that the characteristics of a plurality of buffer circuits can be tested. When a plurality of buffer circuits are used, the number of input / output terminals of the test circuit 4 may be three or more. In the case of three or more, each input / output terminal may be controlled independently. For example, when the digital signal output from the circuit block 3 is a plurality of bits, the number of input / output terminals of the test circuit 4 may be increased so that the number of input / output terminals corresponding to the plurality of bits is reached.

1 is a circuit diagram of an LSI circuit equipped with a test apparatus according to an embodiment of the present invention. The figure which shows the truth table of the test circuit which comprises a test apparatus. The timing diagram in the 1st operation mode in the test device concerning one embodiment. The timing diagram in the 2nd operation mode in the test equipment concerning one embodiment. Explanatory drawing of the input / output relationship at the time of a 2nd operation mode. The flowchart which shows the process sequence of the test method which concerns on one Embodiment. The figure which shows the truth table of the test circuit in a modification. A circuit diagram of an LSI circuit on which a test apparatus of a reference example is mounted. The figure which shows the truth table of the test circuit in a reference example. The timing diagram in the 1st operation mode in the test apparatus of a reference example. The timing diagram in the 2nd operation mode in the test apparatus of a reference example. Explanatory drawing of the input-output relationship at the time of the 2nd operation mode in a reference example.

Explanation of symbols

DESCRIPTION OF SYMBOLS 1 ... Test apparatus 4 ... Test circuit 5a, 5b ... Flip-flop 6 ... Buffer circuit 7 ... Clock input terminal 9 ... Output terminal 10 ... External input terminal 11a, 11b ... Multiplexer

Claims (5)

A first operation mode corresponding to a normal operation mode in which digital signals input to a plurality of input terminals are output from a plurality of output terminals, and a plurality of output levels of the plurality of output terminals can be controlled by a plurality of combinations. A test circuit including an external input terminal to which a mode switching signal for switching between the second operation mode corresponding to the test operation mode is applied;
Each of the data output from the plurality of output terminals is input to a plurality of input terminals, and a register circuit that outputs each output data corresponding to each of the data from the plurality of output terminals in synchronization with a clock;
A test target circuit that outputs a plurality of output data of the register circuit as a plurality of input signals and outputs a corresponding output signal from an output terminal;
A test apparatus comprising:   The test apparatus according to claim 1, wherein the test target circuit is a buffer circuit having a plurality of input terminals.   The test circuit includes the first operation mode in which the plurality of input / output terminals are substantially passed through and output by a mode switching signal corresponding to one value applied to the external input terminal, and the external circuit The second that enables the output level at the plurality of output terminals to be controlled by a plurality of combinations of H level and L level by a mode switching signal corresponding to a plurality of values different from the one value applied to the input terminal. The test apparatus according to claim 1, further comprising: Normal operation mode in which multiple digital signals input to multiple input terminals of the test circuit are input to multiple input terminals of the circuit under test via a register circuit whose output changes in synchronization with the clock from multiple output terminals A switching step of switching from the first operation mode corresponding to the second operation mode corresponding to the test operation mode;
In the second operation mode switched by the switching step, in-mode switching step of temporally switching the output levels of the plurality of output terminals of the test circuit with at least a plurality of combinations;
In each mode switching step, a measurement step of measuring a signal level of an output terminal that changes in synchronization with the clock in the circuit under test via the register circuit to which a clock is applied;
A test method comprising:   The measurement step includes a dynamic characteristic that measures a delay time until the signal level of the output terminal that changes in synchronization with the rising or falling edge of the clock reaches a constant value, and a static characteristic after reaching the constant value. The test method according to claim 4, wherein the characteristic can be measured.

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