JP2005003628A - Lsi test circuit and testing method thereof - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide an LSI test circuit and a testing method thereof which can be measured by a single test pattern when a temperature and a power supply voltage change, and an output is delayed more than several cycles. <P>SOLUTION: An input delay circuit 4 is provided between an LSI tester device 1 and an LSI device 3. The input delay circuit 4 inputs a reference clock signal 101 generated from the LSI tester device 1 into the LSI device 3, inputs an output clock signal 104 outputted from the LSI device 3 and a reference output signal 105 having the same cycle as that of the output clock signal 104, and adds delay to an input signal 102 of the test pattern inputted into the LSI device 3 from the LSI tester device 1 according to the amount of delay of the output clock signal 104 and reference output signal 105. <P>COPYRIGHT: (C)2005,JPO&NCIPI

Description

[0001]
BACKGROUND OF THE INVENTION
The present invention relates to an LSI test circuit used during an LSI test for inspecting whether the operation of an LSI device has been normally performed and a test method therefor.
[0002]
[Prior art]
An LSI test is generally performed at the final stage of manufacturing in order to find out the existence and cause of a failure that occurs during manufacturing or use of an LSI.
[0003]
The LSI test basically includes a DC test for measuring static characteristics of the LSI and a function test for measuring dynamic functions by inputting a test pattern from the LSI tester device. In the function test, an LSI device is used from the LSI tester device. The reference clock signal necessary to operate the LSI is input, and the test pattern input signal is input from the LSI tester device to the LSI device for each reference clock signal, so that the LSI device operates and an output signal is output. .
[0004]
This output signal is taken into the LSI tester device and compared with the expected output value described in the test pattern at the strobe timing set for each reference clock signal, and the non-defective and defective products of the LSI device can be inspected. Done.
[0005]
In the LSI test, since the function test is performed to determine the failure of the LSI, generally, the actual operation test pattern of the LSI to be inspected is not input, but a test pattern automatic creation tool for failure detection is used. Inspection is performed with the created failure detection test pattern to determine whether the LSI device is good or defective.
[0006]
In the LSI test, this function test is generally performed in three states: a high power supply voltage condition, a normal power supply voltage condition, and a low power supply voltage condition.
[0007]
Under each power supply voltage condition, the amount of delay changes in each part inside the LSI device, so it is necessary to create a test pattern with a sufficient margin so that it can operate without any problem under each condition. Since there is no problem even if the inspection is executed at a sufficiently low speed, conventionally, it was not necessary to create a test pattern in consideration of a sufficient margin.
[0008]
Further, there is a method (for example, Patent Document 1) for obtaining the delay amount in the LSI, outputting the optimum strobe timing, and measuring it. In that case, an extra pin used only for the LSI test is provided in the LSI device as an output terminal. Every connection needed to be connected.
[0009]
Therefore, in view of the above-described problems, the present invention provides a case where the delay time in the LSI device varies due to a change in power supply voltage, a change in temperature conditions, a change in process parameters, etc., and the output clock signal serving as a reference of the output signal is delayed. Another object of the present invention is to provide an LSI test circuit that enables measurement using the same test pattern.
[0010]
[Patent Document 1]
Japanese Patent Laid-Open No. 2001-264390
[Problems to be solved by the invention]
However, in recent years, with the increase in speed and integration of LSI devices, it has become difficult to perform sufficient failure detection using only this failure detection test pattern.
[0012]
For this reason, failure detection accuracy is improved by creating a test pattern that implements the actual operation function of the LSI device and adding and executing it during the function test.
[0013]
When confirming actual operation functions, it is often impossible to perform sufficient fault detection by performing measurement at a low speed, so a high-speed reference clock signal close to actual operation is input from the LSI tester device. By doing so, the measurement of the actual operation function was carried out.
[0014]
However, there are cases where the internal delay of the LSI device becomes one cycle or more of the reference clock signal due to fluctuations in power supply voltage conditions, temperature conditions, and process parameters, and the output value is one cycle from the original expected value output. The value is delayed as described above.
[0015]
In this case, a shift of one cycle or more occurs between the expected value of the test pattern at the position where the strobe is set in the reference clock signal and the actual output waveform. The problem of being judged as a defective product arises.
[0016]
Therefore, by preparing a test pattern that takes into account the delay of the signal in the LSI device due to each power supply voltage and temperature condition, the output signal due to the delay in the LSI device and the expectation of the test pattern for each power supply voltage and temperature condition are prepared. There is a method of performing measurement so that the values match. However, if there is a deviation in the delay value inside the LSI device due to a deviation in process parameters, the actual output signal of the LSI device and the created test pattern It may be different from the expected value and may be judged as defective. For this reason, there are cases where measurement cannot be performed by the method of preparing a test pattern for each power supply voltage and temperature condition.
[0017]
Furthermore, in the method of preparing and measuring test patterns for each condition, the number of test patterns increases compared to the conventional method, so the test time increases with the increase in test pattern reading time, and the test pattern amount increases. In some cases, a high-speed and high-performance LSI tester device is required, which causes an increase in test cost.
[0018]
By the way, in the LSI device, various clocks are generated from the reference clock signal input by the LSI tester device by dividing the clock inside the LSI device, the internal circuit is operated by the various clocks, and the signal is output.
[0019]
Since the signal is output based on various clocks with delay in the circuit generated inside the LSI device, the various clocks internally generated on the LSI test program and the input reference clock signal There is a method of measuring the delay amount and changing the timing of expected value comparison in the LSI tester apparatus according to the delay amount.
[0020]
In this case, however, a two-dimensional characteristic plot (referred to as SHMOO) of power supply voltage and frequency required at the time of evaluation in order to obtain the delay amount of the clock first, calculate the timing of the expected value, and then execute the function test. It will be difficult to get.
[0021]
In addition, since it becomes necessary to calculate the delay amount for each measurement and perform the calculation, the test time increases.
[0022]
In addition, there is a method of obtaining the delay amount inside the LSI, outputting the optimum strobe timing, and measuring it. In that case, it is necessary to connect an extra pin used only for the LSI test inside the LSI device for each output terminal. there were.
[0023]
Therefore, in view of the above-described problems, the present invention provides a case where the delay time in the LSI device varies due to a change in power supply voltage, a change in temperature conditions, a change in process parameters, etc., and the output clock signal serving as a reference of the output signal is delayed. Another object of the present invention is to provide an LSI test circuit that enables measurement using the same test pattern.
[0024]
[Means for Solving the Problems]
An LSI test circuit according to the present invention inputs a reference clock signal generated from an LSI tester device that generates a test pattern input signal to an LSI device, and outputs an output clock signal output from the LSI device in the same cycle as the output clock signal. The reference output signal output from the LSI tester device is input, the delay amount between the output clock signal and the reference output signal is measured, and the test pattern input signal input from the LSI tester device to the LSI device is delayed according to the delay amount. Is provided between the LSI tester device and the LSI device.
[0025]
According to this configuration, even when the delay amount of the signal inside the LSI device changes due to fluctuations in the power supply voltage, temperature conditions, and process parameters, the input delay circuit causes each delay amount of the signal inside the LSI device to vary. Since the input timing of the test pattern input signal under conditions can be changed to an optimal position, measurement under all conditions can be performed without changing the test pattern.
[0026]
Since one test pattern can cope with all conditions, the amount of tester memory used in the LSI tester apparatus can be reduced, and the number of times of test pattern reading (test time) can be reduced.
[0027]
A two-dimensional characteristic plot (SHMOO) of power supply voltage and frequency, which was conventionally obtained for each condition at the time of LSI device evaluation, can also be obtained with one test pattern.
[0028]
Focusing on the point that this function is used only during the LSI test, the test circuit is provided outside the LSI device, so there is no need to add an extra circuit inside the LSI device.
[0029]
The LSI test circuit of the present invention includes an input delay circuit in the LSI tester device.
[0030]
With this configuration, it is not necessary to provide an input delay circuit on the LSI test board, and a conventional LSI test board can be used.
[0031]
In the LSI test circuit of the present invention, the input delay circuit selects a phase detector that detects a phase difference between the output clock signal and the reference output signal, a plurality of delay elements that delay the test pattern input signal, and a delay amount. Circuit.
[0032]
With this configuration, the delay amount between the output clock signal and the reference output signal can be detected with high accuracy, and an optimum delay amount can be added for each test pattern input signal. In addition, there is an advantage that an input delay circuit can be configured using general-purpose electronic components such as a PLL, and an LSI test board can be easily manufactured.
[0033]
In the LSI test circuit of the present invention, the input delay circuit includes a phase detector that detects a phase difference between the output clock signal and the reference output signal, a selection circuit that selects a delay element, a delay amount of the delay element, and an output of the selection circuit. And a flip-flop that holds the input value until the signal changes.
[0034]
According to this configuration, the same delay amount may be added to a test pattern input signal input to an LSI device having a bus configuration such as 8 bits or 16 bits. In such a case, the circuit configuration of the input delay circuit can be simplified.
[0035]
In the LSI test circuit of the present invention, the signal input to the phase detector of the input delay circuit is the same period as the output clock signal and the output clock signal output from the LSI device by inputting the reference clock signal to the LSI device. The reference output signal output from the LSI tester apparatus is input to the LSI device, and the signal is output after passing through the LSI device.
[0036]
According to this configuration, it is possible to measure the delay amount of the signal more accurately by passing the signal through the LSI device and inputting the signal to the input delay circuit.
[0037]
The LSI test circuit test method of the present invention further includes a reference clock signal generated from an LSI tester device that generates a test pattern input signal, input to the LSI device, an output clock signal output from the LSI device, and an output clock. Input the reference output signal output from the LSI tester device in the same cycle as the signal, measure the delay amount between the output clock signal and the reference output signal, and input from the LSI tester device to the LSI device according to the measured delay amount In an LSI test circuit having an input delay circuit for adding a delay to the test pattern input signal between the LSI tester device and the LSI device, the measured delay amount between the output clock signal and the reference output signal, and the test pattern input signal Test pattern input signal so that the added value is constant with the added delay amount Controlling the delay amount to be added.
[0038]
DETAILED DESCRIPTION OF THE INVENTION
(Embodiment 1)
Hereinafter, a first embodiment of an LSI test circuit of the present invention will be described with reference to the drawings.
[0039]
FIG. 1 is a connection diagram of an LSI test circuit according to the first embodiment of the present invention.
[0040]
In FIG. 1, a reference clock signal 101, a test pattern input signal 102, and a reference output signal 105 are input to the LSI test board 2 from the LSI tester apparatus 1 in order to test the function of the LSI device 3.
[0041]
An output signal 103 and an output clock signal 104 are output from the LSI device 3, and the output signal 103 is connected to the LSI tester device 1 via the LSI test board 2.
[0042]
The output clock signal 104 output from the LSI device 3 is connected to the input delay circuit 4 on the LSI test board 2, and the test pattern input signal 102 input to the LSI device 3 is transmitted from the delay signal 5 through the input delay circuit 4. Input to the LSI device 3.
[0043]
The LSI tester device 1 generates a reference output signal 105 having the same cycle as the output clock signal 104 and inputs the reference output signal 105 to the input delay circuit 4 via the LSI test board 2. The reference output signal 105 has the same cycle as the output clock signal 104, but is a signal that is input to the input delay circuit 4 without delay with respect to the reference clock signal 101.
[0044]
FIG. 2 is a diagram showing an embodiment of the configuration of the input delay circuit 4.
[0045]
Here, reference numeral 23 denotes a delay element unit for delaying the input signal 102 of the test pattern from the LSI tester apparatus 1, which is constituted by an inverter, a buffer, and the like. A plurality of delay element units 23 are prepared depending on the number of input signals.
[0046]
The selection circuit 24 is a circuit (selector) that selects a predetermined delay value from the result of obtaining the phase difference between the output clock signal 104 and the reference output signal 105 by the phase detector 25. The phase detector 25 detects how much the output clock signal 104 is behind the reference output signal 105 and outputs a signal for selecting a delay value according to the phase difference.
[0047]
The configuration of the phase detector 25 can be realized by the principle of a conventional PLL or the like.
[0048]
Based on the phase difference in the phase detector 25, the delay value added by the delay element unit 23 is selected by the selection circuit 24, and a delay is added to the input signal 102. An output signal 27 with a delay added is output and input to the LSI device 3.
[0049]
The delay value selected by the delay element unit 23 operates the test pattern so that it can correspond to the input delay from the test pattern with the maximum delay of the LSI device 3 to the test pattern with the minimum delay. Prepared for each cycle of the reference clock signal 101.
[0050]
When a function test is performed using the input delay circuit 4, the test pattern input signal 102 from the LSI tester apparatus 1 uses a test pattern under a condition that the delay value is maximum.
[0051]
The reference clock signal 101 passes through the LSI test board 2 and is input to the LSI device 3. After passing through the logic circuit in the LSI device 3, a delay is added, and an output clock signal 104 and an output signal 103 are generated and output. The output clock signal 104 is input to the input delay circuit 4 and is compared with the reference output signal 105 by the phase detector 25, and it is determined which combination of delay elements is selected by the selection circuit 24 according to the delay value.
[0052]
In general, when the temperature is high and the power supply voltage is low, the signal drive capability of the transistors and buffers in the LSI device is minimized, so that the delay amount in the LSI device is maximized.
[0053]
In this case, since the delay amount in the LSI device 3 is maximized, the total delay amount is made constant regardless of the delay amount of the LSI device by minimizing the delay amount added to the input signal 102. To do. Here, the selection circuit 24 in the input delay circuit 4 selects a signal to which no delay due to the delay element is added to the input signal 102, and the output signal 27 is sent to the LSI device 3 without delay in the input signal 102 from the LSI tester apparatus 1. Entered.
[0054]
FIG. 3 is a diagram showing a simulation waveform at the time of maximum delay in the LSI device 3. Here, the test pattern input signal 102 operates with the reference clock signal 101 as a reference. A delay value is calculated from the reference output signal 105 and the output clock signal 104 input to the input delay circuit 4, and when the delay amount between the reference output signal 105 and the output clock signal 104 is large as shown in FIG. The signal 102 having the smallest delay value is selected by the selection circuit 24 and output as the output signal 27. This output signal 27 is input to the LSI device 3. An output signal 103 is output from the LSI device 3 and is input to the LSI tester apparatus 1 and compared with an expected output value to determine pass / fail.
[0055]
Next, when the temperature is low and the power supply voltage is high, the drive capability of the transistor and buffer signals is maximized, and therefore the delay amount inside the LSI device 3 is minimized.
[0056]
FIG. 4 is a diagram showing a simulation waveform when the delay in the LSI device 3 is minimum. The test pattern operates based on the reference clock signal 101 input from the LSI tester apparatus 1. In the phase detector 25, a delay value is calculated from the reference output signal 105 and the output clock signal 104 input to the input delay circuit 4, and when the delay difference between the reference output signal 105 and the output clock signal 104 is small, the selection circuit 24, the input signal 102 is selected so that the delay having the largest delay value is added.
[0057]
For this reason, the input of the test pattern applied to the LSI device 3 is an output signal 27 in which a larger delay value is added to the input delay circuit 4, and the waveform of the output signal 103 of the LSI device 3 has the small delay value of FIG. The waveform is equivalent to the added output signal 103 waveform, and measurement can be performed with the same output expected value test pattern.
[0058]
As described above, when the delay value of the signal in the LSI device 3 is small, the input delay circuit 4 increases the delay value added to the input signal 102 from the LSI tester apparatus 1, and conversely the signal in the LSI device 3. When the delay value is large, in order to reduce the delay added to the input signal 102 from the LSI tester device 1 of the input delay circuit 4, the delay is added to the input signal 102 in accordance with the delay in the LSI device 3 to thereby change the LSI tester. It is possible to perform a function test in actual operation using the apparatus 1 with one test pattern.
[0059]
That is, in the input delay circuit 4, the delay amount inside the LSI device 3 is obtained from the phase difference between the reference output signal 105 and the output clock signal 104, the signal delay amount inside the LSI device 3, and the input signal 102 The delay amount to be added is controlled so that the added value with the delay amount to be added becomes a constant value.
[0060]
As a result, at the time of a function test, even if the temperature and power supply voltage conditions change, measurement can be performed with one function test pattern by having this LSI test circuit.
[0061]
In particular, when acquiring a power supply voltage and frequency two-dimensional characteristic plot (SHMOO) of an LSI device, it is difficult to measure by changing the test program to the strobe position adapted to each temperature and power supply voltage condition. Measurement can be performed by using the LSI test circuit of the present invention. Also, there is no need to change the LSI test program.
[0062]
Further, the same effect can be obtained by incorporating the input delay circuit 4 of FIG. 1 in the LSI tester device 1.
[0063]
In this case, the function can be used without adding an input delay circuit on the LSI test board. In this case, a conventional LSI test board may be used.
[0064]
(Embodiment 2)
FIG. 5 is a diagram showing an input delay circuit according to the second embodiment of the present invention.
[0065]
By the way, in the input delay circuit of FIG. 2, the delay element unit 23 is necessary for each input signal 102. When the number of the input signals 102 is large, it is necessary to prepare the delay element units 23 corresponding to the number of input signal circuits. The scale of.
[0066]
On the other hand, the input signal 102 generally has a bus configuration of 8 bits, 16 bits, etc., and these signals often have the same amount of delay. The second embodiment is an input delay circuit corresponding to such a case.
[0067]
The reference output signal 105 from the LSI tester apparatus 1 and the output clock signal 104 output from the LSI device 3 are input to the phase detector 55.
[0068]
Further, the reference clock signal 101 is connected to the delay element unit 53, and is connected to the selection circuit 54 through the delay element unit 53. Based on the value detected by the phase detector 55, the selection circuit 54 determines which delay is added to the reference clock signal 101.
[0069]
The reference clock signal 101 delayed by the delay element unit 53 passes through the selection circuit 54 and is connected to the clock input of a flip-flop (hereinafter referred to as FF) 58.
[0070]
The input signal 102 from the LSI tester device 1 is connected to the input D terminal of the FF 58 and is output as a delayed signal from the output Q terminal of the FF 58 when the output signal of the selection circuit 54 rises. An output signal 57 output from the output Q terminal is input to the LSI device 3 as an input signal to the LSI device 3.
[0071]
The output signal 57 at the output Q terminal of the FF 58 can be considered as a delay element because the input signal 102 input to the input D terminal of the FF 58 is not output until the rise timing of the output signal of the selection circuit 54, and can be considered as a delay element. Has the same function.
[0072]
Since the other configuration is the same as that in FIG. 1, the actual signal operation is the same as that in FIGS. 3 and 4 of the first embodiment of the present invention.
[0073]
(Embodiment 3)
FIG. 6 is a diagram showing a circuit configuration of a part of a clock input to the LSI device according to the third embodiment of the present invention.
[0074]
The reference clock signal 101 is input from the LSI tester apparatus 1 to the LSI device 3 via the input IO pad 603 of the LSI device 3.
[0075]
The reference clock signal 101 passes through the logic circuit portion 604 and is input as a clock signal of the FF 605. Since the logic circuit unit 604 includes a balance buffer and a delay adjustment circuit for supplying clocks to the LSI device 3 at the same time, a delay occurs.
[0076]
The clock signal frequency-divided through the FF 605 and the combinational circuit unit 606 is output as the output clock signal 104 via the output IO pad 607, and this signal is input to the input delay circuit 4 as the output clock signal 104.
[0077]
Further, the reference output signal 105 is input from the LSI tester apparatus 1 to the LSI device 3 via the input IO pad 611. The input signal 612 passes through the LSI device 3 and is output as a delayed reference output signal 614 via the output IO pad 613. The delayed reference output signal 614 is input to the input delay circuit 4 as a reference output signal. Is done.
[0078]
The delayed reference output signal 614 passing through the LSI device 3 and input to the input delay circuit 4 is delayed when passing through the input IO pad 611 and the output IO pad 613 inside the LSI device 3. For this reason, the delayed reference output signal 614 input to the input delay circuit 4 measures the internal delay 650 excluding the IO pad of the LSI device 3, and therefore is delayed from the output clock signal 104 in the input delay circuit 4. By obtaining the phase difference of the reference output signal 614, it is possible to accurately measure the delay inside the circuit.
[0079]
In the first and second embodiments, the reference output signal 105 from the LSI tester device 1 is directly input to the input delay circuit 4. However, the LSI tester device 1 is also used in the first and second embodiments as in the third embodiment. The same effect can be obtained by inputting the delayed reference output signal 614, which is once input to the LSI device 3 and passed through the circuit, to the input delay circuit 4.
[0080]
【The invention's effect】
As described above, according to the present invention, even when the delay value of the output signal changes more than several cycles of the reference clock signal used at the time of the function test, the measurement with the same test program, test pattern, power supply voltage, frequency 2 Dimensional characteristic plot (SHMOO) measurement is possible.
[0081]
Further, since only one type of test pattern is required, the pattern memory capacity can be saved and the test time (test pattern reading time) can be shortened.
[Brief description of the drawings]
FIG. 1 is a connection diagram of an LSI test circuit according to the first embodiment of the present invention. FIG. 2 is an input delay circuit diagram according to the first embodiment of the present invention. FIG. 5 is a diagram of an input delay circuit according to the second embodiment of the present invention. FIG. 6 is a circuit configuration diagram of an LSI device clock according to the third embodiment of the present invention.
DESCRIPTION OF SYMBOLS 1 LSI tester apparatus 2 LSI test board 3 LSI device 4 Input delay circuit 5 Delay signal 23 Delay element part 24,54 Select circuit 25 Phase detector 27,57,103 Output signal 53 Delay element part 55 Phase detector 58,605 Flip-flop (FF)
101 reference clock signal 102 input signal 104 output clock signal 105 reference output signal 603, 611 input IO pad 604 logic circuit unit 606 combinational circuit unit 607, 613 output IO pad 612 signal 614 delayed reference output signal 650 internal delay

Claims (6)

A reference clock signal generated from an LSI tester device that generates a test pattern input signal is input to the LSI device, and an output clock signal output from the LSI device;
A reference output signal output from the LSI tester device in the same cycle as the output clock signal is input,
An input delay circuit that measures a delay amount between the output clock signal and the reference output signal and adds a delay to the test pattern input signal input from the LSI tester device to the LSI device according to the delay amount. An LSI test circuit provided between a tester device and the LSI device. 2. The LSI test circuit according to claim 1, wherein the input delay circuit is provided in the LSI tester device. The input delay circuit includes a phase detector that detects a phase difference between the output clock signal and the reference output signal, a plurality of delay elements that delay the test pattern input signal, and a selection circuit that selects a delay amount. 3. The LSI test circuit according to claim 1, wherein the LSI test circuit is characterized in that: The input delay circuit includes a phase detector that detects a phase difference between the output clock signal and the reference output signal, a delay element, a selection circuit that selects a delay amount of the delay element, and an output signal of the selection circuit. 3. The LSI test circuit according to claim 1, further comprising a flip-flop that holds an input value. The signal input to the phase detector of the input delay circuit is the LSI having the same period as the output clock signal input from the LSI device by inputting the reference clock signal to the LSI device. 5. The reference output signal output from a tester device is input to the LSI device, and the signal is output after passing through the LSI device. LSI test circuit. A reference clock signal generated from an LSI tester device that generates a test pattern input signal is input to the LSI device, and an output clock signal output from the LSI device and output from the LSI tester device in the same cycle as the output clock signal. The test pattern input signal that is input to the LSI device from the LSI tester device according to the measured delay amount, the reference output signal to be input is input, the delay amount between the output clock signal and the reference output signal is measured In an LSI test circuit comprising an input delay circuit for adding a delay between the LSI tester device and the LSI device, the measured delay amount between the output clock signal and the reference output signal,
A test method for an LSI test circuit, comprising: controlling a delay amount to be added to the test pattern input signal so that an added value is constant with a delay amount to be added to the test pattern input signal.

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