JP4032612B2 - Operating frequency measuring apparatus and image forming apparatus - Google Patents

Description

[0001]
[Technical field to which the invention belongs]
The present invention relates to an operating frequency measuring apparatus and an image forming apparatus, and more particularly to an operating frequency measuring apparatus capable of inspecting an upper limit of an operating frequency of a circuit and an image forming apparatus provided with the operating frequency measuring apparatus.
[0002]
[Prior art]
Various digital circuits require a clock for circuit operation. This clock is generated by various types of clock generation circuits. In recent years, high speed processing has been required for each circuit, and the clock frequency (operating frequency) has been increasing year by year.
[0003]
The operating frequency of the circuit depends on the delay amount of each device, which varies due to various factors such as manufacturing variations, temperature fluctuations, power supply voltage fluctuations, and the like.
In order to operate the circuit at the specified operating frequency,
・ Circuit design with sufficient margin for various variations.
・ Devise each in terms of circuit description, logic synthesis, layout, etc.
-Use a dedicated tool on the computer to perform delay simulation, delay analysis, etc. to confirm and feed back to the circuit design.
[0004]
[Problems to be solved by the invention]
In order to measure the operating frequency of the circuit, test data is input to an actual device using a dedicated tester, and the output of the device is compared with an expected value obtained in advance in the tester. Thereby, it is possible to test whether or not the real device can be operated at a specific operating frequency. Furthermore, the upper limit (maximum operating frequency) of the operating frequency can be obtained by executing this test while changing the operating frequency. As a result, it is possible to improve the operating frequency by eliminating the margin provided for manufacturing variations. However, there is a problem that an expensive dedicated tester is required, and there is also a problem that all mass production devices must be tested.
[0005]
In addition to the above-described method using a dedicated tester, a scan path method and a boundary scan method (JTAG) are also used. In these methods, a dedicated circuit is added between the logic part in the device of the circuit and between the terminals of the device, test data is automatically generated with a dedicated tool, and all terminals and devices are inspected without exception. is there. However, there are problems that test data different from the actual operation is used and that inspection at the actual operation frequency cannot be performed due to technical restrictions.
[0006]
Furthermore, there is a method called BIST (Built-In Self-Test), which is expected in the normal state by supplying input test data to the circuit to be inspected and input test data to the circuit to be inspected. A test data generation unit that generates expected value test data, and an operation state of the circuit to be inspected by comparing the expected test data with output test data that the circuit to be inspected receives and outputs the input test data And a self-test is automatically executed.
[0007]
However, even with such a BIST, the upper limit (maximum operating frequency) of the operating frequency is obtained while freely changing the operating frequency in the actual device mounting state, and is provided for manufacturing variations and the like. It was difficult to improve the operating frequency by eliminating the margin. That is, even if the frequency is made variable by using a PLL circuit for the clock generation unit, a certain time is required until a stable state is obtained at the changed frequency, and the operating frequency is obtained by frequently changing the frequency. Will need a lot of time.
[0008]
The present invention has been made to solve the above-described problem, and in an actual device mounting state, while freely changing the operating frequency, obtaining the upper limit of the operating frequency (maximum operating frequency), An object of the present invention is to provide an operating frequency measuring device and an image forming apparatus capable of improving the operating frequency by eliminating a margin provided for manufacturing variations and the like.
[0009]
[Means for Solving the Problems]
The above-described problem can be solved by the following configuration.
(1) The present invention is to supply and control unit for instructing the frequency data the frequency of the clock that occur, a clock generator for generating a clock having a frequency corresponding to the frequency data, the input test data to the circuit under test And a test circuit for determining an operation state of the circuit under test by comparing output test data output by the circuit under test upon receiving input test data and the expected value test data, and the clock generator The operating frequency measuring device measures the frequency at which the circuit under test can be operated by determining the operating state of the circuit under test while changing the frequency of the generated clock. A delay chain unit in which delay elements are connected in a chain to generate a plurality of delayed clocks obtained by delaying the clock; A delay detection unit for deriving delay information from the output of the ray chain unit; and a switch for generating switching control information indicating a delay clock to be selected from the plurality of delay clocks with reference to the delay information and the frequency data A control unit and a selection unit that generates a clock having a desired frequency by selecting from the plurality of delay clocks based on the switching control information, and the delay detection unit includes a plurality of delay units from the delay chain unit. Flip-flops are connected to the respective delay signal outputs, and a circuit for detecting synchronization point information synchronized with a reference clock among the delay signal outputs is provided, and the number of delay stages between them from the adjacent synchronization point information The test circuit outputs input test data to be supplied to the circuit to be inspected and input test data to the circuit to be inspected. A test data generation unit for generating expected value test data expected in a normal state by supplying data, and comparing the output test data output by the circuit under test receiving the input test data with the expected value test data And a determination unit for determining an operation state of the circuit to be inspected .
[0010]
In the invention of the operating frequency measuring device, when measuring the operable frequency of the circuit under test, the operating state of the circuit under test is determined while changing the frequency of the clock generated by the clock generator. The upper limit of the operable frequency of the circuit under test can be measured.
[0011]
As a result, the upper limit of the operating frequency (maximum operating frequency) is obtained while freely changing the operating frequency in the actual device mounting state, and the margin provided for manufacturing variations is eliminated. It becomes possible to improve the operating frequency. In this case, it is not necessary to use an expensive tester. In addition, an inexpensive digital circuit of a C-MOS process can be used for the circuit to be inspected without using an expensive process technology.
[0012]
Further, it is possible to change the operation speed of the circuit to be inspected by setting by software without changing the circuit board of the circuit to be inspected. Along with this, it becomes possible to determine the operating frequency in consideration of the influence of EMI.
[0014]
( 2 ) In the above (1 ) , the test circuit supplies input test data to be supplied to the circuit to be inspected and expected value test data to be expected in the normal state by supplying the input test data to the circuit to be inspected. A test data generation unit that generates, and a determination unit that determines an operation state of the circuit to be inspected by comparing output test data that the circuit to be inspected receives and outputs the input test data with the expected value test data; Are desirable.
[0015]
( 3 ) In the above (1) or ( 2 ), it is preferable that each of the parts is formed of an integrated circuit .
[0016]
(4 ) In the above (1) to ( 3 ), it is desirable that each of the parts is constituted by a digital circuit.
[0017]
( 5 ) It is also desirable to provide the operating frequency measuring device of the above (1) to ( 4 ) and make the image processing circuit a circuit to be inspected.
[0018]
DETAILED DESCRIPTION OF THE INVENTION
Embodiments of an operating frequency measuring device and an image forming apparatus to which the operating frequency measuring device of the present invention is applied will be described below in detail with reference to the drawings.
[0019]
<Overall configuration of operating frequency measuring device>
Hereinafter, an embodiment of the operating frequency measuring apparatus according to the embodiment of the present invention will be described in detail.
[0020]
In FIG. 1, reference numeral 100 denotes a circuit to be inspected for measuring an operable frequency. Various circuits are targeted, and an image processing circuit in an image forming apparatus is desirable. Reference numeral 101 denotes a CPU that operates as a control unit that controls the entire clock generation device or the entire operating frequency measurement device. The CPU 101 generates frequency data ((3) in FIG. 1) in order to set the clock frequency. Reference numeral 102 denotes input test data (FIG. 1 (8)) supplied to the circuit under test 100, and expected value test data expected when the input test data is supplied to the circuit under test 100 (FIG. 1 (7)). Is a test data generation unit that generates The test data generation unit 102 generates input test data and expected value test data, but each test data may be generated by a separate circuit. Reference numeral 103 denotes an operation of the circuit under test 100 by comparing the output test data (FIG. 1 (9)) received and output by the circuit under test 100 with the expected value test data (FIG. 1 (7)). It is the determination part which determines a state. Note that the test circuit in the claims includes a test data generation unit 102 and a determination unit 103.
[0021]
Reference numeral 400 denotes a clock generator, which includes the following 410 to 450. Reference numeral 410 denotes a reference clock generation unit that generates a reference clock (reference clock).
[0022]
A delay chain unit 420 delays an input signal (a reference clock from the reference clock generation unit 410) to obtain a plurality of delay clocks (a plurality of clocks: FIG. 1 (1)) whose phases are slightly different.
[0023]
Here, in the delay chain unit 420, a large number of delay elements are cascade-connected so that the number of stages that can be generated over two cycles of the reference clock for the delay clocks with slightly different phases .
[0024]
A delay detection unit 430 derives delay information from the output of the delay chain unit 420. That is, it is a means for detecting the number of stages (synchronization point) of the delay clock synchronized with the reference clock (tip position of the desired input signal) among a plurality of clocks (FIG. 1 (2)), and outputs delay information To do. This delay information can also be called a phase difference state, and this delay information (phase difference state) includes synchronization point information described later and the state of the phase difference itself (phase difference state).
[0025]
Here, the delay detection unit 430 is provided with the reference clock from the reference clock generation unit 410 and a plurality of clocks from the delay chain unit 420, and the delay detection unit 430 includes a plurality of clocks ( circle numeral 1 in FIG. 1 ). The first synchronization point information V1st first synchronized with the reference clock, the second synchronization point information V2nd synchronized second with the reference clock, and the number of delay stages Vprd between them (circle in FIG. 1) The number 2) can be output .
[0026]
FIG. 2 shows the reference clock and DL19 to DL51 among a plurality of clocks. In this example, the first synchronization point information V1st = 20, the second synchronization point information V2nd = 50, and the delay stage number Vprd = 30. , Has become.
[0027]
In addition, in order to detect the number of stages synchronized with the reference clock as described above, a flip-flop that inputs adjacent outputs of the plurality of delay chain units 420 is provided, and a place where the logic of the adjacent input is inverted is provided. What is necessary is just to make it detect.
[0029]
Reference numeral 440 denotes a switching control unit that generates select stage number information. The reference clock from the reference clock generation unit 410, the synchronization point information from the delay detection unit 430 ((2) in FIG. 1), and the frequency data from the CPU 101 (see FIG. 1) in order to generate a clock pulse having a desired frequency (desired period) by causing the clock to rise and fall at a desired timing (predetermined time or predetermined time). The selected stage number information (FIG. 1 (4)) indicating which phase of the clock should be selected from among the plurality of clocks (FIG. 1 (2)).
[0030]
The selection unit 450 receives the selection stage number information (FIG. 1 (4)) from the switching control unit 440, and selects a desired rise and fall from a plurality of clocks (FIG. 1 (1)) from the delay chain unit 420. Are selected to generate a clock pulse (FIG. 1 (5)) having a desired frequency.
[0031]
As shown in FIG. 3, the selector 450 includes a selector 451 for selecting a clock having a desired rise timing, a selector 452 for selecting a clock having a desired fall timing, and a desired rise timing. Combinational circuit 452 composed of logical circuits (AND, OR, NAND, NOR, ExOR, ExNOR, etc.) that generate a desired clock pulse (FIG. 1 (5)) with the clock of the falling edge and the clock of the desired falling timing. It consists of
[0032]
With the circuit configuration as described above, the selection unit 450 can select a desired timing according to the selection stage number information determined by the switching control unit 440 according to delay information about a plurality of clocks (see FIG. 2) generated by the delay chain unit 420. In addition, a clock pulse having a desired frequency can be generated.
[0033]
Since the clock generator 400 digitally determines (selects) the rising and falling edges of the output clock pulse in response to an instruction from the CPU 101, the frequency and timing can be changed instantaneously. . Further, even if the delay time varies due to the elements of the delay chain unit 420, the variation is detected by the delay detection unit 430, so that the final clock pulse is not affected, and the clock having a stable timing and frequency is used. A pulse can be obtained. That is, there is no problem that a setup time such as a frequency change by a conventional PLL circuit is required. That is, it is possible to obtain a desired clock pulse instantaneously by calculating in real time.
[0034]
In addition, since the clock generator 400 uses a plurality of clocks to determine the rise and fall of the final clock pulse, unlike the multiplication and division of a general digital circuit, the reference clock It is possible to obtain a clock pulse having an arbitrary frequency, not limited to an integral multiple of the frequency.
[0035]
FIG. 4 is a time chart showing the operating state of the operating frequency measuring apparatus according to the present embodiment.
Here, it is assumed that the reference clock from the reference clock generation unit 410 is 100 MHz (FIG. 4A). Then, the operation frequency measurement is started at the timing when the start signal in FIG.
[0036]
In the first test period, the CPU 101 supplies frequency data (FIG. 1 (3)) for generating a 50 MHz clock pulse by dividing the reference clock by two to the switching control unit 440 and the determination unit 103. . In the next test period, the CPU 101 supplies frequency data (FIG. 1 (3)) for generating a clock pulse of 100 MHz equal to the reference clock to the switching control unit 440 and the determination unit 103. Further, in the next test period, the CPU 101 supplies frequency data (FIG. 1 (3)) for generating a clock pulse of 150 MHz by multiplying the reference clock by 1.5 to the switching control unit 440 and the determination unit 103. (FIG. 4D).
[0037]
For example, various setting values necessary for operating the circuit under test 100 such as parameters for image processing calculation are set in advance before operating frequency measurement.
[0038]
First, in the first test period, when input test data (FIG. 1 (8)) is supplied to the input terminal of the circuit under test 100 to which a clock pulse of 50 MHz is supplied, the output is made from the output terminal of the circuit under test 100. Test data (FIG. 1 (9)) is obtained. The determination unit 103 compares the output test data (FIG. 1 (9)) with the expected value test data (FIG. 1 (7)) generated by the test data generation unit. Since the output test data at the clock pulse 50 MHz (FIG. 4 (h)) and the expected value test data (FIG. 4 (h)) match, the determination unit 103 determines “OK” (FIG. 4 (i)). )).
[0039]
In the next test period, when input test data (FIG. 1 (8)) is supplied to the input terminal of the circuit under test 100 to which a clock pulse of 100 MHz is supplied, the output is made from the output terminal of the circuit under test 100. Test data (FIG. 1 (9)) is obtained. The determination unit 103 compares the output test data (FIG. 1 (9)) with the expected value test data (FIG. 1 (7)) generated by the test data generation unit. The output test data (FIG. 4 (h)) and the expected value test data (FIG. 4 (h)) at the clock pulse of 100 MHz are almost the same, but some of them are inconsistent. Determines “NG” (FIG. 4I).
[0040]
Since “NG” is determined at 100 MHz, the CPU 101 may determine that a test at a higher frequency than this is unnecessary, and may end the test mode.
[0041]
Upon receiving the determination result from the determination unit 103 as described above, the CPU 101 determines the maximum frequency at which “OK” is output as the determination result as the upper limit (maximum operating frequency) of the operating frequency. In the case of this embodiment, the CPU 101 determines 50 MHz as the maximum operating frequency (FIG. 4 (j)).
[0042]
In the above embodiment, for simplicity of explanation, the clock pulse is measured at 50 MHz, 100 MHz, and 150 MHz when the reference clock is 100 MHz. However, the present invention is not limited to this frequency. Since the clock generator 400 can freely select the frequency of the clock pulse, the frequency can be gradually increased in fine steps such as 1 MHz unit, and the maximum operating frequency of the circuit under test 100 can be strictly determined. Is possible.
[0043]
That is, according to the present embodiment, it is possible to obtain the upper limit (maximum operating frequency) of the operating frequency while freely changing the operating frequency in a mounted state in an actual device. Furthermore, it becomes possible to improve the operating frequency by eliminating the margin provided for manufacturing variations.
[0044]
Further, in this embodiment, since the clock generator 400 can digitally change the frequency instantaneously, the operation of measuring the maximum operating frequency while changing the frequency does not require wasted time. Can be executed in a short time in a stable state.
[0045]
Further, according to this embodiment, the circuit under test 100 can be set to operate at a frequency with the least EMI.
Further, in this embodiment, a simple configuration can be used, and there is no need to use an expensive tester as in the prior art. In addition, an inexpensive digital circuit of a C-MOS process can be used for the circuit to be inspected without using an expensive process technology.
[0046]
Further, the operating frequency measuring apparatus according to this embodiment can be incorporated in an image forming apparatus such as a copying machine when the circuit under test 100 is an image processing circuit. In this case, the frequency of image processing can be changed by the control of the CPU 101 (software processing) without changing the substrate. It is also possible to change the image processing speed in accordance with the image forming speed.
[0047]
【The invention's effect】
As described above in detail, according to the present invention, it is possible to obtain the upper limit (maximum operating frequency) of the operating frequency while freely changing the operating frequency in a mounted state in an actual device. Furthermore, it becomes possible to improve the operating frequency by eliminating the margin provided for manufacturing variations.
[Brief description of the drawings]
FIG. 1 is a configuration diagram showing an overall electrical configuration of an operating frequency measuring apparatus according to an embodiment of the present invention.
FIG. 2 is a time chart for explaining the clock generation operation of the operating frequency measuring device according to the embodiment of the present invention.
FIG. 3 is a configuration diagram showing an electrical configuration of a main part of the operating frequency measuring device according to the embodiment of the present invention.
FIG. 4 is a time chart for explaining the operation of the operating frequency measuring device according to the embodiment of the present invention.
[Explanation of symbols]
100 Circuit under test 101 CPU
102 test data generation unit 103 determination unit 410 reference clock generation unit 420 delay chain unit 430 delay detection unit 440 switching control unit 450 selection unit

Claims (5)

And a control unit for instructing by the frequency data the frequency of the clock that occur,
A clock generator for generating a clock having a frequency according to the frequency data;
A test for determining the operating state of the circuit under test by supplying input test data to the circuit under test and comparing the output test data output by the circuit under test with the input test data and the expected value test data A circuit,
An operating frequency measuring device that measures the operable frequency of the circuit under test by determining the operating state of the circuit under test while changing the frequency of the clock generated by the clock generator ,
The clock generator is
A delay chain unit in which delay elements are connected in a chain to generate a plurality of delay clocks obtained by delaying a reference clock;
A delay detection unit for deriving delay information from the output of the delay chain unit;
A switching control unit that generates switching control information indicating a delay clock to be selected from the plurality of delay clocks with reference to the delay information and the frequency data;
A selection unit configured to generate a clock having a desired frequency by selecting from the plurality of delay clocks based on the switching control information;
The delay detection unit is configured to connect a flip-flop to each output of a plurality of delay signals from the delay chain unit, and provide a circuit that detects synchronization point information synchronized with a reference clock among the outputs of the delay signal, An operating frequency measuring apparatus that outputs the number of delay stages between the adjacent synchronization point information as delay information . The test circuit includes:
A test data generation unit for generating input test data to be supplied to the circuit to be inspected and expected value test data to be supplied when the input test data is supplied to the circuit to be inspected;
A determination unit configured to determine an operation state of the circuit to be inspected by comparing the output test data output by the circuit to be inspected upon receiving the input test data and the expected value test data ; 2. The operating frequency measuring apparatus according to claim 1, wherein The operating frequency measuring apparatus according to claim 1 , wherein each of the units is configured by an integrated circuit . The operating frequency measuring apparatus according to claim 1 , wherein each of the units is configured by a digital circuit . An image forming apparatus comprising the operating frequency measuring device according to claim 1, wherein the image processing circuit is a circuit to be inspected.

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