JP2007110686A - Digital circuit, semiconductor device, and clock adjusting method - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To perform an inspection while compensating for delay variations by automatically adjusting a variable delay circuit using a low-speed versatile inspection apparatus, and to achieve cost reduction and improve inspection quality. <P>SOLUTION: A digital circuit 10a comprising a clock operating circuit for outputting a data signal in accordance with input timing of a clock signal is provided with: variable delay circuits 13-1, 13-2 for giving a predetermined delay time to the clock signal or to the data signal; a delay circuit 14a having a delay time that is a predetermined multiple of a period of a test signal; and a data holding circuit for determining whether delay variation of the data signal is earlier or later than a predetermined time by comparing a time obtained by multiplying the period of the test signal by a predetermined factor with the delay time of the delay circuit 14a, and compensating for the delay time of the variable delay circuits 13-1, 13-2 on the basis of the result of the determination. <P>COPYRIGHT: (C)2007,JPO&INPIT

Description

  The present invention relates to a digital circuit provided with one or more clock operation circuits (for example, flip-flops, etc.) that perform a predetermined operation based on an input of a clock signal, a semiconductor device equipped with the digital circuit, and the digital With regard to a clock adjustment method for a circuit, in particular, a digital suitable for improving inspection quality while realizing cost reduction by compensating for delay variation between clock operation circuits in a digital circuit using a general-purpose low-speed test device. The present invention relates to a circuit, a semiconductor device, and a clock adjustment method.

In general, an LSI constituted by a large number of circuit elements is designed with a specific circuit structure using a computer-aided design method (CAD). In this development process using CAD, abstract circuit data corresponding to the function of the LSI to be developed is defined in the hardware description language based on the determined specifications, and further, logic synthesis is performed to generate a logic circuit. A specific circuit structure to be mounted on the chip is determined.
An LSI manufactured through such a design process undergoes a verification operation at a logic level and an actual operation level at the stage of the manufacturing process. For example, at the wafer level stage, logic verification is performed by a low-speed inspection device to eliminate defective products, actual operation is verified at the stage when chip packaging is completed, and only products that are determined to be good products are shipped as products. is doing.

The manufacturing process of such an LSI will be described with reference to FIG.
As shown in the figure, the LSI manufacturing process generally passes through an LSI design stage, an LSI process stage, and an LSI assembly inspection stage.
The LSI design stage is a stage in which functional design, logic design, circuit design, layout design, etc. are usually performed using CAD.
The LSI process stage is the stage where LSI is actually manufactured, such as mask manufacturing, wafer manufacturing (single crystal manufacturing, machining, lapping, polishing, etc.), wafer processing (thin film formation, oxidation, doping, annealing, etching, etc.), etc. Is the stage where

The LSI assembly inspection stage is a stage in which wafer probing (wafer test), mounting assembly, final test, board mounting, initialization, and the like are performed.
Among them, in wafer probing, LSIs built into a wafer are automatically inspected one by one while remaining in the form of a wafer. In this inspection, an inspection needle (probe) is applied to the wafer, and a test signal having a predetermined frequency is transmitted and received between the probe and the LSI.

In mounting assembly, dicing processing to divide the wafer into each LSI chip, bonding processing to connect the electrode on the chip surface and the lead frame terminal with a gold wire, molding processing to completely seal the LSI chip in plastic resin (package) Etc.) are performed.
In the final test, various automatic inspection devices (testers) are used to verify the actual operation of the mounted LSI to see if its electrical characteristics and reliability are ensured. Only then will be shipped as a product.

In board mounting, the packaged LSI is mounted on a board (board) made of epoxy or the like.
In the initialization, each value of the circuit mounted on the LSI is initialized.

By the way, many LSI chips are fabricated on one wafer, but not all of them have good characteristics. For example, in the stage of actually forming a designed circuit on a semiconductor substrate, it is not easy to completely reproduce the electrical characteristics of the designed circuit structure due to delay variations based on process, voltage, and temperature. There may be a difference in characteristics between the designed circuit and the mounted circuit.
If such a difference in characteristics is slight, there is no practical problem. However, for example, in a portion that operates at high speed, the operation is hindered due to a difference in delay time caused by a subtle difference in film thickness. Sometimes.

  On the other hand, in consideration of the entire range of variation, there is a design method that allows variable delay circuits to be used to transfer the delay amount after initialization for critical paths that cannot transfer data between flip-flops. It has been proposed (see, for example, Patent Document 1).

As shown in FIG. 9, this proposal is based on a digital circuit 100 in which a plurality of circuits operating in synchronization with an input clock signal (in the figure, clock operation circuits 111-1 and 111-2) are connected. A plurality of variable delay circuits 113-1 and 113-2 capable of variably setting the delay time are inserted on the input signal lines of the clock signals of the plurality of circuits, and the plurality of variable delay circuits 113-1 and 113-2 are inserted. By variably setting the delay time, the phase shift of the clock signal is compensated.
As a result, the phase of the clock signal constituting the digital circuit can be adjusted to the same timing or a predetermined timing according to the delay amount of the delay element, regardless of a subtle difference in film thickness.
JP 2000-285144 A

  However, the above proposal (the clock signal adjusting method described in Patent Document 1) adjusts the delay time by initialization in actual operation. For this reason, after the adjustment, the flip-flop can operate at, for example, 1066 MHz, but there is no delay setting that allows the flip-flop to be delivered in all delay variations in a fixed pattern at the time of inspection.

In addition, the above proposal searches for an optimum delay time by a full search method, a random search method, a dynamic programming method (DP), a genetic algorithm (GA) search method, a search method using CAD information, and the like. However, these are methods suitable for adjustment using a clock signal having the same frequency as the actual operation at initialization after mounting on the board. For this reason, in wafer probing in which inspection is performed with a low-speed signal, an inadequate inspection method has been used because the clock frequency is slow and it cannot be determined whether adjustment is possible.
Therefore, if properly inspected, an LSI that can be excluded as a defective product is mounted, and it is determined as a defective product by initialization, and it is necessary to replace the LSI mounted on the board. By appropriately inspecting before board mounting, these LSI replacement and initialization operations can be avoided.

Furthermore, it is not necessary to waste useless packaging costs if defective products of LSI can be detected by wafer probing instead of final test.
However, in the wafer probing performed at the wafer stage, since the probe does not pass the high-speed signal, the inspection with the low-speed signal is forced as described above. Therefore, it has been desired to propose an inspection technique that can determine delay variation using a low-speed general-purpose inspection apparatus.

The LSI originally has the ability to move by itself (self). When a signal is input, the LSI operates according to the circuit configuration and outputs a desired signal. For example, in the final test and initialization, the actual operation level can be verified by inputting a high-speed operation test signal.
On the other hand, in wafer probing, the actual operation level cannot be verified because the probe does not pass high-speed signals, but from the viewpoint of eliminating waste such as packaging defective products, low-speed testing is performed before mounting. .

By the way, in the above-mentioned critical path, although it is not necessary to give a delay, delay variation may occur between FFs due to factors such as process, temperature, and voltage. Between these FFs, the setup and hold times must be kept between the data and the clock, but the eye opening may be closed due to delay variation, and in this case, the test signal passes through the critical path. A situation occurs in which test results cannot be obtained. If the test result cannot be obtained in this way, the LSI is determined to be defective, but this is due to the process and the like, and there is always a defective element in the circuit design and configuration itself. It is not a thing.
Here, when it is determined that the LSI is defective due to a process or the like, if the delay amount is adjusted at the time of initialization, the LSI can be handled as a non-defective product and can be commercialized. However, since it is not easy to determine whether the cause of the defect is a process or the like, even if there is such an LSI, it is treated as a defective product after wafer probing (before mounting). It was a cause of yield reduction.

  The present invention has been considered in view of the above circumstances, and by using a low-speed general-purpose inspection device, the variable delay circuit can be automatically adjusted to compensate for delay variation, and can be inspected. An object of the present invention is to provide a digital circuit, a semiconductor device, and a clock adjustment method capable of improving inspection quality and further improving product yield in wafer probing.

  In order to achieve this object, the digital circuit of the present invention includes one or more clock operation circuits that input a data signal and output a data signal according to the input timing of the clock signal, and the clock signal and / or the data signal. A delay circuit that has a variable delay circuit that gives a predetermined delay time to the clock signal, and the delay variation of the data signal output from the clock operation circuit differs depending on whether the delay variation is faster or slower than the predetermined time A configuration is provided that includes an adjustment circuit that outputs a signal, sends the delay setting signal to the variable delay circuit, and sets the delay time of the variable delay circuit.

When the digital circuit has such a configuration, it is determined whether the delay variation of the data signal output from the clock operation circuit is faster or slower than a predetermined time, and the delay time of the variable delay circuit is set based on the determination result. Since the configuration is adopted, the frequency output from the low-speed general-purpose inspection apparatus can be used to determine the delay variation of the data signal.
Whether the determined delay variation is fast or slow is reflected in the variable delay circuit as variation information, and thus the variable delay circuit can be automatically adjusted to compensate for the delay time of the variable delay circuit.

Furthermore, since the delay time of the variable delay circuit can be compensated using a general-purpose low-speed inspection device, the inspection cost can be reduced.
In addition, since it is possible to provide a clock inspection method suitable for a low-speed general-purpose inspection apparatus, it is possible to determine an LSI defect in wafer probing. As a result, LSI replacement work after board mounting, initialization re-execution, and unnecessary packaging costs can be reduced, and inspection quality can be improved.

  Furthermore, since the delay time of the variable delay circuit is set based on the delay setting signal, the delay variation of the clock operation circuit can be corrected, the eye opening can be secured, and the test signal can be passed. Therefore, the quality of the LSI can be determined based on the test signal. As a result, the eye opening is closed due to a process or the like, the test signal cannot be detected, and the determination that the LSI is defective is substantially eliminated. Therefore, an LSI having no defective element in the circuit design or configuration itself is hardly determined as defective at the stage of wafer probing, and the yield can be improved.

  In the digital circuit of the present invention, the adjustment circuit inputs a delay element that gives a predetermined delay time to a pulse signal input from the outside, and an output signal of the delay element as a delay signal, and also inputs a pulse signal. When a delay signal is generated when a pulse signal is generated, a delay setting signal indicating that the delay variation of the data signal is faster than a predetermined time is output, and no delay signal is generated when the pulse signal is generated Includes a data holding circuit that outputs a delay setting signal indicating that the delay variation of the data signal is slower than a predetermined time.

If the digital circuit has such a configuration, it can be determined whether the delay variation of the data signal is faster or slower than a predetermined time. Then, the delay time of the variable delay circuit can be compensated by setting the binary determination result from the outside.
Note that the predetermined multiple includes an integer multiple (for example, 1 ×, 2 ×, 3 ×, etc.), a fractional multiple (for example, 1/2 ×, 1/3 ×, 3/2 ×, etc.), and a fractional multiple. (For example, 0.5 times, 1.5 times, etc.).
The pulse signal indicates a specific waveform of the test signal. However, it will be described as a test signal in [Best Mode for Carrying Out the Invention] described later.

In the digital circuit of the present invention, the delay time of the delay element is a time that is an integral multiple of the cycle of the pulse signal, or a time that is the sum of the integral multiple of the cycle of the pulse signal and the pulse width of the pulse signal. The configuration is as follows.
When the digital circuit has such a configuration, it can be determined whether the delay variation of the data signal is faster or slower than a time that is an integral multiple of the cycle of the test signal.

In the digital circuit of the present invention, the adjusting circuit inputs a pulse signal from one input terminal and sends it to the data holding circuit, and branches from the input terminal or the pulse signal transmission line to delay the pulse signal. And a branch path to be sent to the element.
If the digital circuit has such a configuration, the skew in the path for transmitting the test signal can be reduced.

  The digital circuit of the present invention includes a delay element as a first delay element, and the adjustment circuit includes a second delay circuit that gives a predetermined delay time to a pulse signal input to the data holding circuit. Each delay time difference from the second delay element is an integral multiple of the period of the pulse signal, or the sum of the integral multiple of the period of the pulse signal and the pulse width.

  If the digital circuit has such a configuration, the difference between the delay times of the first delay element and the second delay element is an integral multiple of the test signal period or an integral multiple of the test signal period and the pulse width. Since it is a sum, the data holding circuit determines whether the delay variation of the data signal is fast or slow based on the result of comparing the signal output from the first delay element and the signal output from the second delay element. it can.

  In the digital circuit of the present invention, the adjustment circuit includes a plurality of delay elements each having a different delay time and giving a delay time to an externally input pulse signal, and corresponding to each delay element. When the output signal of the corresponding delay element is input as a delay signal and a pulse signal is input and a delay signal is generated when the pulse signal is generated, the delay variation of the data signal is faster than a predetermined time. A plurality of data that output a first delay setting signal indicating that the delay variation of the data signal is later than a predetermined time when a delay signal is not generated when the pulse signal is generated. The first delay setting signal from the corresponding data holding circuit is inputted and the latch signal inputted from the outside is provided. A plurality of latch circuits that output a first delay setting signal in accordance with the input timing, and a second delay setting signal that is output based on the first delay setting signal output from each latch circuit. And a decoder for setting the delay time of the variable delay circuit.

When the digital circuit has such a configuration, the delay time of the variable delay circuit can be compensated more finely according to the number of delay elements.
For example, when there are three delay elements, four sections (faster than the delay time of the first delay element, slower than the delay time of the first delay element but faster than the delay time of the second delay element, The delay of the variable delay circuit suitable for delay variation can be determined by the delay time of the second delay element, which is slower than the delay time of the second delay element, but faster than the delay time of the third delay element, and later than the delay time of the third delay element. Allow time compensation.

  In the digital circuit of the present invention, the adjustment circuit can set different delay times, and a delay element that gives a delay time to an externally input pulse signal and an output signal of the delay element are input as a delay signal. In addition, when a pulse signal is input and a delay signal is generated when the pulse signal is generated, a first delay setting signal indicating that the delay variation of the data signal is faster than a predetermined time is output, and the pulse signal is generated. Sometimes when no delay signal is generated, it corresponds to the data holding circuit that outputs the first delay setting signal indicating that the delay variation of the data signal is slower than the predetermined time, and the delay time that can be set by the delay element, respectively. The first delay setting signal is input from the data holding circuit, and the first delay setting signal is output according to the input timing of the latch signal input from the outside. Based on a plurality of latch circuits and a first delay setting signal output from each latch circuit, a second delay setting signal is output, and the second delay setting signal is sent to the variable delay circuit to delay the variable delay circuit. The decoder includes a decoder for setting time.

If the digital circuit has such a configuration, the delay time of the variable delay circuit can be compensated more finely according to the number of delay elements.
In addition, the circuit scale can be significantly reduced as compared with the case where a plurality of delay elements are provided.

In the digital circuit of the present invention, the adjustment device includes a rewritable or non-rewritable storage device that holds one or more delay setting times set for the variable delay circuit.
When the digital circuit has such a configuration, the delay time of the variable delay circuit can be set based on the delay setting information held in the storage device.

  A semiconductor device according to the present invention is a semiconductor device on which a digital circuit is mounted, and the digital circuit includes the digital circuit according to any one of claims 1 to 8.

If the semiconductor device has such a configuration, it is possible to suppress delay variation of the output signal of the digital circuit mounted on the semiconductor device.
In particular, the adjustment circuit provided in the digital circuit determines whether the delay variation of the clock signal / data signal of the semiconductor 1 chip is fast or slow with respect to a predetermined time. Based on the determination result, the variable delay circuit Since the delay time is compensated, delay variation using a low-speed general-purpose inspection apparatus can be suppressed.
Furthermore, an eye opening that can be blocked by delay variation between FFs caused by a process or the like is secured in an open state, and a low-speed test of an LSI can be performed using a test signal that has passed through the eye opening. For this reason, an LSI having no defective elements in the circuit design or configuration itself is determined as a non-defective product, so that the yield in wafer probing can be improved.

  The clock adjustment method of the present invention also includes a step (delay variation determining step) of determining a delay variation state of the data signal output from the clock operation circuit in accordance with the input timing of the clock signal, and a result of this determination. And a step of setting a delay time of the variable delay circuit that gives a predetermined delay time to the clock signal (delay time setting step), wherein the delay variation of the data signal output from the clock operation circuit Is a method comprising a step (delay variation determination step) for determining whether the delay time is faster or later than a predetermined time, and a step (delay time setting step) for setting the delay time of the variable delay circuit based on the determination result is there.

  When the clock adjustment method is such a method, it can be determined whether the delay variation of the data signal is faster or slower than the predetermined time, and the delay time of the variable delay circuit can be compensated based on the determination result. Thereby, delay variation can be suppressed, an eye opening of the data signal can be secured, data transfer between the FFs can be ensured, and the yield in wafer probing can be improved.

As described above, according to the present invention, in a digital circuit having one or more clock operation circuits, a variable delay circuit that gives a predetermined delay time to a clock signal and an adjustment that compensates for the delay time of the variable delay circuit A delay time of the delay element included in the adjustment circuit is determined to determine whether the delay variation of the data signal is fast or slow, and based on the determination result Since the delay time of the variable delay circuit is compensated, the variable delay circuit can be automatically adjusted by using a low-speed general-purpose inspection device to compensate for delay variation and enable inspection.
Moreover, since the delay time of the variable delay circuit is compensated using a low-speed general-purpose inspection device, the inspection quality can be improved while realizing cost reduction.
Furthermore, since the eye opening of the data signal is secured by the correction of the variable delay circuit, it is possible to reduce the defect determination due to the process or the like and improve the yield in wafer probing.

  Hereinafter, preferred embodiments of a digital circuit, a semiconductor device, and a clock adjustment method according to the present invention will be described with reference to the drawings.

[First embodiment]
First, a digital circuit, a semiconductor device, and a clock adjustment method according to a first embodiment of the present invention will be described with reference to FIG.
FIG. 2 is a circuit diagram showing the configuration of the digital circuit of this embodiment.
As shown in the figure, the digital circuit 10a of the present embodiment includes clock operation circuits 11-1, 11-2, buffers 12-1, 12-2, variable delay circuits 13-1, 13-2, It has a delay circuit 14a, a data holding circuit 15a, a test signal transmission path 16, and a branch path 17.

The clock operation circuits 11-1 and 11-2 are circuits that perform a predetermined operation based on an input of a clock signal.
Note that the clock operation circuits 11-1 and 11-2 of this embodiment are circuits that input data signals and output the data signals in accordance with the input timing of the clock signals.
The clock operation circuits 11-1 and 11-2 can be composed of, for example, a flip-flop circuit or a latch circuit.

The buffers 12-1 and 12-2 perform logical calculations by an AND circuit / OR circuit, a NOT circuit, and the like during a clock cycle, and input data to the clock operation circuit. When there are few logical calculations, a buffer may be inserted for timing adjustment. The data signal given the delay time is input to the clock operation circuits 11-1 and 11-2.
In FIG. 1, the buffers 12-1 and 12-2 are connected to the path through which the data signal is transmitted. However, the buffers 12-1 and 12-2 are not limited to the path through which the data signal is transmitted, and a clock signal is transmitted. It can also be connected to a route.

The variable delay circuit 13-1 delays the clock signal input to the clock operation circuit 11-1. On the other hand, the variable delay circuit 13-2 delays the clock signal input to the clock operation circuit 11-2.
These variable delay circuits 13-1 and 13-2 can set a delay time based on an external signal. This delay time can be set, for example, by applying a digital data signal or controlling by an analog current amount.
In the variable delay circuits 13-1 and 13-2 of the present embodiment, the delay is set by the delay setting signal from the adjustment circuit (the delay circuit 14a and the data holding circuit 15a). The specific operation of the delay setting by the adjustment circuit will be described in detail in “Operation of the digital circuit of the present embodiment and delay setting of the variable delay circuit” described later.

The delay circuit (delay element) 14a gives a predetermined delay time to TESTCLK (test signal) input from the outside (for example, a low-speed general-purpose inspection device 20 (hereinafter referred to as “inspection device 20” for short)). The data is sent to the data holding circuit 15a.
In this embodiment, the delay circuit 14a can have a period corresponding to the frequency of the output signal (test signal) of the inspection apparatus 20 as a delay time. For example, when the maximum output frequency of the inspection apparatus 20 is 10 MHz, the period of 100 ns is set as the delay time of the delay circuit 14a.

Further, the delay circuit 14a can have a predetermined time as a delay time corresponding to the frequency of the output signal of the inspection apparatus 20 as a delay time. Here, the predetermined multiple may be, for example, 2 times, 3 times, 4 times, 1/2 times, 3/2 times, or the like. The delay time of the delay circuit 14a is, for example, 200 ns (2 times), 300 ns (3 times), 400 ns (4 times), 50 ns (1/2 times) when the maximum output frequency of the inspection apparatus 20 is 10 MHz. ), 150 ns (3/2 times), and the like.
Furthermore, the delay circuit 14a can have, as a delay time, a sum obtained by adding a predetermined time of a period corresponding to the frequency of the output signal of the inspection device 20 and the pulse width of the output signal. For example, when the maximum output frequency of the inspection apparatus 20 is 10 MHz, the period is 100 ns and the pulse width is 50 ns. For this reason, if the predetermined multiple is set to 1, the delay time of the delay circuit 14a is 150 ns.

In FIG. 1, the delay circuit 14a is connected to the data input terminal of the data holding circuit 15a. However, the delay circuit 14a is not limited to the one connected to the data input terminal of the data holding circuit 15a. It may be connected to a clock input terminal. That is, the delay circuit 14a can be connected to one or both of the data input terminal and the clock input terminal of the data holding circuit 15a.
When the delay circuit 14a is connected to both the data input terminal and the clock input terminal of the data holding circuit 15a, the difference between the delay times of the delay circuit 14a is an integer of the frequency input from the inspection device 20. It can be a double or an integer multiple plus the pulse width.

  The data holding circuit 15a inputs a signal from the delay circuit 14a (TESTCLK given a predetermined delay time, a delay signal) at a data input terminal, and inputs TESTCLK at a clock input terminal. Then, a delay setting signal is output according to the input timing of TESTCLK. As described above, the data holding circuit 15a can output the delay setting signal based on the delay signal from the delay circuit 14a and the test signal.

The delay setting signal output from the data holding circuit 15a is sent to the variable delay circuits 13-1 and 13-2. Thereby, the delay time is set in the variable delay circuits 13-1 and 13-2.
The generation of the delay setting signal in the data holding circuit 15a will be described in detail later in “Operation of the digital circuit of the present embodiment and delay setting of the variable delay circuit”.

The data holding circuit 15a can be configured by, for example, a flip-flop or a latch circuit.
In the present embodiment, the delay circuit 14a and the data holding circuit 15a are collectively referred to as an “adjustment circuit”.

  Further, the digital circuit 10a shown in FIG. 1 including this adjustment circuit is entirely mounted on the same LSI. The process, temperature, and voltage that cause the delay variation of the data signals output from the clock operation circuits 11-1 and 11-2 are also the causes of the delay variation of the delay signal output from the delay circuit 14a of the adjustment circuit. Become. For this reason, in the data holding circuit 15a, it is determined whether the generation timing of the delay signal of the delay circuit 14a is early or late with respect to a time that is an integral multiple of the cycle of TESTCLK. It can be considered that it corresponds to the delay variation of the data signal output from.

The test signal transmission path 16 inputs TESTCLK sent from the outside (for example, the inspection apparatus 20) from one input terminal (test signal input terminal 18) and sends it to the data holding circuit 15a.
The branch path 17 branches from the input terminal or the test signal transmission path 16 and sends TESTCLK to the delay circuit 14a.
When the test signal transmission path 16 and the branch path 17 are configured as described above, the path for sending TESTCLK to the data holding circuit 15a and the path for sending the TESTCLK to the delay circuit 14a become the same path halfway. The skew can be reduced as compared with the case where each is provided independently.

In the digital circuit 10a of the present embodiment, a rewritable or non-rewritable storage device (not shown) that holds one or more delay settings for the variable delay circuits 13-1 and 13-2 as delay setting information. Is provided.
This storage device can be composed of, for example, a register (rewritable), a mask chrome (unrewritable), a fuse (set in the inspection process and thereafter non-rewritable), and the like.
By providing this storage device, the delay times of the variable delay circuits 13-1 and 13-2 can be set based on the delay setting information held in this storage device.

If the digital circuit is configured as described above, adjustment setting of the variable delay circuit can be performed only by delay setting by the adjustment circuit, so that only the circuit on the delay setting side is added without modifying the DATA / CLK main path. It is possible to increase the timing margin at the time of inspection by reflecting delay variation.
However, if the operation of the clock operation circuits 11-1 and 11-2 is to be inspected by wafer probing or final test without the adjustment circuit, the variable delay circuits 13-1 and 13-2 are not set appropriately. Then, the output data of the clock operation circuit 11-2 causes a cycle shift for each chip or data loss occurs with respect to the input data of the clock operation circuit 11-1. This is because the digital circuit shown in FIG. 1 cannot operate the variable delay circuit in a fixed state for all the variation states.
However, since the pattern given from the general-purpose inspection apparatus is a fixed pattern, the variable delay circuits 13-1 and 13-2 cannot detect a variation state and set a delay. Therefore, instead of setting a delay from the inspection pattern, delay information (fast / slow) is given from the adjustment circuit, and the clock operation circuits 11-1 and 11-2 are set so that the data always operates in the same cycle. As a result, operation in a fixed pattern becomes possible.

Next, a configuration for implementing the clock adjustment method of this embodiment will be described.
First, a general configuration for performing wafer probing will be described with reference to FIG.

In performing wafer probing, an inspection apparatus 20 and a semiconductor device (DUT) 30 are prepared as shown in FIG.
The inspection apparatus 20 is a low-speed general-purpose inspection apparatus, and sends a DR signal (DR (DRIVER) waveform) to the DUT 30 in order to inspect the electrical characteristics of the digital circuit mounted on the DUT 30.
The DUT 30 is equipped with a digital circuit having a plurality of clock operation circuits.

Then, the DATA signal and the CLK signal (DR waveform) are input from the inspection device 20 to the DATA input and the CLK input of the digital circuit 10a mounted on the DUT 30 at a predetermined timing. An output signal is output from the digital circuit 10a.
The inspection apparatus 20 receives an output signal from the DUT 30 and determines whether the electrical characteristics of the digital circuit mounted on the DUT 30 are good or bad based on the signal waveform (output waveform) of the output signal.

Here, since the delay variation of the data signal is large and the eye opening cannot be sufficiently secured, the data transfer in the clock operation circuits 11-1 and 11-2 is hindered. As a result, the data necessary for determining the quality of the DUT 30 When a signal cannot be obtained, it is necessary to reduce the delay variation and increase the timing margin.
That is, with respect to the data signal, as shown in FIG. 3, it is necessary to secure a constant and sufficient setup margin and hold margin. However, when the delay variation becomes large, the setup margin cannot be sufficiently secured, and the clock operation circuit Data transfer between 11-1 and 11-2 becomes impossible.
Therefore, by installing a digital circuit having an adjustment circuit as shown in FIG. 1 in the semiconductor device 30, the delay time of the variable delay circuits 13-1 and 13-2 is set, and the delay variation of the data signal is compensated. To do.

  That is, with the configuration shown in FIG. 2, TESTCLK is input from the inspection apparatus 20 to the test signal input terminal 18 in the digital circuit 10 a mounted on the semiconductor device 30. Then, the delay time of the variable delay circuits 13-1 and 13-2 is set by the procedure described in the following “about the clock adjustment method of the digital circuit of the present embodiment” to compensate for the delay variation of the data signal.

Next, the clock adjustment method of the digital circuit of this embodiment will be described with reference to FIGS.
FIG. 4 is a flowchart showing a procedure of the clock adjustment method, and FIG. 5 is a signal (data input signal (DATA input) of the data holding circuit 15a) and clock input of the data holding circuit 15a obtained when the clock adjustment method is executed. It is a wave form diagram which shows each waveform of a signal (CLK input) and the output signal (output) of the data holding circuit 15a.

Note that the delay variation of the data signal is caused by the influence of the process, temperature, voltage and the like. Therefore, it is desirable to inspect a plurality of temperatures and voltages and appropriately set the delay times of the variable delay circuits 13-1 and 13-2.
For example, when the voltage setting of the digital circuit 10a is 5V, for example, the inspection is performed for 4.5V and 5.5V. In this way, even if delay variation occurs due to voltage fluctuation, the eye opening of the data signal is secured within the range of 4.5 V to 5.5 V, and wafer probing inspection can be performed.

Therefore, in this embodiment, the voltage setting L and the voltage setting H are inspected.
First, the voltage setting L is inspected.
When the voltage setting L is set (step 10), after WAIT TIME (step 11), two TESTCLKs are input from the inspection apparatus 20 to the test signal input terminal 18 (step 12).
In WAIT TIME (step 13), a predetermined delay time is given to TESTCLK by the delay circuit 14a and sent to the data holding circuit 15a as a delay signal. In the data holding circuit 15a, TESTCLK is input (CLK input, FIGS. 5 (a) (ii), (b) (ii)), and a delay signal is input from the delay circuit 14a (DATA input, FIG. 5 (a)). (I), (b) (i)), based on the result of comparing these TESTCLK and the delay signal, a delay setting signal is output (output, FIG. 5 (a) (iii), (b) (iii) ) And sent to the variable delay circuits 13-1 and 13-2 (delay variation determination step). In response to this delay setting signal, the delay times of the variable delay circuits 13-1 and 13-2 are set (delay variation determining step, step 14).
Thereafter, the DUT 30 is inspected by giving an inspection pattern to the DUT 30 (step 15).

Subsequently, the voltage setting H is inspected. In the voltage setting H, the delay variation is different from that in the voltage setting L. Therefore, it is necessary to reset the adjustment circuit.
When the voltage setting H is set (step 16), thereafter, the inspection is performed in the same procedure as the inspection for the voltage setting L (step 17 to step 21). Thereby, the delay time of the variable delay circuits 13-1 and 13-2 is set.
By such a procedure, an appropriate delay time is set in the variable delay circuits 13-1 and 13-2.

Next, the operation of the digital circuit of this embodiment and the delay setting of the variable delay circuit will be described with reference to FIG.
First, the case where the delay variation is FAST will be described with reference to FIG.
As shown in FIG. 5A, the waveforms of the DATA input, CLK input, and output in the data holding circuit 15a are seen.
For example, when the CLK input has a period of 100 ns and the time difference Tpd between the DATA input and the CLK input is smaller than 100 ns (Tpd <100 ns, FIGS. Since a DATA input is sometimes input, a signal (a signal indicating “1”) as shown in FIGS. 9A and 9C is output from the output of the digital circuit 10a.
At this time, “delay FAST” is set in the variable delay circuits 13-1 and 13-2 (FIG. 5A, “1: delay FAST” in FIG. 1).

Next, the case where the delay variation is SLOW will be described with reference to FIG.
As shown in FIG. 5B, the waveforms of data input (DATA input), clock input (CLK input), and output in the data holding circuit 15a are observed.
For example, when the CLK signal has a period of 100 ns and the time difference Tpd between the DATA signal and the CLK signal is larger than 100 ns (Tpd> 100 ns, (b) (i), (ii) in the figure), the rising edge of the CLK signal Since the DATA signal is not input sometimes, the signal is not output from the output OUT of the digital circuit ((b) (iii) in the figure, a signal indicating “0” is output).
At this time, “delay SLOW” is set in the variable delay circuits 13-1 and 13-2 (FIG. 5B, “2: delay SLOW”).

By causing the digital circuit of this embodiment to execute such an operation, the delay setting for the variable delay circuit can be set in two types, FAST and SLOW.
According to such a method, it is only necessary to set either FAST or SLOW, so that the setting time can be shortened.

There are three possible methods for discriminating whether the delay is fast or slow.
As a first method, there is a method of distinguishing by a frequency input from the inspection apparatus 20.
As a second method, a delay time that is an integral multiple of the period of the signal (TESTCLK) input from the inspection device 20 is used as the delay time of the delay circuit 14a, and the delay time of the delay circuit 14a and the input signal from the inspection device 20 There is a method of comparing a period that is an integer multiple of (TESTCLK).
As a third method, a delay time that is the sum of the integral multiple of the frequency of the signal (TESTCLK) input from the inspection apparatus 20 and the pulse width of the input signal is set as the delay time of the delay circuit 14a, and the delay circuit 14a. Is compared with a multiple of the period of the input signal (TESTCLK) of the inspection apparatus 20 and the pulse width.

Further, in the data holding circuit 15a, the delay variation determination can be made different by comparison between when the delay variation is the fastest and when the delay variation is the slowest.
That is, when the delay variation of the data signal is the fastest, it can be determined that the delay variation is faster than the predetermined time, and when the delay variation is the slowest, it can be determined that the delay variation is later than the predetermined time. Also in this case, the delay time of the variable delay circuit can be compensated based on the determination results.

Furthermore, in the data holding circuit 15a, when the delay variation continuously changes from the fastest to the slowest, it is possible to detect the delay variation state that is determined differently by comparison.
That is, when the delay variation of the data signal continuously changes from the fastest to the slowest, if the delay variation is close to the fastest, it is determined that the delay variation is faster than a predetermined time, and the delay variation is the slowest. When it is close, it can be determined that the delay variation is later than the predetermined time. Also in this case, the delay time of the variable delay circuit can be compensated based on the determination results.

As described above, according to the digital circuit, the semiconductor device, and the clock adjustment method described above, it is determined whether the delay variation of the data signal is faster or slower than the predetermined time, and the delay time of the variable delay circuit is determined based on the determination result. Can compensate.
Therefore, it is possible to provide a clock adjustment method suitable for a low-speed general-purpose inspection apparatus. As a result, the clock operation circuit can be inspected before mounting, so that unnecessary packaging and mounting can be prevented in advance, and it is possible to determine the defect of the LSI in wafer probing. Can be prevented from occurring and the inspection quality can be improved.
In addition, by compensating the delay amount of the variable delay circuit, an eye opening that can be blocked due to a process or the like can be secured, and the test signal can be passed. As a result, an LSI that has been considered defective due to a process or the like although there is no problem in circuit design or configuration can be determined as a non-defective product, and can be shipped as a product after initialization. Therefore, the yield in wafer probing can be improved.

[Second Embodiment]
Next, a second embodiment of the digital circuit, semiconductor device, and clock adjustment method of the present invention will be described with reference to FIG.
FIG. 2 is a circuit diagram showing the configuration of the digital circuit of this embodiment.
This embodiment is different from the first embodiment in that a plurality of delay circuits, data holding circuits, and latch circuits are provided so that delay variation can be determined and delay time can be compensated more finely.
Therefore, in FIG. 6, the same components as those in FIG. 1 are denoted by the same reference numerals, and detailed description thereof is omitted.

  As shown in FIG. 6, the digital circuit 10b of this embodiment includes clock operation circuits 11-1 and 11-2, buffers 12-1 and 12-2, variable delay circuits 13-1 and 13-2, Delay circuits 14b-1 to 14b-3, flip-flops 15b-1 to 15b-3, latch circuits 18b-1 to 18b-3, and a decoder (DECODER) 19 are provided.

Here, the delay circuits 14b-1 to 14b-3 have different delay times. For example, as shown in FIG. 6, the first delay circuit 14b-1 may have a delay time of 80ns, the second delay circuit 14b-2 may have a delay time of 100ns, and the third delay circuit 14b-3 may have a delay time of 120ns.
In the present embodiment, three delay circuits 14b are provided. However, the number of delay circuits 14b is not limited to three, and may be two or four or more.

The flip-flops 15b-1 to 15b-3 are provided corresponding to the respective delay circuits 14b-1 to 14b-3, and the output signals of the corresponding delay circuits 14b-1 to 14b-3 are used as delay signals. Input and output the delayed signal according to the input timing of the test signal.
Since the flip-flops 15b-1 to 15b-3 are provided one-to-one with the delay circuits 14b-1 to 14b-3, the number of the flip-flops 15b-1 to 15b-3 is the same as that of the delay circuits 14b-1 to 14b-3.

The latch circuits 18b-1 to 18b-3 are provided corresponding to the respective flip-flops 15b-1 to 15b-3, and input the delay signals from the corresponding flip-flops 15b-1 to 15b-3. The delay signal is output according to the input timing of the LATCH signal.
Since the latch circuits 18b-1 to 18b-3 are provided one-to-one with the flip-flops 15b-1 to 15b-3 (or the delay circuits 14b-1 to 14b-3), the flip-flops 15b-1 to 15b- 3 (or delay circuits 14b-1 to 14b-3).

The latch circuits 18b-1 to 18b-3 are provided when TESTCLK is continuously input.
In the first embodiment, two TESTCLKs are input as shown in FIG. For this reason, the correspondence between each waveform of the DATA input and the CLK input is clear.
On the other hand, in this embodiment, since TESTCLK is continuously input, it is necessary to fix the waveform by a latch circuit. Thereby, the correspondence between the waveforms of the DATA input and the CLK input is clarified, and the time difference between them can be obtained.

The decoder 19 receives output signals from the latch circuits 18b-1 to 18b-3, and performs delay settings for the variable delay circuits 13-1 and 13-2 based on the output signals.
In this embodiment, the delay setting can be set in four stages because three delay circuits 14b-1 to 14b-3 are provided.
That is, (1) setting when the delay variation of the data signal is faster than the first delay circuit 14b-1, and (2) the delay variation of the data signal is slower than the first delay circuit 14b-1, but the second delay circuit 14b. -3, setting when faster than -2, (3) setting when delay variation of data signal is slower than second delay circuit 14b-2 but faster than third delay circuit 14b-3, (4) delay of data signal This is a setting when the variation is slower than that of the third delay circuit 14b-1.
Therefore, an appropriate delay setting can be performed for the variable delay circuits 13-1 and 13-2 depending on the degree of delay variation.

Note that the digital circuit 10b of this embodiment can also be mounted on the semiconductor device 30 in the same manner as the digital circuit 10a of the first embodiment.
Further, the clock adjustment method performed in the configuration shown in FIG. 2 using the digital circuit 10b of this embodiment can be performed in the same steps (steps shown in FIG. 4) as the clock adjustment method in the first embodiment. A result similar to that of FIG. 5 is obtained. Therefore, also in this embodiment, the adjustment circuit can determine whether the delay variation of the data signal is faster or slower than the predetermined time, and based on this determination result, the delay time of the variable delay circuits 13-1 and 13-2. And delay variation can be suppressed.

  As described above, according to the digital circuit, the semiconductor device, and the clock adjustment method of the present embodiment, with a simple configuration such as an adjustment circuit, a method suitable for a low-speed general-purpose inspection apparatus in wafer probing can be used. Since defective products can be detected, the cost can be reduced compared to the conventional clock adjustment method, and the inspection quality and product yield can be improved.

[Third embodiment]
Next, a third embodiment of the digital circuit, semiconductor device, and clock adjustment method of the present invention will be described with reference to FIG.
FIG. 2 is a circuit diagram showing the configuration of the digital circuit of this embodiment.
This embodiment is different from the first embodiment in the configuration of the adjustment circuit. That is, in the first embodiment, the adjustment circuit includes a delay circuit having a predetermined delay time, and one data holding circuit that inputs a signal output from the delay circuit and outputs the signal according to the input timing of the test signal. In this embodiment, the adjustment circuit includes a plurality of data holding circuits and a plurality of latch circuits, and each data holding circuit extracts a predetermined delay time from the delay circuit group and is delayed thereby. The test signal is input. Other components are the same as those in the first embodiment.
Therefore, in FIG. 7, the same components as those in FIG. 1 are denoted by the same reference numerals, and detailed description thereof is omitted.

  As shown in FIG. 7, the digital circuit 10c of this embodiment includes clock operation circuits 11-1, 11-2, buffers 12-1, 12-2, variable delay circuits 13-1, 13-2, The circuit includes a delay circuit group 14c, data holding circuits 15c-1 to 15c-3, latch circuits 18c-1 to 18c-3, and a decoder (DECODER) 19.

Here, the delay circuit group 14c can be configured to have, for example, cascade connection of delay circuits. Thereby, the delay time according to the cut-out position can be obtained. For example, as shown in FIG. 7, delay times of 80 ns (first setting), 100 ns (second setting), and 120 ns (third setting) can be obtained according to the cutout position.
The data holding circuits 15c-1 to 15c-3 input a signal given a delay time corresponding to the cut-out position of the delay circuit group 14c as a delay signal, and output the delay signal according to the input timing of the test signal To do.
For example, a delay signal having a delay time of 80 ns is input to the data holding circuit 15c-1, and a delay signal having a delay time of 100ns is input to the data holding circuit 15c-2. -2 is input with a delay signal having a delay time of 120 ns.

The latch circuits 18c-1 to 18c-3 receive the delay signal from the data holding circuits 15c-1 to 15c-3, and output the delay signal according to the input timing of the LATCH signal.
The decoder 19 receives output signals from the latch circuits 18c-1 to 18c-3, and performs delay setting for the variable delay circuits 13-1 and 13-2 based on the output signals.

In this embodiment, the delay setting can be set in four stages since the delay time of the delay circuit group 14c can be set in three stages.
(1) Setting when data signal delay variation is faster than the first setting, (2) Setting when data signal delay variation is slower than the first setting but faster than the second setting, (3) This is a setting when the data signal delay variation is slower than the second setting but faster than the third setting, and (4) a setting when the data signal delay variation is slower than the third setting.
Therefore, an appropriate delay setting can be performed for the variable delay circuits 13-1 and 13-2 depending on the degree of delay variation.

Note that the digital circuit 10c of this embodiment can also be mounted on the semiconductor device 30 in the same manner as the digital circuit 10a of the first embodiment.
Further, the clock adjustment method performed in the configuration shown in FIG. 2 using the digital circuit 10c of this embodiment can be performed in the same steps (steps shown in FIG. 4) as the clock adjustment method in the first embodiment. A result similar to that of FIG. 5 is obtained. Therefore, also in this embodiment, the adjustment circuit can determine whether the delay variation of the data signal is faster or slower than the predetermined time, and based on this determination result, the delay time of the variable delay circuits 13-1 and 13-2. And delay variation can be suppressed.

As described above, according to the digital circuit, the semiconductor device, and the clock adjustment method of the present embodiment, with a simple configuration such as an adjustment circuit, a method suitable for a low-speed general-purpose inspection apparatus in wafer probing can be used. Since defective products can be detected, the cost can be reduced as compared with the conventional clock adjustment method, and the inspection quality can be improved.
Further, since the eye opening of the data signal is ensured by correcting the delay amount of the variable delay circuit, it is possible to reduce the defect determination due to the process or the like and improve the yield in wafer probing.

The preferred embodiments of the digital circuit, semiconductor device, and clock adjustment method of the present invention have been described above. However, the digital circuit, semiconductor device, and clock adjustment method of the present invention are not limited to the above-described embodiments, It goes without saying that various modifications can be made within the scope of the present invention.
For example, in the above-described embodiment, the TESTCLK frequency of the low-speed general-purpose inspection apparatus is 10 MHz and the delay time of the delay circuit 14 is 100 ns (and 80 ns, 120 ns), but the delay time of the delay circuit 14 is limited to 100 ns or the like. Instead, it can be a predetermined multiple of the cycle of the test signal (for example, 50 ns, 150 ns, 200 ns, etc.).

In each embodiment, two clock operation circuits, buffers, and variable delay circuits are provided. However, the number of clock operation circuits and the like is not limited to two, and any number may be provided. it can. In this case, the delay setting by the adjustment circuit is performed for each variable delay circuit.
Furthermore, the present invention provides an inspection method suitable for a low-speed general-purpose inspection apparatus used in wafer probing, but is not limited to wafer probing, and can be implemented in a final test.

  The digital circuit, semiconductor device, and clock adjustment method of the present invention are an arbitrary combination of the digital circuit, semiconductor device, and clock adjustment method in each of the first embodiment, the second embodiment, and the third embodiment. May be.

  The present invention is an invention for compensating for delay variation between clock operation circuits of a digital circuit mounted on an LSI, and thus can be used for an inspection apparatus and a clock adjustment method for compensating for delay variation between clock operation circuits. is there.

It is a circuit diagram which shows the structure of the digital circuit in 1st embodiment of this invention. It is a block diagram which shows the structure for implementing the clock adjustment method in 1st embodiment of this invention. It is a wave form diagram for demonstrating the delay dispersion | variation of a data signal. It is a flowchart which shows the procedure of the clock adjustment method in 1st embodiment of this invention. It is a timing chart which shows a time-dependent change of each waveform when the clock adjustment method in 1st embodiment of this invention is implemented. It is a circuit diagram which shows the structure of the digital circuit in 2nd embodiment of this invention. It is a circuit diagram which shows the structure of the digital circuit in 3rd embodiment of this invention. It is a block diagram which shows the manufacturing process of LSI. It is a circuit diagram which shows the structure of the conventional digital circuit which compensates the delay dispersion | variation between flip-flops.

Explanation of symbols

10a, 10b, 10c Digital circuit 11-1, 11-2 Clock operation circuit 12-1, 12-2 Buffer 13-1, 13-2 Variable delay circuit 14a, 14b Delay circuit 14c Delay circuit group 15a, 15b-1 15b-3, 15c-1 to 15c-3 Data holding circuit 16 Test signal transmission path 17 Branch path 18b-1 to 18b-3, 18c-1 to 18c-3 Latch circuit 19 Decoder 20 Semiconductor device 30 Inspection device (low speed General purpose inspection equipment)

Claims (10)

One or more clock operation circuits for inputting a data signal and outputting the data signal in accordance with the input timing of the clock signal;
A digital circuit comprising a variable delay circuit for giving a predetermined delay time to the clock signal and / or the data signal,
Output a delay setting signal having different values when the delay variation of the data signal output from the clock operation circuit is faster and slower than a predetermined time, and send the delay setting signal to the variable delay circuit. A digital circuit comprising an adjustment circuit for setting a delay time of a variable delay circuit to a different time. The adjustment circuit is
A delay element that gives a predetermined delay time to an externally input pulse signal;
When the output signal of the delay element is input as a delay signal, the pulse signal is input, and the delay signal is generated when another period of the pulse signal is generated, the delay variation of the data signal is a predetermined time. A delay setting signal indicating that the delay variation of the data signal is later than a predetermined time when the delay signal is not generated when another period of the pulse signal is generated. The digital circuit according to claim 1, further comprising a data holding circuit that outputs a signal. The delay time of the delay element is
3. The digital circuit according to claim 2, wherein the time is an integral multiple of the period of the pulse signal or a sum of an integral multiple of the period of the pulse signal and the pulse width of the pulse signal. . The adjustment circuit is
A pulse signal transmission path for inputting the pulse signal from one input terminal and sending the pulse signal to the data holding circuit;
The digital circuit according to claim 2, further comprising: a branch path that branches from the input terminal or the pulse signal transmission path and sends the pulse signal to the delay element. The delay element is a first delay element,
The adjustment circuit includes a second delay circuit that gives a predetermined delay time to the pulse signal input to the data holding circuit;
The difference in delay time between the first delay element and the second delay element is an integral multiple of the cycle of the pulse signal, or the sum of an integral multiple of the cycle of the pulse signal and the pulse width. The digital circuit according to claim 2. The adjustment circuit is
A plurality of delay elements each having a different delay time and giving the delay time to an externally input pulse signal;
Each delay element is provided correspondingly, and an input signal of the corresponding delay element is input as a delay signal, and the pulse signal is input, and when the delay signal is generated when the pulse signal is generated, A first delay setting signal indicating that the delay variation of the data signal is faster than a predetermined time is output, and when the delay signal is not generated when the pulse signal is generated, the delay variation of the data signal is a predetermined time. A plurality of data holding circuits for outputting a first delay setting signal indicating slower than,
The first delay setting signal is provided corresponding to each data holding circuit, receives the first delay setting signal from the corresponding data holding circuit, and outputs the first delay setting signal according to the input timing of the latch signal input from the outside. A plurality of latch circuits;
A second delay setting signal is output based on the first delay setting signal output from each latch circuit, and the second delay setting signal is sent to the variable delay circuit to set the delay time of the variable delay circuit. The digital circuit according to claim 1, further comprising a decoder. The adjustment circuit is
A delay element that enables setting of different delay times and gives the delay time to an externally input pulse signal;
An output signal of the delay element is input as a delay signal, and when the pulse signal is input and the delay signal is generated when the pulse signal is generated, delay variation of the data signal is faster than a predetermined time. A first delay setting signal indicating that the delay variation of the data signal is later than a predetermined time when the delay signal is not generated when the pulse signal is generated. A data holding circuit to output,
The first delay setting signal corresponding to the delay time that can be set by the delay element is input, the first delay setting signal from the data holding circuit is input, and the first delay setting is performed according to the input timing of the latch signal input from the outside A plurality of latch circuits for outputting signals;
A second delay setting signal is output based on the first delay setting signal output from each latch circuit, and the second delay setting signal is sent to the variable delay circuit to set the delay time of the variable delay circuit. The digital circuit according to claim 1, further comprising a decoder. The adjusting device is
The digital circuit according to any one of claims 1 to 7, further comprising a rewritable or non-rewritable storage device that holds one or more delay setting times set for the variable delay circuit. . A semiconductor device equipped with a digital circuit,
The said digital circuit contains the digital circuit in any one of Claims 1-8. The semiconductor device characterized by the above-mentioned. A step of determining a delay variation state of the data signal output from the clock operation circuit in accordance with an input timing of the clock signal, and a variable delay circuit for giving a predetermined delay time to the clock signal based on a result of the determination A clock adjusting method including a step of setting a delay time,
Determining whether the delay variation of the data signal output from the clock operation circuit is faster or slower than a predetermined time;
A clock adjustment method comprising: setting a delay time of the variable delay circuit based on the result of the determination.

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