WO2011023030A1

WO2011023030A1 - Integrated circuit and method for acquiring reference clock in integrated circuit

Info

Publication number: WO2011023030A1
Application number: PCT/CN2010/074530
Authority: WO
Inventors: 王惠刚
Original assignee: 炬力集成电路设计有限公司
Priority date: 2009-08-28
Filing date: 2010-06-25
Publication date: 2011-03-03
Also published as: CN102006056A

Abstract

An integrated circuit is disclosed in present invention, which includes: a first frequency division unit, a counter, an oscillation signal generation circuit and a second frequency division unit; wherein: the first frequency division unit is used for dividing the frequency of an external clock signal from exterior of the integrated circuit to acquire a first reference clock; the oscillation signal generation circuit is used for generating the oscillation signal; the counter is used for taking count of the oscillation signal using the first reference clock to acquire frequency information of the oscillation signal; and, the second frequency division unit is used for dividing the frequency of the oscillation signal according to a frequency division factor obtained on the basis of the frequency information to acquire a second reference clock. A method for acquiring a reference clock in the integrated circuit is also disclosed in the invention. The solution of the invention can acquire an accurate reference clock under the condition of without a low-frequency crystal oscillator, and save precious pin resources.

Description

Integrated circuit and method for obtaining a reference clock in an integrated circuit

Technical field

The present invention relates to the field of integrated circuit technology, and more particularly to an integrated circuit and a method of obtaining a reference clock in an integrated circuit. Background of the invention

In the design and application of the existing System-On-a-Chip (SOC), it is generally required to use two crystal oscillators as the clock source of the SOC, and one is the high-frequency crystal oscillation with an oscillation frequency of several tens of megahertz. The other is a low frequency crystal oscillator with an oscillation frequency of several tens of kilohertz. 1 is a schematic block diagram of a clock device of a prior art system in the prior art. As shown in FIG. 1, the high frequency crystal oscillator 12 is used as a clock source of a phase-locked loop (PLL) group 111 in the SOC 11, and generates high voltages required for various high frequency circuits in the SOC 11. Frequency clock. The low frequency crystal oscillator 13 has two main purposes: one is to generate an operating clock when the SOC 11 is in standby; the other is used as a clock source of the low frequency frequency divider 112 in the SOC 11 to generate a precision timing circuit. The timing reference clock is typically a clock with a frequency of 1 Hz. The precision timing circuit in the SOC is mainly used to implement timing functions in seconds, such as perpetual calendar and Digital Right Management (DRM).

Although the reference clock required for accurate timing can be generated by frequency division of the high-frequency crystal oscillator, the power consumption of the SOC in the standby state is unacceptable due to the large current during oscillation of the high-frequency crystal oscillator. Therefore, in the existing SOC, a lower power crystal oscillator with lower power consumption is generally used to generate a reference clock required for precise timing.

The disadvantage of the prior art is that the SOC not only needs to be equipped with two pins for the high frequency crystal oscillator, but also has two pins for the low frequency crystal oscillator, which leads to the most rare in the SOC. Lack of resources - pins, more intense, scarce. Moreover, because the Bill of Material (BOM) of the SOC application product needs to increase the resistance and capacitance required for the low-frequency crystal oscillator and its application circuit, thereby increasing the BOM cost of the SOC application product and reducing the market competitiveness of the SOC. Summary of the invention

The present invention proposes an integrated circuit and a method of obtaining a reference clock in an integrated circuit to conserve resources of the integrated circuit.

An integrated circuit according to an embodiment of the present invention includes: a first frequency dividing unit, a counter, an oscillating signal generating circuit, and a second frequency dividing unit; wherein:

The first frequency dividing unit is configured to obtain a first reference clock by dividing an external clock signal from outside the integrated circuit;

The oscillation signal generating circuit is configured to generate an oscillating signal;

The counter is configured to obtain frequency information of the oscillating signal by counting the oscillating signal by using the first reference clock; and

The second frequency dividing unit is configured to divide the oscillating signal according to a frequency dividing factor obtained according to the frequency information to obtain a second reference clock. The embodiment of the invention further provides a method for obtaining a reference clock in an integrated circuit, the method comprising:

A first reference clock is obtained by dividing an external clock signal from outside the integrated circuit;

Generating an oscillating signal;

Frequency information of the oscillating signal is obtained by counting the oscillating signal by using the first reference clock; and And dividing the oscillating signal according to a frequency dividing factor obtained according to the frequency information to obtain a second reference clock. It can be seen from the above technical solution that the embodiment of the present invention can obtain a precise reference clock without requiring a low-frequency crystal oscillator, so that the two pins of the low-frequency crystal oscillator need not be connected on the integrated circuit, thereby saving Valuable pin resources. BRIEF DESCRIPTION OF THE DRAWINGS

1 is a schematic block diagram of a clock device of a system on chip in the prior art;

2 is a block diagram of a system on chip using the solution of the present invention;

3 is a block diagram of an implementation of a reference clock generating apparatus according to an embodiment of the present invention; FIG. 4 is a block diagram of another implementation of a reference clock generating apparatus according to an embodiment of the present invention; FIG. a processing flowchart for generating a reference clock by the device; and,

FIG. 6 is a flowchart of implementing a reference clock according to an embodiment of the present invention.

Further details are described below in conjunction with the embodiments and the accompanying drawings. Mode for carrying out the invention

The present invention will be further described in detail below with reference to the drawings and embodiments.

2 shows a block diagram of a system on a chip employing an embodiment of the present invention. As can be seen from FIG. 2, the low frequency crystal oscillator is no longer required at the periphery of the SOC 21, but the reference clock generating means 212 in the system on chip generates a reference clock signal in accordance with the high frequency clock signal from the high frequency crystal oscillator 22. And once the reference clock signal can be output, the reference clock generating means 212 can generate a stable reference clock signal by itself without relying on the high frequency clock signal. The low power requirement of the soc in the standby state.

An integrated circuit according to the first embodiment of the present invention includes: a first frequency dividing unit, a counter, an oscillating signal generating circuit, and a second frequency dividing unit; wherein:

The first frequency dividing unit is configured to obtain a first reference clock by dividing an external clock signal input from the external circuit;

The oscillating signal generating circuit is configured to generate an oscillating signal;

The counter is configured to obtain the frequency information of the oscillating signal by counting the oscillating signal by using the first reference clock; wherein the frequency information may be a frequency value of the oscillating signal, or any one of the oscillating signal frequency values Frequency or multiplier value, etc. The method for counting the oscillating signal by using the first reference clock to obtain the frequency information of the oscillating signal may be, for example, after the first frequency dividing unit obtains the first reference clock of 0.5 Hz, and is at the first reference. The oscillation signal is counted during the period corresponding to the high level or low level portion of one cycle of the clock (the duration is 1 second), thereby obtaining the frequency value of the oscillating signal; it can be understood that there may be more in the specific implementation. The implementation manner is not limited thereto. For example, the oscillating signal is counted in one cycle of the first reference clock to obtain a double frequency value of the oscillating signal, etc., and the first obtained by the first frequency dividing unit is obtained. The reference clock is also not limited to 0.5 Hz.

The second frequency dividing unit is configured to divide the oscillating signal according to the frequency dividing factor obtained according to the frequency information to obtain a second reference clock; wherein the frequency dividing factor obtained according to the frequency information may be the frequency information itself, or Any frequency value or multiplication value of the frequency information. Specifically, the second frequency dividing unit may include a frequency divider.

Specifically, the first frequency dividing unit may include a first frequency divider and a second frequency divider; wherein the first frequency divider is configured to use the first clock input from the outside of the integrated circuit by using a frequency dividing factor (ie: The aforementioned external clock signal is divided to obtain a clock signal; the second frequency divider is configured to obtain a first reference by dividing a clock signal obtained by the first frequency divider by two. Clock signal.

Optionally, the first frequency dividing unit may further include a frequency divider, configured to divide the first clock input from the external circuit by using a frequency dividing factor to obtain a first reference clock. .

Specifically, the integrated circuit may further include a control unit, configured to control the first frequency dividing unit, the counter, and any one of the devices external to the integrated circuit for generating the first clock after the counter obtains the counting result. Or any combination into a non-working state. Here, the device for generating the first clock may be referred to as a clock generating unit for generating an external clock signal. This can save power consumption; and after that, the second frequency dividing unit can still divide the oscillating signal according to the counting result to obtain the second reference clock.

Specifically, the integrated circuit further includes: an automatic calibration unit for controlling the first frequency dividing unit, the counter, and the device for generating the first clock to enter an operating state according to a predetermined calibration interval time.

The first clock may be a high frequency clock, and the oscillating signal may be a low frequency oscillating signal.

The frequency dividing factor for dividing the first clock may be the nominal frequency of the first clock or the frequency dividing frequency or frequency multiplication frequency of the nominal frequency.

3 is a block diagram showing an implementation of a reference clock generating device 212 in a system-on-chip according to a second embodiment of the present invention, including a first frequency divider 31, a second frequency divider 32, a counter 33, a low frequency RC oscillator 34, and The third frequency divider 35.

After receiving the start signal, the first frequency divider 31 divides the high frequency clock (which may be a high frequency crystal oscillation clock generated by a high frequency crystal oscillator, which is called a high frequency crystal oscillator clock) input from the outside of the integrated circuit. , produces a 1 Hz clock. The input of the first frequency divider 31 includes a start signal, a first frequency dividing factor, and a high frequency clock input from the outside of the integrated circuit, and outputs a clock signal having a frequency of 1 Hz. The first frequency dividing factor is a constant, and the value is a high frequency crystal oscillator The frequency of the high frequency clock generated by the sigma, that is, the nominal frequency of the high frequency crystal oscillator.

The input of the second frequency divider 32 includes a start signal and a 1 Hz clock generated by the first frequency divider 31, and an output duty cycle of 1, a first reference clock signal having a frequency of 0.5 Hz. The division factor of the second frequency divider 32 is referred to as a second frequency division factor, and its value is 2. In a specific embodiment, the second frequency divider 32 can be implemented by a divide-by-2 circuit, for example, "T. "Type edge triggers are implemented.

It can be understood that, in a further embodiment of the present invention, the first reference clock signal can also be generated by a frequency divider that uses a nominal frequency of twice the high frequency crystal oscillator as a frequency division factor pair. The high frequency clock input from the outside of the integrated circuit is divided, and the first reference clock of 0.5 Hz with a duty ratio of 1 can also be output.

The input of the counter 33 includes an enable signal, a 0.5 Hz clock signal generated by the second frequency divider 32, and a low frequency oscillation clock generated by the low frequency RC oscillator 34, and the output is a count completion signal fed back to the SOC and sent to the third frequency divider 35. Frequency information (such as the third division factor in Figure 3). The counter 33 obtains the frequency information of the low frequency oscillation by counting the oscillation signal using the first reference clock, and inputs the frequency information of the low frequency oscillation clock to the third frequency divider 35. One of the operating modes of the counter 33 is: after receiving the start signal, the low frequency oscillation clock generated by the low frequency RC oscillator 34 is counted at a high level portion of one cycle of the first reference clock, and the counting is completed after the counting is completed. Signal, and save the count results.

The following is a circuit implementation of a counter 33 designed using Verilog hardware description language, where rst_n is the enable signal, clk_i is the low frequency oscillation clock generated by the low frequency RC oscillator 34, and enable is the frequency generated by the second frequency divider 32. Hertz clock signal.

Module counter (rst_n, clk_i, enable, finish, result);

Parameter WIDTH = 10;

Parameter UDLY = 1;

Input rst_n;

Input clk_i; Input enable;

Output finish;

Output [WIDTH- 1:0] result; reg [1 :0] enable_p;

Always @ (posedge clk_i or negedge rst_n)

Begin

If (rst_n == 1'bO)

Enable_p <= #UDLY 2'bOO;

Else

Enable_p <= #UDLY {enable_p[0], enable};

End

Reg finish;

Always @ (posedge clk_i or negedge rst_n)

Begin

If (rst_n == 1'bO)

Finish <= #UDLY l'b0;

Else if (enable_p == 2'blO)

Finish <= #UDLY l'bl;

End reg [WIDTH:0] pointer;

Always @ (posedge clk_i or negedge rst_n)

Begin

If (rst_n == 1'bO)

Pointer <= #UDLY 'h0;

Else if (enable_p[0] == l'bl)

Pointer <= #UDLY pointer + l'bl;

Else

Pointer <= #UDLY 'h0;

End

Reg [WIDTH- 1:0] result;

Always @ (posedge clk_i or negedge rst_n)

Begin

If (rst_n == 1'bO)

Result <= #UDLY 'h02;

Else if (enable_p == 2'blO)

Result <= #UDLY pointer;

End

Endmodule II counter

The circuit implementation shown above is only one possible implementation of the counter 33 in the solution of the present invention and is not intended to limit the present invention.

The low frequency RC oscillator 34 produces a low frequency oscillation clock, where R represents the resistance and C represents the capacitance. The low frequency oscillation clock can be used as an operating clock for SOC standby on the one hand, and the other The face can be used as a clock source to generate the reference clock. The low frequency RC oscillator is a very mature basic circuit, and the low frequency RC oscillator 34 of the present embodiment can be a low frequency RC oscillator in the prior art. The choice of its oscillation frequency depends on the accuracy requirements of the timing reference clock. For example, if the accuracy of the timing reference clock is less than 40 parts per million, then the frequency is higher than the reciprocal of 40 parts per million, that is, 25 kHz, and then the low frequency RC oscillator is drifted by the semiconductor processing process. The effect (typically the frequency drift does not exceed ±50%), so the frequency of the low frequency RC oscillator can be chosen to be 50 kHz.

The function of the third frequency divider 35 is to divide the low frequency oscillation clock generated by the low frequency RC oscillator 34 by a third frequency dividing factor after starting, to generate a second reference clock of 1 Hz required for accurate timing. The third division factor may be the frequency information of the counter 33 itself. The third frequency divider 35 can adopt the same circuit design as the first frequency divider 31. The frequency dividing factor and the output clock of the first frequency divider 31, the second frequency divider 32, and the third frequency divider 35 may adopt other design forms that meet the requirements of the present invention, and are not limited to the values mentioned in the above embodiments. .

It can be understood that, in more embodiments of the present invention, the third frequency dividing factor may also be any frequency dividing value or multiplication value of the frequency information obtained by the counter. In a specific implementation, for example, a frequency divider may be configured between the counter and the third frequency divider to divide the frequency information to obtain a third frequency dividing factor, or may be obtained by the processing unit having processing capability according to the data output by the counter. The third frequency dividing factor is directly supplied to the third frequency divider for use.

Further, the SOC of this embodiment may further include: a control unit, configured to: after the counter obtains the counting result, control the first frequency dividing unit (which may include a first frequency divider and a second frequency divider, Either include a divider, a counter, and any one or any combination of clock generation units (such as high-frequency crystal oscillators) on the periphery of the SOC to enter an inactive state (ie, stop working). This can save power consumption; and at this time, the third frequency divider can still divide the oscillating signal by using the third frequency dividing factor to obtain the second reference clock. Since the low frequency oscillation clock generated by the low frequency RC oscillator during the SOC operation drifts with the internal temperature and voltage drift of the SOC, the third frequency division factor of the third frequency divider 35 can be calibrated in time to ensure the stability of the reference clock. In this case, the SOC of the embodiment of the present invention may further include: an automatic calibration unit, configured to control any one or any combination of the first frequency dividing unit, the counter, and the clock generating unit to enter a working state after a predetermined calibration interval time. . This automatic calibration unit may include a frequency divider (hereinafter referred to as a fourth frequency divider) and an automatic calibration start controller. among them:

The fourth frequency divider uses the count completion signal from the counter as an enable signal for receiving the second frequency dividing unit (which may include a frequency divider, after receiving the enable signal). In the case of the second reference clock signal referred to as the third frequency divider, the second reference clock signal is divided by a frequency dividing factor preset or received from the outside, and a time interval signal is generated and output to The above automatic calibration starts the controller.

The above-mentioned automatic calibration start controller uses the count completion signal from the counter as an enable signal for receiving the time interval signal from the fourth frequency divider after receiving the enable signal. The second reference clock signal of the frequency dividing unit generates a hardware enable signal of the clock generating unit, and/or generates an operation enable signal of the first frequency dividing unit with an external clock signal from the clock generating unit and outputs the same To the first frequency division unit. Thus, any one or any combination of the first frequency dividing unit, the counter, and the clock generating unit is brought from the non-working state to the operating state.

A specific implementation block diagram of the SOC according to the third embodiment of the present invention is shown in FIG. 4. On the basis of the second embodiment, an automatic calibration unit is further added, which is used to implement a timely automatic calibration of the third frequency division factor, and the automatic calibration unit includes A fourth frequency divider 36 and an automatic calibration start controller 37, wherein:

The fourth frequency divider 36 can be implemented by the same structure as the first to third frequency dividers, and the division factor (hereinafter referred to as the fourth frequency division factor) can be preset or received from the outside. The value can be determined by the maximum calibration interval. For example, if the maximum calibration interval is 64 seconds, the fourth division factor can be selected as 128. The calibration time interval selection signal (select ) shown in Fig. 4 is the fourth frequency dividing factor received from the outside. The fourth frequency divider 36 functions as a timer that receives the 1 Hz reference clock from the third frequency divider 35 after receiving the enable signal enable from the counter 33 (i.e., the count completion indicator signal of the counter 33). The signal is divided by the fourth division factor to the 1 Hz reference clock signal, and the obtained frequency division result is output to the automatic calibration start controller 37 as a time interval signal (timer).

The input signals of the automatic calibration start controller 37 include rst_n, enable, timer, clk_i and clk_o, wherein the rst_n connection start signal, the count completion signal of the enable connection counter 33, the timer connection time interval signal output by the fourth frequency divider 36, Clk_i is connected to the high-frequency crystal oscillator clock signal (called the high-frequency crystal clock), and clk_o is connected to the 1 Hz reference clock signal. The output signals are enable_osc and enable_divl2, where enable_osc is used as the hardware enable signal of the high-frequency crystal oscillator (the high-frequency crystal oscillator hardware is started), and enable_divl2 is used as the first frequency divider 31 and the second frequency divider 32. The work enable signal. The working principle is as follows: The automatic calibration start controller 37 takes the count completion signal from the counter 33 as an enable signal, and the automatic calibration start controller 37 receives the enable signal from the fourth frequency divider 36 after receiving the enable signal. In the time interval signal, the hardware start signal of the high frequency crystal oscillator is generated by the 1 Hz reference clock signal from the third frequency divider 35, and is sent to the high frequency crystal oscillator, and the high frequency crystal oscillator from the high frequency crystal oscillator is used to oscillate. The clock signal generates a first frequency divider 31, a second frequency divider 32, a working enable signal output to the first frequency divider 31 and the second frequency divider 32, such that the first frequency divider 31 and the second frequency divider The device 32 transitions to a working state.

To sum up, the implementation of the reference clock shown in Figure 4 is based on Figure 3, and further includes a fourth frequency divider and an auto-calibration start controller;

The fourth frequency divider uses the count completion signal from the counter as an enable signal, and the fourth frequency division After receiving the enable signal, the receiver receives the reference clock signal with a frequency of 1 Hz from the third frequency divider, and divides the reference clock signal of 1 Hz with a fourth frequency division factor preset or externally received. , generating a time interval signal output to the automatic calibration start controller;

The auto-calibration start controller will use the count completion signal from the counter as an enable signal. The auto-calibration start controller will receive the time interval signal from the fourth divider after receiving the enable signal. The 1 Hz reference clock signal of the frequency generator generates a hardware start signal of the high frequency crystal oscillator and transmits it to the high frequency crystal oscillator; the high frequency crystal oscillator clock signal from the high frequency crystal oscillator generates the first, The duty enable signal of the divide-by-2 is output to the first frequency divider and the second frequency divider, so that the first frequency divider and the second frequency divider are turned into an active state.

For the convenience of design, the first to fourth frequency dividers are designed to have the same structure. The following is a circuit of the first to fourth frequency dividers designed by Verilog hardware description language, where rst_n is the start signal, enable is the enable signal, divisor is the division factor, clk_i is the input clock, and clk_o is the frequency division. The output clock, pointer is the count pointer in the process of dividing or counting.

Module divider (rst_n, enable, divisor, clk_i, clk_o, pointer);

Parameter WIDTH = 10;

Parameter UDLY = 1; input rst_n;

Input enable;

Input clk_i;

Output clk_o;

Input [WIDTH- 1:0] divisor;

Output [WIDTH-1:0] pointer; wire [WIDTH-1 :0] divisor; reg [WIDTH- 1 :0] pointer;

Always @ (posedge clk_i or negedge rst_n) Begin

If (rst_n == 1'bO)

Pointer <= #UDLY 'hO;

Else if ((enable == l'bl) && (pointer < divisor - 1))

Pointer <= #UDLY pointer + l'bl;

Else

Pointer <= #UDLY 'hO;

End reg clk_o;

Always @ (posedge clk_i or negedge rst_n)

Begin

If (rst_n == 1'bO)

Clk_o <= #UDLY l'bO;

Else if (enable == l'bl)

Clk_o <= #UDLY pointer < divisor » 1;

Else

Clk_o <= #UDLY l'bO;

End

Endmodule II divider

The circuit implementation shown above is only one possible implementation of the first frequency divider 31 to the fourth frequency divider 36 in the solution of the present invention, and is not intended to limit the present invention.

The processing flow for generating the reference clock by the reference clock generating means 212 shown in FIG. 4 is as shown in FIG. 5, and includes the following steps:

Step 501: Power on the SOC.

Step 502: Start the low frequency RC oscillator 34.

Step 503: Start the high frequency crystal oscillator.

Step 504: Start the first frequency divider 31, the second frequency divider 32, and the counter 33 by software, and they start to work, calculate the frequency division factor required by the second frequency divider 32, and feed back the calculation completion signal to the SOC. .

Step 505: After receiving the counting completion signal fed back by the counter 33, the SOC starts the first The three-way divider 35, the third frequency divider 35 saves the division factor sent from the counter 33 and produces a 1 Hz reference clock required for accurate timing.

After that, in order to reduce power consumption, the SOC can place the first frequency divider 31, the second frequency dividing circuit 32, and the counter 33 and the high frequency crystal oscillator in an inoperative state, preventing them from operating to generate unnecessary power consumption. Thus, even if the high frequency crystal oscillator is disabled, the low frequency oscillation clock generated by the low frequency RC oscillator 34 is output to the third frequency divider 35, and the third frequency divider 35 oscillates the low frequency according to the divided frequency factor of the counter 33. The clock is divided to obtain a reference clock, so that the reference clock generating device 212 can still perform accurate timing, so that the high-frequency crystal oscillator oscillation operation is not required when the SOC standby state is reached, and the power consumption during the SOC standby operation is small.

In order to implement the function of timely calibration, step 505 may further include: Step 506: After the fourth frequency divider 36 is enabled, the timing is determined according to the frequency dividing factor determined according to the maximum calibration time interval, and the automatic calibration start controller 37 is based on the calibration time. The interval selection signal is turned on to turn on the high frequency crystal oscillator and the first frequency divider 31 and the second frequency divider 32 are enabled, and the process proceeds to step 503, and steps 503 to 505 are repeatedly executed to automatically calibrate the frequency dividing factor at intervals.

In the above embodiment, after the frequency information of the oscillating signal generated inside the integrated circuit is obtained, the first frequency dividing unit, the counter, and/or the clock generating unit outside the integrated circuit can be controlled to enter a non-operating state as needed (ie, Stop working), and at this time, the reference clock required for the application of the accurate timing can be divided according to the frequency division factor obtained by the frequency signal, and the low-power requirement of the standby state can be satisfied; The first frequency dividing unit, the counter, and the clock generating unit are controlled to enter an operating state at a predetermined calibration time interval to regain the frequency information of the oscillating signal, thereby functioning as a timely calibration of the reference clock.

The reference clock generating means 212 shown in FIG. 3 can implement steps other than step 506. Steps 501 to 505.

The implementation process of the reference clock according to the third embodiment of the present invention can be summarized according to the above description. Specifically, as shown in FIG. 6, the method includes the following steps:

Step 601: Multiplying the nominal frequency of the high frequency clock generated by the high frequency crystal oscillator by 2 and then dividing the frequency into a frequency division factor, and dividing the high frequency clock to output a clock signal having a duty ratio of 1. 0.5 Hz. ;

Step 602: Count the low frequency oscillation clock generated by the low frequency RC oscillator at a high level portion of the clock signal whose duty ratio is 1 frequency of 0.5 Hz, and count when the high level portion ends. After completion, the counting result is saved as the third frequency dividing factor; Step 603: The low frequency oscillation clock generated by the low frequency RC oscillator is divided according to the third frequency dividing factor, and a reference clock of 1 Hz is generated and output.

Preferably, the above step 601 can be divided into:

Step 601a: receiving a high frequency clock generated by the high frequency crystal oscillator and a nominal frequency of the high frequency clock, and dividing the high frequency clock by the nominal frequency, and outputting a clock signal having a frequency of 1 Hz;

Step 601b: Divide the above 1 Hz clock signal by two, and output a clock signal with a duty ratio of 1, and a frequency of 0.5 Hz.

Optionally, after the foregoing step 603, the method further includes:

Step 604: Divide a 1 Hz reference clock signal by using a fourth frequency division factor to generate a time interval signal;

Step 605: When receiving the time interval signal, generate a hardware start signal of the high frequency crystal oscillator with a reference clock signal of 1 Hz and send it to the high frequency crystal oscillator, and then go to the above step 601.

The technical scheme of the present invention utilizes a high frequency clock generated by a high frequency crystal oscillator, and obtains a frequency division factor of a reference clock of 1 Hz frequency through an internal hardware circuit of the SOC, thereby not requiring low In the case of a frequency crystal oscillator, a precise 1 Hz frequency reference clock is obtained, and a timely calibration can be achieved as needed.

The beneficial effect of the invention is that the two 氐 frequency crystal oscillator pins provided for the low frequency crystal oscillator in the SOC can be omitted, which provides the possibility that the SOC realizes a package with fewer pins, and on the other hand, the SOC can have More functions are implemented with the same number of pins. At the same time, in the multimedia processor SOC application, an external low-frequency crystal oscillator and its application circuit components can be saved, which can effectively reduce the BOM cost of the multimedia processor SOC application product and improve the market competitiveness of the SOC product.

In conclusion, the above is only the preferred embodiment of the present invention and is not intended to limit the scope of the present invention. Any modifications, equivalents, improvements, etc. made within the spirit and scope of the present invention are intended to be included within the scope of the present invention.

Claims

Claim

An integrated circuit, comprising: a first frequency dividing unit, a counter, an oscillating signal generating circuit, and a second frequency dividing unit; wherein:

The second frequency dividing unit is configured to divide the oscillating signal according to a frequency dividing factor obtained according to the frequency information to obtain a second reference clock.

The integrated circuit according to claim 1, wherein said first frequency dividing unit comprises a first frequency divider and a second frequency divider; wherein:

The first frequency divider is configured to obtain a clock signal by dividing the external clock signal by using a frequency dividing factor; and

The second frequency divider is configured to obtain the first reference clock signal by dividing a clock signal obtained by the first frequency divider by a frequency division.

The integrated circuit according to claim 1, wherein the first frequency dividing unit comprises: a frequency divider, wherein the one frequency divider is configured to divide the external clock signal by using a frequency dividing factor The frequency is obtained by the first reference clock.

The integrated circuit according to claim 1, wherein the integrated circuit further comprises: a control unit, configured to: when the counter obtains the frequency information, control the first frequency dividing unit, Any one or any combination of a counter and a clock generating unit external to the integrated circuit for generating the external clock signal enters an inactive state.

5. The integrated circuit of claim 4, wherein the integrated circuit The step includes: an automatic calibration unit, configured to control any one or any combination of the first frequency dividing unit, the counter, and the clock generating unit to enter an operating state after a predetermined calibration interval time.

The integrated circuit according to claim 5, wherein said automatic calibration unit comprises: a frequency divider and an automatic calibration start controller; wherein:

The frequency divider uses a count completion signal from the counter as an enable signal for receiving the second reference clock signal from the second frequency division unit after receiving the enable signal And dividing the second reference clock signal by a frequency dividing factor preset or received from the outside, generating a time interval signal and outputting the same to the automatic calibration start controller;

The automatic calibration start controller uses a count completion signal from the counter as an enable signal for receiving the time interval signal from the frequency divider after receiving the enable signal, Generating a hardware enable signal of the clock generating unit with the second reference clock signal from the second frequency dividing unit, and/or generating the operation of the first frequency dividing unit with the external clock signal The enable signal is output to the first frequency division unit.

The integrated circuit according to any one of claims 1 to 6, wherein the external clock signal is a high frequency clock signal, and the oscillating signal is a low frequency oscillating signal.

8. A method of obtaining a reference clock in an integrated circuit, the method comprising:

Generating an oscillating signal;

Frequency information of the oscillating signal is obtained by counting the oscillating signal by using the first reference clock; and And dividing the oscillating signal according to a frequency dividing factor obtained according to the frequency information to obtain a second reference clock.

The method according to claim 8, wherein the obtaining the first reference clock by dividing an external clock signal from the outside of the integrated circuit comprises:

The first reference clock is obtained by dividing the external clock signal by using a division factor.

10. The method according to claim 8, wherein the dividing the external reference clock signal from the external clock signal to obtain the first reference clock comprises: using the frequency dividing factor to the external clock The signal is divided to obtain a clock signal; and the first reference clock signal is obtained by dividing the clock signal obtained by the frequency division by two.

The method according to claim 8, wherein after obtaining the frequency information of the oscillating signal, the method further comprises: controlling a frequency dividing unit for dividing the frequency to obtain the first reference clock, The oscillating signal is counted to obtain a counter of the frequency information and any one or any combination of clock generating units for generating the external clock signal to enter a non-operating state.

The method according to claim 11, wherein after controlling any one or any combination of the frequency dividing unit, the counter, and the clock generating unit to enter a non-working state, the method further includes: Controlling any one or any combination of the frequency dividing unit, the counter, and the clock generating unit to enter an operational state after a predetermined calibration interval.

The method according to claim 12, wherein the controlling any one or any combination of the frequency dividing unit, the counter, and the clock generating unit to enter a work after a predetermined calibration interval time Status, including:

After the counting of the counter is completed and the second reference clock signal is received, The second reference clock signal is divided by a frequency dividing factor preset or received from the outside to generate a time interval signal;

Generating, by the second reference clock signal, a hardware enable signal of the clock generating unit after the counting of the counter is completed, and receiving the time interval signal, and/or generating the external clock signal The working enable signal of the frequency dividing unit is output.