JP2011197910A - Clock control circuit and microcomputer - Google Patents

Abstract

PROBLEM TO BE SOLVED: To reduce the power consumption of a circuit which periodically corrects a low accuracy clock outputted from a low accuracy clock oscillation circuit by using a high accuracy clock outputted from a high accuracy clock oscillation circuit.SOLUTION: A clock control circuit includes: a correction interval timer 80 clocking a correction interval for making a clock correction circuit 30 correct a frequency of a first clock signal; a correction time timer 70 clocking a correction time required for the clock correction circuit 30 to correct the frequency of the first clock signal; and control means 40, 50, 60 which make the correction time timer 70 start the clocking of the correction time for each correction interval clocked by the correction interval timer 80, brings a second oscillation circuit 20 into an operation state thereby making the clock correction circuit 30 correct the frequency of the first clock signal, and which brings a second clock oscillation circuit 20 into a stop state when the clocking of the correction time is notified by the correction time timer 70.

Description

  The present invention relates to a clock control circuit and a microcomputer having a clock correction circuit that corrects the frequency of a first clock signal using a second clock signal that is more accurate than the first clock signal.

  Conventionally, a main clock oscillation unit that generates a main clock, a sub clock oscillation unit that generates a sub clock, and an oscillation frequency of the sub clock generated by the sub clock oscillation unit using the main clock generated by the main clock oscillation unit There is a clock control circuit including a sub-clock correction unit that corrects (see, for example, Patent Document 1).

  Also, a main clock oscillating unit that generates a main clock, a sub clock oscillating unit that generates a sub clock having a frequency lower than that of the main clock, a pulse counter that counts the number of pulses of the main clock included in one cycle of the sub clock, and A calculation unit that calculates correction information using the number of pulses counted by the pulse counter and a predetermined reference pulse number, a pause signal counter that outputs a clock correction signal based on the correction information, and a clock correction signal There is also a clock correction circuit having a gate for correcting the output of the main clock (see, for example, Patent Document 2).

JP 2004-213197 A JP 2006-309479 A

  Some devices described in the above-mentioned Patent Document 1 reduce the power consumption by stopping the operation of the main clock oscillation unit when the CPU enters the sleep mode.

  However, in such a configuration in which the operation of the main clock oscillation unit is stopped, it becomes impossible to correct the oscillation frequency of the sub clock using the main clock, so that the oscillation frequency of the sub clock becomes the reference range as time passes. The possibility of deviating from is increased. For this reason, the CPU sleep mode is canceled at a preset time interval (for example, every 20 seconds) to wake up, and the main clock oscillation unit is operated intermittently according to instructions from the CPU to correct the sub clock. The unit is adapted to correct the oscillation frequency of the sub clock signal.

  However, waking up the CPU at preset time intervals in this manner causes an increase in power consumption.

  Further, although the device described in Patent Document 2 is not configured to periodically wake up the CPU, it is configured to always operate both the main clock oscillation unit and the sub clock oscillation unit. Therefore, there is a limit to reducing power consumption.

  In view of the above problems, the present invention reduces power consumption in a circuit that periodically corrects a low-precision clock output from a low-precision clock oscillation circuit using a high-precision clock output from the high-precision clock oscillation circuit. It aims to plan.

  In order to achieve the above object, according to a first aspect of the present invention, a first clock oscillation circuit (10) for generating a first clock signal and a second clock signal having a higher frequency and accuracy than the first clock signal are generated. A clock control circuit (1) comprising: a second clock oscillation circuit (20) that performs correction; and a clock correction circuit (30) that corrects the frequency of the first clock signal using the second clock signal. A correction interval timer (80) having a counter that operates in synchronization with the clock and clocking a correction interval for causing the clock correction circuit (30) to correct the frequency of the first clock signal using the counter; A counter that operates in synchronization with the clock, and uses the counter to compensate for the time required for correcting the frequency of the first clock signal by the clock correction circuit (30). For each correction interval timed by the time timer (70) and the correction interval timer (80), the correction time timer (70) starts measuring the correction time and makes the second clock oscillation circuit (20) in an operating state. Control to cause the clock correction circuit (30) to correct the frequency of the first clock signal and to stop the second clock oscillation circuit (20) when the correction time timer (70) notifies the time of the correction time. Means (40, 50, 60).

  According to such a configuration, the correction interval timer (80) that measures the correction interval for causing the clock correction circuit (30) to correct the frequency of the first clock signal using the counter that operates in synchronization with the first clock. A correction time timer (70) for measuring a correction time required for correcting the frequency of the first clock signal by the clock correction circuit (30) using a counter operating in synchronization with the first clock, and a correction interval timer (80 ) Causes the correction time timer (70) to start measuring the correction time and causes the second clock oscillation circuit (20) to be in an operating state for each correction interval timed by the first clock signal to the clock correction circuit (30). When the correction time timer (70) notifies the time of the correction time, the second clock oscillation circuit (20) is stopped. Thus, the frequency of the first clock signal is corrected by the clock correction circuit (30) without causing the CPU to wake up regularly and without constantly operating the second clock oscillation circuit (20). Power consumption can be reduced.

  In the second aspect of the invention, the control means (40, 50, 60) determines whether the CPU (90) operating with the second clock signal as a clock is in a normal operation state or a low power consumption state. When a signal indicating that the CPU (90) has changed from the normal operation state to the low power consumption state is input from the operation state control unit (40) to be monitored and the operation state control unit (40), the operation state is changed from the stop state to the operation state. At each correction interval timed by the correction interval timer (80), the correction time timer (70) starts to measure the correction time, and the second clock oscillation circuit (20) is put into an operating state to make the clock correction circuit (30 ) To correct the frequency of the first clock signal, and when the correction time timer (70) notifies the correction time, the second clock oscillation circuit (20) is stopped. Itself is characterized by comprising an operation control circuit to be stopped (50, 60), to the.

  According to such a configuration, the operation state control unit (40) monitors whether the CPU (90) operating with the second clock signal as a clock is in a normal operation state or a low power consumption state, and operates. When a signal indicating that the CPU (90) has changed from the normal operation state to the low power consumption state is input, the control circuit (50, 60) changes from the stop state to the operation state and is timed by the correction interval timer (80). At each correction interval, the correction time timer (70) starts measuring the correction time, and the second clock oscillation circuit (20) is put into an operating state to cause the clock correction circuit (30) to correct the frequency of the first clock signal. When the correction time timer (70) notifies the time of the correction time, the second clock oscillation circuit (20) is brought into a stopped state and itself is brought into a stopped state. That is, when the CPU (90) is in the low power consumption state, the operation control circuit (50, 60) is in the stopped state, and therefore, the power consumption can be further reduced.

  According to a third aspect of the present invention, when the CPU (90) changes from the low power consumption state to the normal operation state, the operation state control unit (40) sets the second clock oscillation circuit (20) to the operation state. It is characterized by letting.

  According to such a configuration, when the CPU (90) changes from the low power consumption state to the normal operation state, the operation state control unit (40) causes the second clock oscillation circuit (20) to enter the operation state. When the CPU (90) changes from the low power consumption state to the normal operation state, the second clock signal generated by the second clock oscillation circuit (20) can be instantaneously supplied to the CPU.

  According to a fourth aspect of the present invention, there is provided a microcomputer comprising a CPU (90) which operates using the second clock signal generated by the clock control circuit according to any one of the first to third aspects as a clock. The control means (40, 50, 60), correction time timer (70) and correction interval timer (80) in the clock control circuit are formed in the same chip as the CPU (90). It is said.

  According to such a configuration, the control means (40, 50, 60), the correction time timer (70), and the correction interval timer (80) in the clock control circuit are formed in the same chip as the CPU (90). Therefore, the control means (40, 50, 60), the correction time timer (70), and the correction interval timer (80) in the clock control circuit can be configured without substantially increasing the manufacturing cost.

  In addition, the code | symbol in the bracket | parenthesis of each means described in this column and the claim shows the correspondence with the specific means as described in embodiment mentioned later.

It is a figure which shows the structure of the clock control circuit which concerns on one Embodiment of this invention. 2 is a diagram showing a detailed configuration centering on a low-accuracy clock correction circuit 30. FIG. It is a time chart which shows operation | movement of a high precision clock oscillation circuit. It is a time chart which shows operation | movement of an operation state control part. It is a time chart which shows operation | movement of a correction | amendment interval timer. It is a time chart which shows operation | movement of a high precision clock oscillation operation control circuit. It is a time chart which shows operation | movement of a correction time timer. It is a time chart which shows operation | movement of a low precision clock correction | amendment operation control circuit. It is a time chart which shows operation | movement of a low precision clock correction circuit.

  A configuration of a clock control circuit according to an embodiment of the present invention is shown in FIG. The clock control circuit 1 includes a low-precision clock oscillation circuit (first clock oscillation circuit) 10, a high-precision clock oscillation circuit (second clock oscillation circuit) 20, a low-precision clock correction circuit 30, and an operation state control unit (operation state control). 40), a low-accuracy clock correction operation control circuit 50, a high-accuracy clock oscillation operation control circuit 60, a correction time timer 70, and a correction interval timer 80. A CPU 90 is connected to the operation state control unit 40.

  The operation state control unit 40, the low-accuracy clock correction operation control circuit 50, the high-accuracy clock oscillation operation control circuit 60, the correction time timer 70, and the correction interval timer 80 are an AND circuit, an OR circuit, a NAND circuit, an inverter circuit, etc. A logic circuit and various flip-flop circuits are used.

  The low-accuracy clock oscillation circuit 10 generates a low-accuracy clock signal (corresponding to the first clock signal) with relatively low accuracy, and outputs the generated low-accuracy clock signal from the signal line 11. The low-accuracy clock oscillation circuit 10 in the present embodiment is composed of a CR oscillation circuit, and always outputs a low-accuracy clock signal.

  The low-accuracy clock oscillation circuit 10 can correct the oscillation frequency of the low-accuracy clock signal by a control signal input from the low-accuracy clock correction circuit 30 via the signal line 31. Details of the correction of the oscillation frequency will be described later.

  The high-precision clock oscillation circuit 20 generates a high-precision high-precision clock signal (corresponding to the second clock signal) and outputs the generated high-precision clock signal from the signal line 21. The high-accuracy clock oscillation circuit 20 in this embodiment is configured by a crystal oscillation circuit. Note that the frequency of the high-accuracy clock signal is higher than that of the low-accuracy clock signal.

  The low precision clock correction circuit 30 is a circuit that corrects the oscillation frequency of the low precision clock using a high precision clock signal. FIG. 2 shows a detailed configuration centering on the low-accuracy clock correction circuit 30. The low-accuracy clock correction circuit 30 includes an edge detection circuit 35a, a pulse counter 35b, a count number setting register 35c, a comparison adjustment unit 35d, and a resistance adjustment circuit 35e. The low-accuracy clock oscillation circuit 10 includes a ladder resistor 10a, a capacitor 10b, an inverter 10c, and a buffer 10d as variable resistors whose resistance values are variable by a control signal from the resistance adjustment circuit 35e.

  The edge detection circuit 35a of the low precision clock correction circuit 30 detects the edge of the low precision clock SCLK output from the low precision clock oscillation circuit 10 and outputs a detection signal. The pulse counter 35b is a digital counter that counts output pulses of the high-precision clock signal MCLK. The count number setting register 35c is a register that stores an appropriate count number of MCLK pulses that should correspond to one cycle of the low-accuracy clock signal SCLK. That is, the count number set in the count number setting register 35c is set to a numerical value for adjusting the oscillation cycle of the low-accuracy clock signal SCLK according to the time during which the MCLK pulse is generated by the count number.

  When receiving the edge detection signal from the edge detection circuit 35a, the comparison adjustment unit 35d compares the pulse count number by the pulse counter 35b with the count number stored in the count number setting register 35c, and compares the count numbers with the comparison result. Based on this, an adjustment signal for adjusting the oscillation period of the low-accuracy clock signal SCLK is output.

  The resistance adjustment circuit 35e is a circuit that generates a control signal based on the adjustment signal from the comparison adjustment unit 35d and adjusts the resistance value of the ladder resistor 10a of the low-accuracy clock oscillation circuit 10 using this control signal.

  The operation of the low-accuracy clock correction circuit 30 is disclosed in detail in Japanese Patent Laid-Open No. 2001-111389, and the outline thereof will be described below. When one cycle of the low-accuracy clock signal SCLK elapses and the edge of the clock pulse is detected by the edge detection circuit 35a, the detection signal is output to the comparison adjustment unit 35d. Then, the comparison adjustment means 35d reads the number of pulses accumulated from the previous detection signal accumulated by the pulse counter 35b and the count number stored in the count number setting register 35c and compares them.

  Here, the count number set in the count number setting register 35c is an appropriate integrated value of pulses that should correspond to one cycle of the low-accuracy clock signal SCLK. Therefore, the comparison / adjustment unit 35d determines how much of one cycle of the low-accuracy clock signal SCLK is larger than an appropriate set value depending on how many high-accuracy clock signal MCLK pulses are accumulated in one cycle of the low-accuracy clock signal SCLK. Or small. The comparison adjustment unit 35d generates an adjustment signal for adjusting the oscillation period of the low-accuracy clock signal SCLK based on the determination result, and the adjustment resistor generation circuit 35e generates and outputs a control signal based on the adjustment signal. Then, the resistance value of the ladder resistor 10a is adjusted.

  Returning to the description of FIG. 1, the high-accuracy clock oscillation circuit 20 is supplied with a signal for instructing start or stop of oscillation from the operation state control unit 40 via the signal line 41, and A signal instructing oscillation start or oscillation stop is input from the precision clock oscillation operation control circuit 60.

  As shown in FIG. 3, the high-accuracy clock oscillation circuit 20 enters an operation state or a stop state according to a signal instructing the start or stop of oscillation input from the operation state control unit 40. The operation state or stop state is also entered by a signal instructing oscillation start or oscillation stop input from the high-accuracy clock oscillation operation control circuit 60. Note that the high-accuracy clock oscillation circuit 20 enters an operation state if a signal instructing the start of oscillation is input from either the operation state control unit 40 or the high-accuracy clock oscillation operation control circuit 60.

  The operation state control unit 40 operates in synchronization with the low precision clock signal generated by the low precision clock oscillation circuit 10. The operation state control unit 40 also has a PLL frequency multiplier circuit (not shown) that outputs a signal that oscillates synchronously at a frequency obtained by multiplying the frequency of the high-precision clock signal, and is output from the PLL frequency multiplier circuit. The signal is input to a main clock terminal (not shown) of the CPU 90.

  The operation state control unit 40 receives a signal indicating whether the wake-up state (normal operation state) or the sleep state (low power consumption state) input from the CPU 90 via the signal line 91, and the CPU 90 in the sleep state. The operating state (normal operating state or sleep state) of the CPU 90 is managed based on wake-up factor information such as a wake-up request periodically input from a wake-up timer (not shown) for intermittent wake-up. The main clock signal input to the main clock terminal of the CPU 90 is transmitted or stopped according to the operating state of the CPU 90.

  When the operation state control unit 40 recognizes that the CPU 90 is in the normal operation state based on a signal input from the CPU 90 via the signal line 91, the operation state control unit 40 instructs the high-accuracy clock oscillation circuit 20 to start oscillation via the signal line 41. A signal obtained by multiplying a high-accuracy clock signal input from the high-accuracy clock oscillation circuit 20 via the signal line 21 by a PLL frequency multiplication circuit (not shown) is output from the signal line 42. Further, a signal for instructing start of operation is sent to the low-accuracy clock correction circuit 30 via the signal line 43, and a signal for instructing to stop operation is sent to the high-accuracy clock oscillation operation control circuit 60 via the signal line 44.

  Further, when the operation state control unit 40 recognizes that the state of the CPU 90 is the sleep state based on a signal input from the CPU 90 via the signal line 91, the operation state control unit 40 causes the high state via the signal line 41 as illustrated in FIG. 4. A signal to stop oscillation is sent to the precision clock oscillation circuit 20 to stop the main clock signal output to the CPU 90 from the signal line 42. Further, a signal for instructing operation stop is sent to the low-accuracy clock correction circuit 30 via the signal line 43, and a signal for instructing start of operation is sent to the high-accuracy clock oscillation operation control circuit 60 via the signal line 44.

  The correction interval timer 80 measures the frequency correction interval (for example, 20 seconds) of the low-accuracy clock signal that is intermittently performed by the low-accuracy clock correction circuit 30 while the CPU 90 is in the sleep state. The correction interval timer 80 has a correction interval counter (not shown) that operates in synchronization with the low-accuracy clock signal, and the low-accuracy clock implemented by the low-accuracy clock correction circuit 30 using the correction interval counter. Times signal frequency correction interval.

  When a signal for instructing the timer start is input from the high-accuracy clock oscillation operation control circuit 60 via the signal line 63, the correction interval timer 80 starts measuring the correction interval as shown in FIG. When the count value of the counter reaches a count corresponding to the correction interval, a correction interval timer expiration signal is transmitted.

  When the signal for instructing the timer to stop is input from the high precision clock oscillation operation control circuit 60 via the signal line 63, the correction interval timer 80 stops counting the correction interval and the count value of the correction interval counter is set. It is supposed to return to zero.

  The high-precision clock oscillation operation control circuit 60 operates in synchronization with the low-precision clock signal generated by the low-precision clock oscillation circuit 10. The high-accuracy clock oscillation operation control circuit 60 enters an operation state when receiving a signal for instructing operation start from the operation state control unit 40 via the signal line 44, and enters a stop state when receiving a signal for instructing operation stop. .

  In this embodiment, the low-accuracy clock correction operation control circuit 50, the high-accuracy clock oscillation operation control circuit 60, the correction time timer 70, and the correction interval timer 80 each include a gate circuit at the input portion of the low-accuracy clock signal. By controlling this gate circuit, the operation state or the stop state is switched.

  When the high-accuracy clock oscillation operation control circuit 60 is stopped, the high-accuracy clock oscillation circuit 20 stops oscillating, the low-accuracy clock correction operation control circuit 50 is stopped, and the interval correction timer 80 is also stopped.

  Further, when a signal for instructing the start of operation is input from the operation state control unit 40 via the signal line 44 and the high precision clock oscillation operation control circuit 60 enters an operation state, as shown in FIG. Then, a signal instructing the timer start is sent to the interval correction timer 80.

  As shown in FIG. 5, the interval correction timer 80 starts measuring the correction interval when receiving a signal instructing the start of the timer. When the correction interval elapses, the interval correction timer 80 performs high-accuracy clock oscillation via the signal line 81. A correction interval timer expiration signal is sent to the operation control circuit 60.

  When this correction interval timer expiration signal is input via the signal line 81, the high-accuracy clock oscillation operation control circuit 60 receives the low-accuracy clock correction operation control circuit 50 via the signal line 62 as shown in FIG. Sends a signal to start operation.

  The correction time timer 70 is for measuring a correction time (for example, 2 milliseconds) required for correction of the low-accuracy clock oscillation circuit 30. The correction time timer 70 has a correction time counter (not shown) that operates in synchronization with the low-accuracy clock signal, and uses this correction time counter to measure the correction time, and the count value of the correction time counter is When the count number corresponding to the correction time is reached, a correction time timer expiration signal is transmitted.

  When the correction time timer 70 receives a signal instructing timer start from the low precision clock correction operation control circuit 50 via the signal line 53, the correction time timer 70 starts measuring the correction time as shown in FIG. When the count value reaches the count corresponding to the correction time, a correction time timer expiration signal is transmitted.

  When the signal for instructing to stop the timer is input from the low precision clock correction operation control circuit 50 via the signal line 53, the correction time timer 70 stops counting the correction time and the count value of the correction time timer is changed. It is supposed to return to zero.

  The low precision clock correction operation control circuit 50 operates in synchronization with the low precision clock signal generated by the low precision clock oscillation circuit 10.

  When the low-accuracy clock correction operation control circuit 50 enters an operation state when a signal for instructing the operation start is input from the high-accuracy clock oscillation operation control circuit 60 via the signal line 62, the signal line 51 is connected as shown in FIG. Via the signal line 52, a signal indicating that the correction has not been completed, and a signal indicating that the correction has not been completed. A signal instructing the start of the timer is sent to the correction time timer 70 via the line 53.

  The correction time timer 70 counts the correction time when receiving a signal instructing the start of the timer, and sends a correction time timer expiration signal to the low-accuracy clock correction operation control circuit 50 via the signal line 71 when the correction time elapses. To do.

  When the low-accuracy clock correction operation control circuit 50 receives the correction time timer expiration signal via the signal line 71, the low-accuracy clock correction operation control circuit 50 sends a signal indicating operation stop to the low-accuracy clock correction circuit 30 via the signal line 51 and A signal indicating that the correction is completed is sent to the high-accuracy clock oscillation operation control circuit 60 via the line 52.

  As shown in FIG. 9, the low-accuracy clock correction circuit 30 enters a stop state when a signal indicating operation stop is input from the low-accuracy clock correction operation control circuit 50 via the signal line 51, and a signal indicating operation start is received. When it is input, it enters an operating state. Further, when a signal for instructing the start of operation is input to the low-accuracy clock correction circuit 30 via the signal line 43, the operation state is entered, and when a signal indicating operation stop is entered, the operation state is stopped.

  The high-accuracy clock oscillation operation control circuit 60 receives a signal indicating that the correction is incomplete from the low-accuracy clock correction operation control circuit 50 via the signal line 52 as shown in FIG. Then, a signal for instructing the start of oscillation is sent to the high-accuracy clock oscillation circuit 20 via the signal line 61, and a signal for instructing to stop the operation is sent to the correction interval timer 80 via the signal line 63.

  The high-accuracy clock oscillation operation control circuit 60 receives a signal indicating that the correction is completed from the low-accuracy clock correction operation control circuit 50 via the signal line 52, and then receives the high-accuracy clock via the signal line 61. A signal for instructing oscillation stop is transmitted to the oscillation circuit 20, a signal for instructing operation stop is transmitted to the low-accuracy clock correction operation control circuit 50 via the signal line 62, and a correction interval timer is further transmitted via the signal line 63. A signal instructing operation start is sent to 80.

  Next, the operation of the clock control circuit 1 will be described. When the CPU 90 is in the normal operation state, the operation state control unit 40 recognizes that the CPU 90 is in the normal operation state based on a signal or the like input from the CPU 90 via the signal line 91 and passes through the signal line 41. Then, a signal for instructing the oscillation start to the high precision clock oscillation circuit 20 is transmitted. Therefore, a high precision clock signal is generated by the high precision clock oscillation circuit 20. Further, a signal that oscillates synchronously with the frequency by multiplying the frequency of the high-accuracy clock signal by the PLL frequency multiplication circuit is input to a main clock terminal (not shown) of the CPU 90.

  Further, the operation state control unit 40 sends a signal for instructing the low precision clock correction circuit 30 to start the operation via the signal line 43, and causes the low precision clock correction circuit 30 to correct the frequency of the low precision clock signal. .

  Further, when the CPU 90 is in the normal operation state in this way, the operation state control unit 40 sends a signal for instructing the high-accuracy clock oscillation operation control circuit 60 to stop the operation via the signal line 44. With this signal, the low-accuracy clock correction operation control circuit 50, the high-accuracy clock oscillation operation control circuit 60, the correction time timer 70, and the correction interval timer 80 are stopped.

  Next, when the CPU 90 enters the sleep state, the operation state control unit 40 recognizes that the CPU 90 has entered the sleep state based on a signal or the like input from the CPU 90 via the signal line 91, and sets the high level via the signal line 41. A signal to stop oscillation is sent to the precision clock oscillation circuit 20 and the main clock signal output to the CPU 90 from the signal line 42 is stopped. Accordingly, the high-precision clock is not output from the high-precision clock oscillation circuit 20, and the main clock signal is not output from the signal line 42 to the CPU 90.

  The operation state control unit 40 sends a signal for instructing the low-accuracy clock correction circuit 30 to stop the operation via the signal line 43, and starts the operation to the high-accuracy clock oscillation operation control circuit 60 via the signal line 44. Send a signal to indicate. As a result, the low-accuracy clock correction circuit 30 continues to be stopped, and the high-accuracy clock oscillation operation control circuit 60 enters the operating state.

  When the high-accuracy clock oscillation operation control circuit 60 enters the operating state, it sends a signal instructing the correction interval timer 80 to start measuring the correction interval. Thereby, the correction interval timer 80 starts measuring the correction interval.

  When the correction interval elapses and a correction interval timer expiration signal is received from the correction interval timer 80, a signal instructing the start of operation is sent to the low precision clock correction operation control circuit 50 via the signal line 62. As a result, the low-accuracy clock correction operation control circuit 50 enters an operating state.

  When the low-accuracy clock correction operation control circuit 50 is in the operating state, it sends a signal for instructing the low-accuracy clock correction circuit 50 to start the operation via the signal line 51 and also starts the correction time timer 70 to start measuring the correction time. Send a signal to indicate. As a result, the low-accuracy clock correction circuit 50 starts correcting the frequency of the low-accuracy clock signal, and the correction time timer 70 starts measuring the correction time.

  After the correction of the frequency of the low-accuracy clock signal by the low-accuracy clock correction circuit 50 is completed, when the correction time timer expiration signal is received from the correction time timer 70, the low-accuracy clock correction operation control circuit 50 performs the low-accuracy clock correction. A signal indicating the operation stop is sent to the circuit 30 and a signal indicating that the correction is completed is sent to the high precision clock oscillation operation control circuit 60. As a result, the low-accuracy clock correction circuit 30 is stopped, the high-accuracy clock oscillation operation control circuit 60 sends a signal to stop oscillation to the high-accuracy clock oscillation circuit 20, and the low-accuracy clock correction operation control circuit 50 The correction interval timer 80 starts to measure the correction interval.

  When the correction interval has elapsed and a correction interval timer expiration signal is received from the correction interval timer 80, a signal instructing the start of operation is sent to the low-accuracy clock correction operation control circuit 50 via the signal line 62. As a result, the low-accuracy clock correction operation control circuit 50 enters an operating state.

  The above-described processing is repeatedly performed, and the correction of the frequency of the low-accuracy clock signal by the low-accuracy clock correction circuit 30 is intermittently performed.

  According to the configuration described above, the correction interval timer 80 that measures the correction interval for causing the clock correction circuit 30 to correct the frequency of the first clock signal using the counter that operates in synchronization with the first clock, and the first clock A correction time timer 70 that measures the correction time required for correcting the frequency of the first clock signal by the clock correction circuit 30 using a counter that operates in synchronization with each other, and a correction interval that is corrected by the correction interval timer 80. The time timer 70 starts measuring the correction time, and the high-accuracy clock oscillation circuit 20 is put into an operating state to cause the clock correction circuit 30 to correct the frequency of the first clock signal, and the correction time timer 70 measures the correction time. Is notified, the second clock oscillation circuit 20 is stopped and the CPU is periodically woken up. Without also without the constantly operating state and the second clock oscillation circuit 20, it is possible to implement the correction of the frequency of the first clock signal by the clock correction circuit 30, it is possible to reduce power consumption. Many automobiles owned by general users are parked for most of the day, and applying this clock control circuit to each in-vehicle device installed in such an automobile can greatly reduce the amount of power consumed. It is possible to obtain.

  The operation state control unit 40 monitors whether the CPU 90 operating with the second clock signal as a clock is in a normal operation state or a low power consumption state, and the high-accuracy clock oscillation operation control circuit 50 and the low-accuracy clock. When the signal indicating that the CPU 90 has changed from the normal operation state to the low power consumption state is input, the correction operation control circuit 60 changes from the stop state to the operation state, and corrects at each correction interval timed by the correction interval timer 80. The time timer 70 starts measuring the correction time, and the second clock oscillation circuit 20 is put into an operating state to cause the clock correction circuit 30 to correct the frequency of the first clock signal. The correction time timer 70 measures the correction time. Is notified, the second clock oscillation circuit 20 is brought into a stopped state and is also brought into a stopped state. That is, when the CPU 90 is in a normal operation state, the high-accuracy clock oscillation operation control circuit 50 and the low-accuracy clock correction operation control circuit 60 are in a stopped state, so that power consumption can be further reduced.

  Further, when the CPU 90 changes from the low power consumption state to the normal operation state, the operation state control unit 40 changes the second clock oscillation circuit 20 to the operation state, so that the CPU 90 changes from the low power consumption state to the normal operation state. In this case, the second clock signal generated by the second clock oscillation circuit 20 can be instantaneously supplied to the CPU.

  In addition, this invention is not limited to the said embodiment, Based on the meaning of this invention, it can implement with a various form.

  For example, in the above embodiment, the operation state control unit 40, the low-accuracy clock correction operation control circuit 50, the high-accuracy clock oscillation operation control circuit 60, the correction time timer 70, and the correction interval timer 80 in the present clock control circuit are separated from the CPU 90. However, for example, the circuits 40 to 80 may be configured as a microcomputer formed in the same chip as the CPU 90. Thus, by forming the circuits 40 to 80 in the same chip as the CPU 90, the circuits 40 to 80 can be configured with almost no increase in manufacturing cost.

  In the above embodiment, the clock control circuit is configured using the low-accuracy clock correction circuit that corrects the frequency of the clock signal by changing the resistance value of the variable resistor. Without using the clock correction circuit, for example, the clock control circuit may be configured using a clock correction circuit that corrects the number of pulses of the clock signal using a gate as described in Patent Document 2.

DESCRIPTION OF SYMBOLS 1 Clock control circuit 10 Low precision clock oscillation circuit 20 High precision clock oscillation circuit 30 Low precision clock correction circuit 40 Operation state control part 50 Low precision clock correction operation control circuit 60 High precision clock oscillation operation control circuit 70 Correction time timer 80 Correction interval Timer 90 CPU

Claims (4)

A first clock oscillation circuit (10) for generating a first clock signal; a second clock oscillation circuit (20) for generating a second clock signal having a higher frequency and accuracy than the first clock signal; and the second clock. A clock control circuit (1) comprising a clock correction circuit (30) for correcting the frequency of the first clock signal using a signal,
A correction interval timer (80) that has a counter that operates in synchronization with the first clock and counts a correction interval that causes the clock correction circuit (30) to correct the frequency of the first clock signal using the counter. )When,
A correction time timer (70) having a counter that operates in synchronization with the first clock, and clocking a correction time required for correcting the frequency of the first clock signal by the clock correction circuit (30) using the counter. When,
For each correction interval timed by the correction interval timer (80), the correction time timer (70) starts measuring the correction time, and the second clock oscillation circuit (20) is put into an operating state. When the clock correction circuit (30) corrects the frequency of the first clock signal and the correction time timer (70) notifies the time of the correction time, the second clock oscillation circuit (20) is stopped. And a control means (40, 50, 60). The control means (40, 50, 60) is an operation state control unit (40) for monitoring whether the CPU (90) operating with the second clock signal as a clock is in a normal operation state or a low power consumption state. When,
When a signal indicating that the CPU (90) has changed from the normal operation state to the low power consumption state is input from the operation state control unit (40), the operation state is changed from the stop state to the operation state, and the correction interval timer (80) At each correction interval to be timed, the correction time timer (70) starts measuring the correction time, and the second clock oscillation circuit (20) is put into an operating state to cause the clock correction circuit (30) to operate. When the correction of the frequency of the first clock signal is performed and the time of the correction time is notified by the correction time timer (70), the second clock oscillation circuit (20) is brought into a stopped state and itself is also brought into a stopped state. The clock control circuit according to claim 1, further comprising an operation control circuit (50, 60).   The operation state control unit (40) causes the second clock oscillation circuit (20) to be in an operation state when the CPU (90) changes from a low power consumption state to a normal operation state. 3. The clock control circuit according to 2. A microcomputer comprising a CPU (90) that operates using the second clock signal generated by the clock control circuit according to any one of claims 1 to 3 as a clock,
The control means (40, 50, 60), the correction time timer (70), and the correction interval timer (80) in the clock control circuit are stored in the same chip as the CPU (90). A featured microcomputer.

Images