JPH0784666A - Control device for intermittent operation of cpu - Google Patents

Abstract

PURPOSE:To highly accurately control the sleeping time of a CPU capable of executing intermittent operation. CONSTITUTION:In the case of starting the CPU 1 when a counter 4 counts an external clock signal 3 up to x periods in the sleeping state of the CPU 1, the periods of the signal 3 are highly accurately measured by means of a reference clock signal outputted from a reference oscillator 7 in accordance with a timing signal 6. A compensation part 8 compensates the value of (x) based upon the measured value and a required sleeping time. Consequently the sleeping time of the CPU 1 can be accurately held independently of the dispersion of frequency of the signal 3.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a CPU intermittent operation control device for controlling a CPU to operate intermittently.

[0002]

2. Description of the Related Art Conventionally, a CPU is operated intermittently to reduce power consumption. FIG. 3 is a block diagram showing a conventional intermittent operation control device for a CPU. In the figure, 1 is a CPU that performs an intermittent operation, and 2 is an external clock signal 3 having a frequency of, for example, several hundred kHz.
An external clock signal oscillator 4 that oscillates is a counter for a timer event that is provided in the CPU 1 and that counts the external clock signal 3.

Next, the operation will be described with reference to the flowchart of FIG. After the power source such as a battery is turned on in step ST1, a value of x corresponding to a desired sleep time (stop time of the CPU 1) T is set in the counter 4 in step ST2. Next, in step ST3, it is checked whether or not the CPU 1 is in a stopped state (SLEEP state) in which the operation is stopped. If it is not in the stopped state, the CPU 1 performs a normal operation based on the program in step ST4.

If the CPU 1 is in a stopped state, step ST
At 5, the counter 4 starts counting the external clock signal 3 obtained from the external clock signal oscillator 2. Then, counting is continued until the count value becomes x in step ST6, and when the count value becomes x, CP is processed in step ST7.
U1 is activated and enters the operating state (WAKE UP state).

[0005]

Since the conventional CPU intermittent operation control device is configured as described above, when the external clock signal oscillator 2 is configured by a capacitor or a resistor for cost reduction, However, the oscillation frequency may change significantly due to variations in these elements, temperature changes, etc., which may change the sleep time T of the CPU 1. When the sleep time T changes, there is a problem that the operation of the control target controlled by the CPU 1 may be adversely affected.

The present invention has been made to solve the above problems, and an object of the present invention is to provide an intermittent operation control device for a CPU, which is capable of accurately maintaining a stop time of the CPU at a predetermined length. I am trying.

[0007]

In the present invention, C
A timing signal generation circuit that gives a timing signal to the PU, and a correction that measures the cycle of the external clock signal using the reference clock signal of the CPU according to the timing signal and corrects the set value of the counter from the measured value and the sleep time. And means are provided.

[0008]

Since the cycle of the external clock signal can be measured with high accuracy using the reference clock signal, the counter set value x for obtaining the desired sleep time from this measured value can be set.
Can be corrected to an accurate value.

[0009]

1 is a block diagram showing an intermittent operation control device for a CPU according to an embodiment of the present invention. Parts corresponding to those in FIG. In FIG. 1, reference numeral 5 is a timing signal 6 for operating the CPU 1 and for measuring the cycle of the external clock signal 3.
Is a timing signal generating circuit, and reference numeral 7 is a reference oscillator for oscillating a reference clock signal necessary for the arithmetic processing of the CPU 1. The reference oscillator 7 uses a crystal oscillator having a high oscillation frequency and oscillates a reference clock signal of, for example, several MHz. Reference numeral 8 denotes a correction unit provided in the CPU 1 as correction means for correcting the value of x.

Next, the operation will be described with reference to the flowchart of FIG. Steps ST1 to ST7 in the flowchart of FIG. 2 are the same as in FIG. In FIG.
After setting x to the counter 4 in step ST2, it is checked in step ST8 whether the timing signal 6 has changed from L to H, and during the period of L, the operations of steps ST3 to ST7 are performed. If the timing signal 6 becomes H, step ST9
Then, the CPU 1 is activated and the period of the external clock signal 3 is measured with high accuracy using the reference clock of the reference oscillator 7. In step ST10, the correction unit 8 uses the measured value to calculate the count number for counting the sleep time T by the counter 4, and corrects the value of x with the calculated count value.

Thereafter, the operations of steps ST3 to ST7 are performed, but at this time, the corrected value of x is used in step ST6. This corrected value of x is held until the timing signal 6 next changes from L to H. According to the above, the value of x for always obtaining the desired sleep time T can be obtained, and the sleep time T of the CPU 1 can be obtained with high accuracy.

[0012]

According to the present invention, the cycle of the external clock signal is measured with high accuracy using the reference clock signal according to the timing signal, and the set value of the counter is corrected from this measured value and the desired sleep time. I configured it to
There is an effect that the sleep time of the CPU can always be kept at a predetermined length with high accuracy regardless of variations in the external clock signal.

[Brief description of drawings]

FIG. 1 is a block diagram showing an intermittent operation control device for a CPU according to an embodiment of the present invention.

FIG. 2 is a flowchart showing the operation of the same device.

FIG. 3 is a block diagram showing a conventional intermittent operation control device for a CPU.

FIG. 4 is a flowchart showing an operation of the same device.

[Explanation of symbols]

 1 CPU 3 External Clock Signal 4 Counter 5 Timing Signal Generation Circuit 6 Timing Signal 8 Correction Unit (Correction Means)

Claims (1)

[Claims] 1. An intermittent operation control device for a CPU, wherein an external clock signal applied from the outside of the CPU is counted up to a set value by a counter provided in the CPU to obtain a sleep time of the CPU. A timing signal generating circuit that applies a timing signal having the following to the CPU, and the cycle of the external clock signal is measured using a reference clock signal used for the operation of the CPU according to the timing signal obtained from the timing signal generating circuit. An intermittent operation control device for a CPU, comprising: a correction unit that corrects the set value using the measured value and the sleep time.