JPH0366847B2 - - Google Patents

Description

[Detailed Description of the Invention] [Industrial Application Field] The present invention provides a method for adjusting the duty ratio of an output signal from 0% to
Regarding a duty control pulse generation circuit that can control up to 100%.

[Conventional technology]

There are roughly two methods for controlling the duty ratio (ratio of on-time to one period T, hereinafter abbreviated as duty) of the output signal from 0% to 100%. One method is to generate it using hardware using an electric circuit that combines active elements and CR components. The other method is to generate it using software that combines the CPU and peripheral circuits.

[Problems to be Solved by the Invention] The conventional method of generating electricity using hardware using an electric circuit has a cost limit, and it is difficult to reduce the cost.

Furthermore, the method of generating pulses using software has the disadvantage that duty control cannot be performed over a wide range due to the time required to set the duty value, the relationship between the clock frequency and the duty of the output pulse, and so on.

[Means for solving problems]

The present invention has been made in view of the above points, and
The purpose is to perform low-cost and wide-ranging duty control using software.

In order to achieve this object, the duty control pulse generation circuit according to the present invention includes a counting means for counting clock signals, and a first pulse generating circuit that compares the count value of the counting means with a set value, and generates an output when the two match. and a second comparison means, and a first
flip-flop means that is reset by the output of the second comparing means; and a central controller that performs interrupt processing according to the outputs of the first and second comparing means; calculates the duty ratio of the output pulse signal based on the input data in interrupt processing, and if the duty of the output pulse is less than a predetermined value, the first data determines the time from the falling edge of the output pulse signal to the next rising edge. and second data that determines the time from one fall of the output pulse signal to the next fall are set in the first and second comparison means, respectively, and when the second data and the count value match, the next interrupt is generated. Processing is started, and when the duty ratio of the output pulse is equal to or greater than a predetermined value, the third data that determines the time from the rise of the output pulse signal to the next fall and the time from the rise of the output pulse signal to the next rise are determined. the fourth data and the first and second data, respectively.
When the fourth data and the count value match, the next interrupt processing is started, and when the duty ratio of the output pulse changes from below to above a predetermined value, and from above to below,
The configuration is such that the next interrupt process is started when the first and third data match the count value.

[Effect]

In this configuration, by selecting and operating either the first setting means or the second setting means based on the output of the duty detection means, when the duty changes from a predetermined value to either a large or small value, By switching the first setting means or the second setting means, it is possible to output a pulse signal whose duty ratio changes continuously.

〔Example〕

Hereinafter, the present invention will be explained based on FIGS. 1 to 5.

FIG. 1 is a block diagram showing one embodiment of a duty control pulse generation circuit according to the present invention.

In FIG. 1, 3 is a sensor that detects, for example, changes in temperature. 1 is a central control unit (CPU) that inputs a measured value from the sensor 3 and outputs a preset value to a comparator to be described later based on this measured value. Counter 4 is an up counter that increments from zero and is used in a free running state. The count value of counter 4 is supplied to comparators 5 and 6. Comparators 5 and 6 compare the preset value set by the CPU 1 and the count value supplied from the counter 4, and when the two values match, the CPU outputs an output that changes from L level to H level.
1 interrupt pins INT1 and INT2.

The outputs of comparators 5 and 6 are also supplied to flip-flop 8. Flipflop 8 is
It is an RS type flip-flop, and is set when the output of comparator 6 rises, and reset when the output of comparator 5 rises. The Q output of this flip-flop 8 is the first
It is taken out from the output terminal 9 as the output of the circuit shown in the figure. The output taken out from the output terminal 9 is input to the driver 10 as shown in FIG. 2, and the driver 10 drives the actuator 11 based on this output.

Next, the basic operation of this embodiment will be explained using the flowchart shown in FIG.

The program shown in FIG. 3 is used as a duty control pulse generation circuit for supplying pulses whose duty is changed according to the measured value of the sensor 3 to the actuator 11.

The CPU 1 of the duty control pulse generation circuit 10 according to this embodiment normally executes another program (main program), but when an interrupt signal is supplied to INT1 and INT2 from the comparators 5 and 6, the main program Interrupt the third
Start the interrupt program shown in the figure.

Setting values based on the measured values of the sensor 3 are set in the comparators 5 and 6 by the CPU 1, respectively.
This set value determines the duty of the pulse that will be output from now on.

Then, when interrupt processing starts,
In step S101, the CPU 1 first masks an interrupt (hereinafter referred to as interrupt 2) caused by the comparator of comparators 5 and 6 whose set value has a longer time length. To explain this mask processing specifically, the CPU 1 stores the set values given to the comparators 5 and 6, and at step S101, the CPU 1's processing program connects the comparator with the longer set value. INT terminal (INT1 or INT2)
This is to stop the input detection process.

Next, in step S102, the comparator 5
and 6, it is determined whether the interrupt by the comparator whose set value is shorter in time (hereinafter referred to as interrupt 1) has been canceled. To explain concretely what it means to cancel an interrupt here, in the processing program of CPU1, restart the detection process of the input of the INT pin (INT1 or INT2) connected to the comparator that sends the interrupt signal you want to cancel. It is.

Next, if interrupt 1 has been canceled, the CPU 1 inverts the flag in step S103 as a mark that it has been canceled, and also masks interrupt 1 anew. after that,
In step S104, the CPU 1 determines the duty of the pulse output from the flip-flop 8 based on the set value from the sensor 3. If interrupt 1 is already masked, the duty is determined immediately. Unfortunately, the duty in this embodiment is the ratio of the ON time to one cycle T, ie, the on-duty, as shown in FIG.

Next, in step S105, it is determined whether the flag is 1 or not. Unfortunately, the initial value of the flag is set to "0".

In S105, if the flag is "0", as shown in step S106, the CPU
In step 1, two data, data A and data B, are calculated based on the duty ratio determined in S104, data A is set in the comparator 6, and data B is set in the comparator 5. Further, if the flag is "1", the CPU 1 executes S10 as shown in step S107.
Two data, data C and data D, are calculated based on the duty ratio obtained in step 4, and data C
is set in comparator 5, and data D is set in comparator 6.

Here, data A is data that determines the time from the falling edge of the output pulse signal to the next rising edge, that is, the length of the "L" period in the period T, as shown in FIG. This is data that determines the time from one falling edge to the next falling edge, that is, the period T of the output pulse.

Furthermore, data C is data that determines the time from the rising edge of the output pulse signal to the next falling edge, that is, the length of the "H" period in the period T, and data D is the data that determines the length of the "H" period in the period T. This is data that determines time.

As can be seen from FIG. 5, each value of data A, B, C, and D is determined by the following equation.

An=Tn−(Tn×dn) (1) Bn=Hn (2) Cn=Tn×d _o-1 (3) Dn=Cn+Tn−(Tn×d _o+1 ) (4) It can be seen from the above equations As such, the ratio of data C and D does not represent the on-duty in the corresponding period.

If the flag is "0" in step S105, it is further determined in step S108 whether the duty is 50% or more based on the data in step S104, and if it is greater than 50%, step In S111, interrupt 1 is canceled and the process returns to the main program. Also
If it is less than 50%, interrupt 2 is canceled in step S110 and the process returns to the main program.

If the flag is "1" in step S105, it is further determined in step S109 whether the duty is 50% or more based on the data in step S104, and if it is greater than 50%, step S110 is performed. At this point, interrupt 2 is canceled and the process returns to the main program. Also, 50
% or less, in step S111, interrupt 1 is canceled and the process returns to the main program.

Next, the operation when outputting a pulse signal whose duty changes as shown in FIG. 4 will be explained.

In the initial state, the flag is set to "0" and both interrupts 1 and 2 are masked.
For this reason, in period T2, step S1
02, the process moves to step S104, and the duty _d1 is determined based on the signal from the sensor 3. Since the flag is "0", the process moves from step S105 to step S106, and the above-mentioned process is performed based on the duty _d1 .
The values of A ₁ and B ₁ are determined using equations (1) and (2) and set in comparators 5 and 6. Step S108
Since duty d ₁ is less than 50% in
Interrupt 2 is canceled. For this purpose, CPU1
Of the INT terminals (INT1, INT2) connected to comparators 5 and 6, the INT terminal to which data _B1 is set is enabled to receive. The processing up to this point is performed during the period t ₂ in Figure 4, and the data B ₁
When the value of counter 4 matches the value of counter 4, the next interrupt signal is input from the comparator, and the period T ₃
begins.

Next, in cycle _T3 , since interrupt 1 has not been canceled yet, the process moves from step S102 to step S104, and in step S104, duty _d3 in cycle T3 is determined based on the signal from sensor ₃ . Since the flag is still "0", the process moves from step S105 to step S106, and data A ₃ and B ₃ are obtained based on duty d ₃ . In the next step S108, the duty _d3 is
It is determined whether the duty is 50% or more, but since the duty in cycle _T3 is 50% or more, the process moves to step S111, and interrupt 1 is canceled this time. The processing up to this point is performed during period _t3 . Since interrupt 1 has been canceled, CPU 1 can receive the INT terminal connected to the one of comparators 5 and 6 to which data A ₃ with a shorter period is set, and transfers the value of data A ₃ and counter 4. When the values match, period _T3 has not yet ended, but the next interrupt is received at the INT pin.

This time, since interrupt 1 was canceled in the previous process, the flag is inverted and set to "1" in step S103. Next step S10
4, the duty d ₄ of period T ₄ is determined. Since the flag has become "1", the process moves from step S105 to step S107, where data C ₄ and D ₄ are obtained from equations ( ₃ ) and (4) based on duty d 4 and set in comparators 5 and 6, respectively. Ru. Next, the process moves to step S109, and it is determined whether the duty is 50% or more. Since the duty _d4 is 50% or more, the process moves to step S110, and interrupt 2 is canceled. The processing up to this point is performed in period _t4 .

In period _t4 , interrupt 2 is released, so CPU1 is connected to the comparator 5 and 6 that is set to data _D4 with a longer period.
The INT terminal is enabled for reception, and when the value of data _D4 and the value of counter 4 match, the next interrupt operation is received.

Next, in periods T ₅ and T ₆ , the duty d ₅ ,
Since d ₆ is all 50% or more, the same control as in period T ₄ is repeated.

Then, at the end of period _T6 , the next interrupt enters and _{period t7} begins in period T6. When interrupt operation starts at the beginning of period _t7 , interrupt 1
is masked, the process moves from step _S102 to step S104, and the duty _d7 of the next cycle T7 is determined based on the signal from the sensor. _Since the flag is set to "1" during the flag period _t4 and remains unchanged, the process moves to step S107, where data _C7 and _D7 are calculated based on the duty d7.
Since _d7 is less than 50%, the process moves from step S109 to step S111, and interrupt 1 is canceled.

Since interrupt 1 has been canceled, CPU 1 can receive the INT terminal connected to the one of counters 5 and ₆ to which the short-term data C7 has been set.
When the value of data C ₇ and the value of counter 4 match,
Next interrupt processing, period _t8 , begins.

In period _t8 , since interrupt 1 was canceled in period _t7 , steps S102 to S1
03, the flag is inverted from "1" to "0". In step S104, the duty of the next cycle _T8 is set.
d ₈ is determined, and since the advance flag has become "0" in step S105, the process moves to step S106, where data A ₈ and B ₈ are calculated from the duty d ₈ using equations (1) and (2). , comparators 5 and 6 are set. Since the duty _d8 is less than 50, the process moves to step S110 and interrupt 2 is canceled. Since interrupt 2 has been released, CPU 1 can receive the INT terminal connected to the comparator of comparators 5 and 6, which is set to data B ₈ with a long period, and the value of data B ₈ matches the value of counter 4. The next interrupt occurs when

Thereafter, the operation shown in FIG. 3 is repeated in the same manner, and pulses P are continuously obtained from the Q terminal of the flip-flop circuit 8.

As described above, according to this embodiment, when the on-duty is continuously 50% or less, waveform creation processing is performed during the off period, so that sufficient processing time can be taken. Also, on duty is 50
% or more continues, waveform creation processing is performed during the on period, so sufficient processing time can be taken. Furthermore, when the on-duty changes from less than 50% to more than 50%, or from more than 50% to less, waveform creation processing is performed as soon as the next period's duty change is detected, so the pulse signal is continuously Duty can be varied.

Although the present invention has been described above with reference to embodiments, the following modifications are also possible.

For example, in the above embodiments, the counters, comparators, flip-flops, etc. have been explained as hardware, but they may also be configured as software.

Furthermore, although the duty has been described as being determined by the output of a sensor, for example, when the present invention is used in a signal generator, the duty can be set by an operation dial instead of a sensor.

Furthermore, although the duty setting boundary value is set to 50%, it can also be set to 20% or 80%, which is less than 50%.

〔Effect of the invention〕

As described above, according to the present invention, the simplicity and configuration,
In operation, a pulse signal with a continuously changing duty ratio can be output.

[Brief explanation of drawings]

FIG. 1 is a block diagram showing an embodiment of the duty control pulse generation circuit according to the present invention, FIG. 2 is a wiring diagram showing an example of the use of the circuit shown in FIG. 1, and FIG. 3 is a block diagram showing an example of the use of the circuit shown in FIG. Flowcharts illustrating the operation, FIGS. 4 and 5 are waveform diagrams illustrating the operation of the circuit shown in FIG. 1. 1...CPU, 4...Counter, 5, 6...Comparator, 8...Flip-flop.

Claims (1)

[Claims] 1. A duty control pulse generation circuit that changes the duty ratio of an output pulse signal in response to a change in input data and outputs the same, comprising: a count means for counting a clock signal; and a count value of the count means. and a set value, and when the two match, the first and second comparison means generate an output, and are reset by the output of the first comparison means,
a flip-flop means that is set by the output of the second comparison means; and a central control unit that performs interrupt processing according to the outputs of the first and second comparison means, and the central control unit performs interrupt processing in the interrupt processing. The duty ratio of the output pulse signal is calculated based on the input data, and if the duty ratio of the output pulse is less than or equal to a predetermined value, first data is used that determines the time from the falling edge of the output pulse signal to the next rising edge. Second data that determines the time from one fall of the output pulse signal to the next fall is set in the first and second comparing means, respectively, and when the second data and the count value match, The next interrupt processing is started, and when the duty ratio of the output pulse is greater than or equal to a predetermined value, third data that determines the time from the rise of the output pulse signal to the next fall, and from the rise of the output pulse signal to the next rise. and fourth data that determines the time of the count value are set in the first and second comparison means, respectively, and when the fourth data and the count value match, the next interrupt processing is started, and the output pulse When the duty ratio changes from below a predetermined value to above a predetermined value and from above to below a predetermined value, the next interrupt processing is started when the first and third data and the count value match. Control pulse generation circuit.