JPH0973404A - Watchdog timer circuit - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a watchdog timer circuit which securely puts program operation back in its normal state by entirely stopping the circuit operation of a microcomputer circuit itself and retrying it if the program runs away. SOLUTION: This circuit has a cyclic pulse monitor circuit which inputs cyclic pulses generated as a program on a CPU 2 operates normally, judges whether or not the program runs away from whether or not the cyclic pulses have periodicity, and outputs a reset trigger signal when judging that the program runs away, a program resetting means which receives the reset trigger signal from the cyclic pulse monitor circuit and outputs a reset signal stopping at least the program operation to the reset terminal of the CPU 2 at least once, and an oscillation circuit reset means which supplies a reset signal to the stand by terminal of the CPU 2 for a time longer than the effective time of the reset signal in synchronism with the reset signal from the program resetting means.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a watchdog timer circuit used to return a microcomputer (CPU) to a normal state when a program runs out of control.

[0002]

2. Description of the Related Art A conventional watchdog timer circuit of this type will be described with reference to a microcomputer circuit shown in FIG. That is, in FIG. 1, when the STBY terminal is supplied with, for example, a high-level signal, the microcomputer 2 changes the signal supplied to the input port PIN by a program that operates based on the clock pulse supplied from the oscillation circuit 1. Process and create control signals, etc., and output port P
Output from OUT. Further, the microcomputer 2 generates the P pulse generated by dividing the frequency of the clock pulse from the P1 terminal when the program operation is normally performed.
-The RUN signal is output to the watchdog timer circuit 3.

The watchdog timer circuit 3 comprises an edge detection / one-shot output circuit 12, an integrating circuit 4, a comparing circuit 5, and a first timer circuit 6, and a pulse signal supplied from the P-RUN terminal of the microcomputer 2. Edge is detected by the edge detection / one-shot output circuit 12,
After one-shot output, the integration circuit 4 performs integration (corresponding to frequency / voltage conversion here), and the integrated value is compared with a reference value by a comparison circuit 5, and if the integrated value is lower than the reference value, a micro The comparison circuit 5 supplies a reset trigger signal to the first timer circuit 6 upon determining that the computer 2 is running out of program. The first timer circuit 6 sets the output to the low level for a certain period of time each time the reset trigger signal is supplied from the comparison circuit 5, and supplies the reset signal to the reset terminal RST of the microcomputer 2 to cause the microcomputer 2 to operate. Reset the program operation to the initial state. A runaway detection circuit is formed by the integration circuit 4 and the comparison circuit 5 to determine whether or not the microcomputer 2 is running out of program. Further, the output of the comparison circuit 5 is configured to switch to the low level state not only once but periodically a plurality of times when the integrated output of the integrating circuit 4 falls below the reference value.

[0004]

However, in the above-mentioned microcomputer circuit, when the microcomputer 2 runs out of program, the program is returned to the initial state based on the reset signal from the watchdog timer circuit 3 and operates normally. Therefore, when the clock pulse that determines the operation timing of the program operation is abnormal, there is a problem that the reset operation is not returned to the normal operation no matter how many times it is supplied to the microcomputer 2. .

Therefore, the present invention has been made by paying attention to the above problems, and when the program goes out of control, the circuit operation of the microcomputer circuit itself is completely stopped and the program operation is surely performed again. The purpose is to obtain a watchdog timer circuit that returns to normal.

[0006]

A watchdog timer circuit according to the present invention inputs a periodic pulse created in accordance with a normal operation of a program of a CPU, and determines whether the periodic pulse has periodicity or not. A periodic pulse monitoring circuit that determines a program runaway and outputs a reset trigger signal when a program runaway is determined, and a reset signal that receives a reset trigger signal from the periodic pulse monitoring circuit and stops the program operation at least Times, said C
Program reset means supplied to the reset terminal of the PU and a reset signal from the program reset means, and for a period longer than the effective time of the reset signal,
And an oscillating circuit resetting means for supplying a reset signal to the standby terminal of the CPU.

[0007]

FIG. 1 shows the configuration of an embodiment according to the present invention. In these figures, the watchdog timer circuit 11 is different from that described in the conventional example of FIG.
The other components are the same as or equivalent to those shown in FIG. 3, and therefore, the same reference numerals are given and detailed description thereof is omitted.

That is, the watchdog timer circuit 11
Is composed of an edge detection / one-shot output circuit 12, an integration circuit 4, a comparison circuit 5, a first timer circuit 6, a falling edge detection circuit 7, a counter circuit 8, a delay circuit 9, a second timer circuit 10, and the like, The falling edge detection circuit 7 detects the falling edge of the reset trigger signal output from the comparison circuit 5 (see FIG. 2C), and the counter circuit 8 counts the number of detection times from 1 to 5. When the count value becomes 1, the output is set to the high level, and when it becomes 5, the count value is immediately reset to 0 and the output is set to the low level state (see FIG. 2D).

The delay circuit 9 delays the change in the output of the counter 8 and outputs it. That is, as shown in FIG. 2F, when the output of the counter circuit 8 changes to the low level, the change is delayed for t3 time, the output is changed to the low level only for a predetermined time, and then changed to the high level.

The second timer circuit 10 uses the falling edge of the signal (FIG. 2 (F)) output from the delay circuit 9 as a reference for a predetermined time t2 (> t3) immediately after the detection of the falling edge. Keep the output low level,
Then switch to high level. This second timer circuit 1
The output signal from 0 is the STB of the microcomputer 2.
By being supplied to the Y terminal, the microcomputer 2 stops the operation of the oscillation circuit 1 and is also supplied to the first timer circuit 6 to change the timer time of the first timer circuit 6 from t0 to t1 (> t2). And operate it (see FIG. 2 (H)).

In the above embodiment, the low level signal is supplied to the STBY terminal based on the output signal from the second timer circuit 10. However, the power supply to the microcomputer 2 and the oscillation circuit 1 is cut off using the same signal. It goes without saying that you can do it.

Next, the operation of the above configuration will be described. When the power is turned on and the microcomputer 2 operates based on the clock pulse signal from the oscillation circuit 1 (during the period T0 in FIG. 2A), the P-RUN signal is detected from the terminal P1 of the microcomputer 2 during this period. The signal is supplied to the integrating circuit 4 through the one-shot output circuit 12, but since it is a normal pulse signal, the integration result (FIG. 2B) exceeds the reference value of the comparing circuit 5, so the output of the comparing circuit 5 is output. Is always kept at a low level, and the microcomputer 2 is never reset.

Next, when the microcomputer 2 starts program runaway (during section T1 in FIG. 2A), the P-RU output from the terminal P1 of the microcomputer 2 is output.
Since the N signal is maintained at the low level or the high level and is no longer a pulse, the frequency / voltage conversion is not performed in the integrating circuit 4, and the output starts decreasing, and when the output falls below the reference value of the comparing circuit 5, the reset trigger signal becomes 1 timer circuit 6 and the falling edge detection circuit 7, and the first timer circuit 6 outputs 4
Until the reset pulse for the first time, the output from the comparison circuit 5 is in the same state, but for the fifth time, as shown in FIG.
The reset signal is maintained longer than the time t2 during which the reset signal is supplied to the Y terminal, and is extended until time t1. That is, the program is operated (reset is released) after the oscillation circuit 1 is in the normal oscillation state.

That is, the counter 8 counts the number of appearances of the falling edge of the reset trigger signal output from the comparison circuit 5, and when the fifth time is detected, the timing is delayed by the delay circuit 9 by t3 time. Let After the delay of t3 time, a signal for stopping the oscillation operation of the oscillation circuit 1 is supplied from the second timer circuit 10 to the STBY terminal of the microcomputer 2 for t2 time, and at the same time, the fifth reset is output from the first timer circuit 6. The signal generation time is extended to t1 hours.

[0015]

As described above, according to the present invention,
The operation of the microcomputer circuit is reset by resetting the program operation of the microcomputer and also the operation of the oscillator circuit that creates the clock pulse, so even if the oscillation frequency shifts or stops for some reason, it restarts. It is possible to obtain the effect of reliably returning to normal operation.

[Brief description of drawings]

FIG. 1 is a circuit block explanatory diagram of a microcomputer circuit for explaining an embodiment of the present invention.

FIG. 2 is a timing chart for explaining the operation of the watchdog timer circuit in FIG.

FIG. 3 is a circuit block diagram of a watchdog timer circuit used in a conventional microcomputer circuit.

[Explanation of symbols]

 1 Oscillation circuit 2 Microcomputer 3, 11 Watchdog timer circuit 4 Integration circuit 5 Comparison circuit 6, 10 Timer circuit 7 Falling edge detection circuit 8 Counter circuit 9 Delay circuit 12 Edge detection / one-shot output circuit

Claims (1)

[Claims] 1. A program runaway is determined by inputting a periodic pulse created in accordance with a normal operation of a program of a CPU (2) and determining whether the periodic pulse has periodicity or not. In this case, a periodic pulse monitoring circuit (4, 5) that outputs a reset trigger signal, and at least a reset signal that receives the reset trigger signal from the periodic pulse monitoring circuit and stops the program operation
The reset signal is supplied to the reset terminal of the CPU, and the reset signal is supplied to the standby terminal of the CPU in synchronization with the reset signal from the program reset means and for a period longer than the valid time of the reset signal. Oscillation circuit reset means (7, 8, 9, 10)
And a watchdog timer circuit.