JP3314791B2 - Synchronization method for multiprocessor systems - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a multiprocessor system having an error in an operation clock, and more particularly to a synchronization system for preventing a double interrupt.

[0002]

2. Description of the Related Art In recent years, as a FA system has become more sophisticated, a higher performance of a controller has been required. Therefore, a multiprocessor system has emerged in which the controllers are multiprocessors and the processors communicate with each other by interruption. By the way, when a clock pulse output from a main processor (hereinafter, referred to as a CPU) is used as a time reference signal for each CPU, no problem such as a change in the phase of the interrupt timing occurs. However, as the types of interrupts increase and the number of interrupt signal lines increases, the main CP
This U-led approach is no longer valid. Also, in a multiprocessor system, each CPU has a built-in clock pulse oscillator equivalent to each CPU.
A counter which generates an interrupt signal (hereinafter referred to as INTL) in each CPU in a cycle of a fraction of this integer in synchronism with an interrupt signal (real-time clock, hereinafter referred to as RTC) having a constant cycle to be transmitted to the CPU. Some of them synchronize interrupts of the entire system. This interrupt synchronization technique will be described with reference to FIG.

In FIG. 3, reference numeral 1 denotes a counter incorporated in each CPU for counting clock pulses. Counter 1
Counts the clock pulse CP, and the overflow signal RC is input to the load pin * LD via the NOR gate 4 to preset the count value of the counter 1 to 0 and output as an interrupt signal * INTL. Therefore, the counter 1 repeats the overflow and preset alternately generates an overflow signal RC having a predetermined period T _2. On the other hand, an interrupt signal * RTC with a period T ₁ sent from a certain CPU is input to the load pin * LD of the counter 1 via the inverter 5 and the NOR gate 4 to preset the count value of the counter 1 and to execute the interrupt. Signal * RT
Output as C. Now, as shown in FIG. 2A, the ratio between the cycle T ₁ of the interrupt signal * RTC and the cycle T ₂ of the interrupt signal * INTL generated at the time of the overflow is an integer value N (=
It is set in advance to be equal to 4). Therefore, in a certain period of the interrupt signal * INTL generated when the counter 1 overflows, the interrupt signal * RTC from a certain CPU as a load signal via the NOR gate 4
Is input to the counter 1 (hereinafter, this period is referred to as a synchronization period). Since the counter 1 is preset by the interrupt signal * RTC, the counting operation is performed by the interrupt signal * R
Forcibly synchronized by TC, interrupt signal * RTC
To output the interrupt signal * INTL period T ₂ in synchronism with the.

However, if the overflow signal of the counter 1 is used as it is as the interrupt signal * INTL, the following inconvenience occurs. In the synchronization period, the interrupt signal
The timing at which the * RTC and the interrupt signal * INTL are load-input to the counter 1 is actually very small even though the oscillators of the original clock pulses generating the interrupt signals * RTC and * INTL are equivalent. Phase shift, the interrupt signal * RTC causes the interrupt signal * IN
When inputting somewhat earlier than TL and interrupt signal * RTC
Is input somewhat somewhat later than the interrupt signal * INTL (FIG. 2B). In particular, when the latter interrupt signal * INTL is input to the counter 1 earlier than the interrupt signal * RTC, two interrupts of the interrupt signal INTL * and the interrupt signal * RTC are performed in a short time. The problem of double interrupts, which occur one after another, occurs. To solve this problem, the conventional system applies an interrupt mask to the interrupt signal * INTL in the synchronization period.
It is necessary to control the interrupt mask by a program, and there is a disadvantage that software becomes complicated.

[0005]

SUMMARY OF THE INVENTION An object of the present invention is to solve the above-mentioned drawbacks, and to generate individual interrupt signals synchronized with the single interrupt signal in respective CPUs.
An object of the present invention is to provide a synchronization method that does not allow a double interrupt.

[0006]

To solve the above problems [Means for Solving the Problems], synchronization scheme of the multiprocessor system according to the present invention, a processor for sending a first interrupt signal at a constant period T _1, the first receiving the interrupt signal, it in a multiprocessor system comprising a processor operating a plurality of unique clocks generated respectively a second interrupt signal of the T ₁ of the integer fraction one period T ₂ to be synchronized, the multiple each processor, said preset by the first interrupt signal, having a counter which overflows in a cycle T ₂ counts the clock pulses to generate a second interrupt signal output, the first The pulse width of the interrupt signal is a time width capable of absorbing a phase error between the operation clock pulse of the first interrupt signal and the clock pulse forming the second interrupt signal. It is an butterfly.

[0007]

In the synchronizing period, the interruption signal * RTC and the interruption signal * INTL occur one after another because a slight phase shift occurs in each oscillator of the clock pulse from which each signal is generated. Because of this, by setting the pulse width of the interrupt signal * RTC at a time when this phase error can be absorbed, the generation of the interrupt signal * INTL can be captured within the generation period of the interrupt signal * RTC. And the occurrence of a double interrupt can be prevented.

[0008]

DESCRIPTION OF THE PREFERRED EMBODIMENTS Embodiments of the present invention will be described with reference to the drawings.
I do. FIG. 1 shows a multiprocessor system according to the present invention.
FIG. 4 is a circuit diagram of a counter unit that operates. 1 is built into each CPU
Clock pulse from the same clock pulse generator
Counter, for example, TI company SN74LS1
A counter IC such as 61 is used. Counter 1 is clock
Counts the pulse CP and when it overflows the RC pin
Outputs an interrupt signal * INTL. On the other hand, a certain CPU
Period T sent from₁ * RTC is a load signal
Input to the load pin * LD and the total of counter 1
Preset the value to 0 and set the bus as an interrupt signal.
Sent to Therefore, counter 1 overflows
And the preset are alternately repeated, and the predetermined cycle T_Two Percent of
Generate the input signal * INTL. Above interrupt signal * RTC
Period T₁ And the interrupt signal * INTL cycle T_Two And the ratio (T ₁ 
/ T_Two ) Is preset to be equal to the integer value N
Interrupt signal * once every N cycles of INTL
* RTC and interrupt signal * INTL almost simultaneously
Output. Interrupt signal * INTL for other cycles
Only the signal is output via the knot circuit 2. This interrupt signal
Input to CPU or interrupt controller 8259
Is done.

Next, as shown in FIG. 2B, due to the phase shift of the clock pulse oscillator of each CPU, the interrupt signal *
An embodiment of the present invention will be described for the case where the RTC is slower than the interrupt signal * INTL. Now, assuming that the period T ₁ of the interrupt signal * RTC is 8 ms, the period T of the interrupt signal * INTL is T
₂ is ₂ ms to interpolate this. By the way, since the accuracy of a normal oscillator is about 100 ppM, an interrupt signal *
If applied to the clock pulse oscillator that creates the RTC, an error of 0.8 μs will occur. This error is the same for the clock pulse oscillator that is the source of the interrupt signal * INTL. Therefore, if the safety count is multiplied by the minus and plus components of the error, an interrupt signal * RTC having a pulse width of 4 μs is generated, so that the interrupt signal * INTL in the synchronization cycle becomes equal to the interrupt signal * RTC. It will be included during the outbreak period. Therefore, even in the case of FIG. 2B, the interrupt signal * RTC includes the interrupt signal * INTL without causing a double interrupt, so that the interrupt factor of the interrupt signal * INTL is eliminated, and the interrupt signal * INTL is eliminated. R
After executing the interrupt processing by TC, the interrupt signal * INT
What is necessary is just to process the original interrupt processing by L.

[0010] Regarding the pulse width of the interrupt signal * RTC,
It can be determined at the design stage based on a clock pulse oscillator built in the CPU, and the pulse width of the interrupt signal * RTC sent to each CPU may be set using a known pulse width adjustment circuit.

[0011]

As described above, according to the present invention,
Real-time clock (RT) sent to each processor
Only by adding hardware to increase the pulse width of C), it is possible to synchronize interrupts in a multiprocessor system and prevent double interrupts.

[Brief description of the drawings]

FIG. 1 is a circuit diagram of a counter unit for implementing a synchronization method according to the present invention.

FIG. 2A is a waveform diagram showing a relationship between an interrupt signal * RTC and an interrupt signal * INTL. B: Waveform diagram showing the relationship between two interrupt signals in the synchronization cycle.

FIG. 3 is a circuit diagram of a counter unit for implementing a conventional synchronization method.

[Explanation of symbols]

 1 counter 2 knot circuit 3 pulse width adjustment circuit 4 NOR gate circuit 5 inverter circuit

Claims (1)

(57) [Claims] 1. A processor for transmitting a first interrupt signal at a constant period T ₁ , a processor for receiving the first interrupt signal, and synchronizing with the first interrupt signal, a _second period T ₂ of an integer fraction of T ₁ . A multiprocessor system comprising a plurality of independent clock-operating processors each generating two interrupt signals, wherein each of the plurality of processors is preset by the first interrupt signal and counts clock pulses. Period T ₂
A counter which overflows and generates and outputs a second interrupt signal. The pulse width of the first interrupt signal is determined by the operation clock pulse of the first interrupt signal and the second interrupt signal. A synchronization method in a multiprocessor system, which has a time width capable of absorbing a phase error with a clock pulse being formed.