JP4490337B2 - Resynchronizable interrupt generator - Google Patents

Description

  The present invention relates to a resynchronizable interrupt generation circuit, and more particularly, to an interrupt generation circuit that can resynchronize internal interrupt timing by an external synchronization signal and prevents continuous generation of interrupt signals.

An integrated circuit device having a plurality of processor cores therein has been proposed. For example, Patent Literatures 1 and 2 are used. In an integrated circuit device incorporating such a processor core, the built-in interrupt generation circuit may give an interrupt signal to the built-in processor core at a predetermined cycle. In this case, the interrupt generation circuit generates an internal clock based on an external clock supplied from the outside, operates the counter in synchronization with the internal clock, and internally responds to a predetermined count value of the counter. Generate an interrupt signal. By incorporating a clock generator that generates an internal clock from an external clock, the internal clock is continuously generated even if the external clock is interrupted for some reason, and the generation of an interrupt signal can be continued internally. In this case, however, it is necessary to resynchronize the operation of the internal counter by supplying a synchronization signal from the outside in consideration of the phase shift of the internal clock by the built-in clock generator. It is also necessary to resynchronize with the timing of a new external synchronization signal when the external synchronization signal is switched.
Japanese Examined Patent Publication No. 6-1464 Special table 2003-507217 gazette

  In the above interrupt generation circuit, the internal interrupt signal generation timing can be resynchronized by clearing the internal counter in response to the external synchronization signal. However, when the timing of the external synchronization signal coincides with that immediately after the internal counter clear operation, the internal counter is cleared again. In this case, if an internal interrupt signal is generated in response to the clear operation of the internal counter, the internal interrupt signal is generated continuously. Interrupt signals generated continuously within a short time may not be received depending on the built-in processor cores, and the interrupt control of a plurality of processor cores is different, resulting in inconsistencies in interrupt operations between processors.

  SUMMARY OF THE INVENTION An object of the present invention is to provide an interrupt generation circuit that prevents occurrence of continuous interrupts in a short time.

  To achieve the above object, according to the first aspect of the present invention, an n-ary counter that circulates from 0 to n-1 in synchronization with a clock and performs a counting operation, and a predetermined count value of the counter And an interrupt signal generator for generating an interrupt signal in response to the delay synchronization signal having a delay circuit for delaying the external synchronization signal by k clocks, wherein the counter is delayed by the delay circuit. In response, the count value “k” is loaded, and the interrupt signal generator generates the interrupt signal in response to the clear value of the counter.

  According to the first aspect described above, even if the external synchronization signal is supplied at the timing when the counter is cleared, the delay circuit sets the counter to the count value “k” with a delay of k clocks from the timing of the external synchronization signal. Therefore, it is possible to prevent the counter from continuously becoming the clear value “0” in a short time, and it is possible to prevent occurrence of continuous interrupts in a short time.

  In the first aspect, according to a preferred embodiment, the delay circuit delays the external synchronization signal by one clock, and the counter loads the count value “1” in response to the delay synchronization signal. According to another preferred embodiment, it further comprises a clock generator which is supplied with an external clock and supplies a clock to the counter. According to this, even if the external synchronization signal and the external clock are interrupted, the clock is generated internally, so that the generation of the interrupt signal can be continued.

  In order to achieve the above object, according to a second aspect of the present invention, an n-ary counter that circulates from 0 to n-1 in synchronization with a clock and performs a counting operation, and a predetermined count value of the counter And an interrupt signal generator for generating an interrupt signal in response to the delay synchronization signal having a delay circuit for delaying the external synchronization signal by k clocks, wherein the counter is delayed by the delay circuit. In response to the counter value, the count value is cleared to "0", and the interrupt signal generator generates the interrupt signal in response to the count value "nk" of the counter.

  According to the second aspect, even when the counter does not have a load function but has a clear function, the counter is substantially loaded with a clear value “0” at a timing delayed by k clocks from the timing of the external synchronization signal. Therefore, it is possible to prevent the interruption signal generated at the count value “n−k” from being generated continuously.

  In the interrupt generation circuit, continuous interrupt generation in a short time can be prevented.

  Hereinafter, embodiments of the present invention will be described with reference to the drawings. However, the technical scope of the present invention is not limited to these embodiments, but extends to the matters described in the claims and equivalents thereof.

  FIG. 1 is a diagram showing the configuration and operation of an integrated circuit device incorporating an interrupt generation circuit. The integrated circuit device LSI of FIG. 1A includes four processor cores DSP # 1 to DSP # 1-4, and includes an interrupt generation circuit 10 that generates an interrupt signal IRQ. The interrupt generation circuit 10 is supplied with the external clock ECLK and the external synchronization signal SYNC from the clock supply unit 20 that supplies the external clock ECLK and the synchronization signal supply unit 22 that supplies the external synchronization signal SYNC, respectively. . The interrupt generation circuit 10 is an n-ary counter 12 that circulates and counts from 0 to n-1 in response to the internal clock ICLK, and decodes the count value of the counter 12 and outputs an interrupt signal when the count value is a predetermined value. And an interrupt generator 14 for generating an IRQ. Furthermore, the interrupt generation circuit 10 has a clock generator 16 that is supplied with the external clock ECLK and generates the internal clock ICLK at a period equivalent to the external clock ECLK.

  FIG. 1B shows an operation example of the interrupt generation circuit. In synchronization with the internal clock ICLK generated by the clock generator 16, the octal counter 12 counts the count values 0-7. As an example, the interrupt signal generator 14 outputs the interrupt signal IRQ at the timing of the count values “0” and “4”. In normal operation, the external clock ECLK and the internal clock ICLK have the same timing. However, the counter 12 is cleared at the timing of the external synchronization signal SYNC so that the timing of the interrupt signal is adjusted to a desired timing even if there is a timing difference between both clocks.

  By incorporating the clock generator 16, even if the supply of the external clock ECLK is interrupted due to a failure of the clock supply unit 20, the supply of the internal clock ICLK is continued and the generation of the interrupt signal IRQ can be maintained. Even when the synchronization signal supply unit 22 breaks down, the generation of the interrupt signal can be maintained in the same manner. After switching to another synchronization signal supply unit 24, the counter 12 is cleared at the timing of the external synchronization signal SYNC therefrom, and the counter is resynchronized.

  FIG. 2 is an operation timing chart of the interrupt generation circuit of FIG. In this example, the counter is a 256-ary counter that counts from 0 to 255, and the interrupt signal generator 14 generates the interrupt signal IRQ at the timing when the count value becomes “0”. FIG. 2A shows the timing of normal operation. That is, the external synchronization signal SYNC is supplied at the timing of the count value “255” at time t1, and is input as the clear signal CLR at time t2 in synchronization with the next clock ICLK to clear the count value to “0”. In response to the clear account value “0”, the interrupt signal generator 14 outputs an interrupt signal IRQ. Thus, if the external synchronization signal SYNC is generated at the timing of the count value “255”, the counter is cleared at the next clock timing, and the counter is normally cleared (clearing to the count value “0”). And an interrupt signal IRQ is generated with a counter period (256 clocks). The above is the normal operation.

  On the other hand, FIG. 2B shows an example of malfunction. When the external synchronization signal SYNC is delayed and supplied at the timing of the count value “0” at time t2, it is input as the clear signal CLR at time t3 in synchronization with the next clock ICLK, and the count value is cleared to “0”. . Therefore, the interrupt signal IRQ is generated continuously at time t2 when the count value is cleared to “0” by normal counter operation and at time t3 cleared by the external synchronization signal immediately after that. Of the processors supplied with this interrupt signal, for example, the processor DSP # 1 can receive a continuous interrupt signal IRQ, but another processor DSP # 2 immediately receives the interrupt signal IRQ. During the predetermined period, there is a case where only the first of the continuous interrupt signals IRQ is received and the second interrupt signal cannot be received because the interrupt prohibition mode is set. As a result, the processor DSP # 1 executes the interrupt operation twice, and the processor DSP # 2 only executes the interrupt operation once, so that the interrupt operations of both processors become inconsistent, resulting in malfunction. . For example, when interrupt operations are performed in cooperation between processors, a malfunction may be caused.

  Therefore, an interrupt generation circuit is configured so that it is possible to avoid the continuous generation of the interrupt signal IRQ within a short time as described above, regardless of the timing of the external synchronization signal SYNC. It is desirable.

  FIG. 3 is a block diagram of an integrated circuit device having an interrupt generation circuit in the present embodiment. The integrated circuit device LSI includes a plurality of processor cores DSP # 1 to DSP # 1 to 4 as in FIG. The interrupt generation circuit 10 includes a counter 12 that sequentially increments a count value in synchronization with the internal clock ICLK, and an interrupt signal generator 14 that generates an interrupt signal IRQ when the count value CUNT of the counter 12 is a predetermined value. A clock generator 16 that is supplied with the external clock ECLK and generates an internal clock ICLK having the same frequency as the external clock ECLK, a delay circuit 18 that delays the external synchronization signal SYNC by one clock of the internal clock ICLK, and a load value register 19. . Then, the load value “1” is loaded into the counter 12 at the timing when the delayed synchronization signal is supplied to the load terminal of the counter 12. The interrupt signal generator 14 has a function of decoding the count value. For example, the interrupt signal generator 14 decodes the cleared count value “0” to generate an interrupt signal. An interrupt signal may be generated with another count value.

  In a generalized interrupt generation circuit described later, the load value of the load value register 19 is k, and the delay circuit 18 delays the external synchronization signal SYNC for a period of k clocks.

  As in FIG. 1, an external clock supply unit 20, an external synchronization signal supply unit 22, and a spare external synchronization signal supply unit 24 are provided outside. The basic operation is the same as the timing chart of FIG.

  Unlike the circuit of FIG. 1, the interrupt generation circuit of the present embodiment is supplied to the load terminal LOAD of the counter 12 with the external synchronization signal SYNC delayed by one clock by the delay circuit 18. Then, the counter 12 loads the load value “1” of the load value register 19 as the input count value IN at the timing when the delay synchronization signal is supplied to the load terminal LOAD. The external synchronization signal SYNC is supplied with the timing of the count value “255” as in FIG. Thus, in the resynchronization operation by the external synchronization signal SYNC, the counter 12 only loads the load value “1” and does not become the clear value “0”. Therefore, in a short time regardless of the timing of the external synchronization signal SYNC. Generation of a continuous interrupt signal IRQ does not occur.

  4, 5 and 6 are operation timing charts of the interrupt generation circuit of FIG. FIG. 4 shows a normal operation. When the external synchronization signal SYNC is supplied at the timing of the count value “255” at the time t1, the delay circuit 18 delays one clock and loads it at the timing of the count value “0” at the time t2. A synchronization signal is supplied to the terminal LOAD. In response to this, the counter 12 loads the load value “1” at time t3 which is the timing of the next internal clock. Since the counter 12 is cleared to the count value “0” by the normal counter operation at time t2, the interrupt signal generator 14 outputs the interrupt signal IRQ at that timing. Thus, by delaying the external synchronization signal by one clock and loading “1” without clearing the count value to “0” at that timing, the normal operation becomes the same as in FIG.

  FIG. 5 shows a case where the timing of the external synchronization signal SYNC is delayed and shifted to the timing of the count value “0”. When the external synchronization signal SYNC is supplied at the timing of the count value “0” at time t2, the load signal LOAD is supplied at time t3 delayed by one clock. Then, the counter 12 loads the load value “1” at the timing of the next internal clock (time t4). As a result, the counter 12 repeats the count value “1” at times t3 and t4. Therefore, the period at that time is increased by 257 clocks and 1 clock. However, after the interrupt signal IRQ is generated with the count value “0”, the counter is not cleared again, so that the interrupt signal IRQ is not generated continuously.

  Since the next external synchronization signal SYNC is supplied at the timing of the count value “255” after 256 clocks, the normal operation is resumed from there. When the timing of the external synchronization signal SYNC is further delayed, the counter 12 becomes the load value “1” and only the cycle becomes longer, and the count value does not repeat “0” in a short time.

  FIG. 6 shows a case where the timing of the external synchronization signal SYNC is advanced to a timing of the count value “254”. When the external synchronization signal SYNC is supplied at the count value “254” at time t0, the load signal LOAD is supplied at the count value “255” at time t1 after one clock delay. In response to this, the load value “1” is loaded into the counter 12 at the time t2 of the timing of the next internal clock. Therefore, in this case, the count value “0” is not cleared and the corresponding interrupt signal IRQ is not generated. Then, since the next external synchronization signal SYNC is supplied at the timing of the count value “255” after 256 clocks, it returns to normal operation. Thus, the interrupt signal IRQ is not generated only once, but is re-synchronized from the next cycle to return to the normal operation.

  When the timing of the external synchronization signal SYNC is further advanced, the counter 12 becomes the load value “1” at the earlier timing and only the number of clocks until the next normal operation is reduced. Is not repeated.

  FIG. 7 is an operation timing chart when the present embodiment is generalized. When generalized, the counter is an n-ary counter with a count value of 0 to n−1, the delay circuit 18 of FIG. 3 is delayed by k clocks, and the load value register 19 stores the load value “k”. Yes. In the normal operation, the external synchronization signal SYNC is supplied from the outside at the timing when the count value is “n−1”.

  FIG. 7A shows a normal operation, in which the external synchronization signal SYNC is supplied at the timing t1 of the maximum count value “n−1” of the counter 12, and the counter is cleared to the count value “0” at the next time t2. And an interrupt signal IRQ is generated. Then, the load signal LOAD is supplied at time t3 (count value “k−1”) after being delayed by k clocks from time t1, and the counter loads the load value “k” at time t4 of the next clock timing. . Therefore, no change occurs in the normal count operation of the counter 12.

  FIG. 7B shows a case where the external synchronization signal SYNC is supplied at a timing t2 of the count value “0” with a delay of one clock. When the external synchronization signal SYNC is supplied at time t2, it is delayed by k clocks, and the load signal LOAD is supplied at the timing t4 of the count value “k”. In response to this, the counter loads the load value “k” at time t5 of the next clock timing. Therefore, the count value “k” continues at times t4 and t5. However, since the count value “0” is generated only once, the interrupt signal IRQ is only generated at that timing. In the cycle in which the count value “k” is loaded, it becomes longer by one clock, the external synchronization signal SYNC is supplied at the timing of the next count value “n−1” after 256 clocks, and the same normal operation as in FIG. Return to.

  Since the operation when the external synchronization signal SYNC is advanced can be understood from the comparison with FIG. 6, the description thereof is omitted here.

  FIG. 8 is a block diagram of an integrated circuit device having an interrupt generation circuit in the second embodiment. In the interrupt generation circuit 10 of the second embodiment, the load function of the counter 12 is not used, but instead, the load value “0” is substantially loaded using the clear function. The delay circuit 18 delays the external synchronization signal SYNC by one clock as in the first embodiment. However, since the load value “0” is substantially loaded using the clear function, the external synchronization signal SYNC is supplied at the timing of the count value “254” in the normal operation, and the count after one clock delay is obtained. With the value “255”, the counter receives the synchronization signal as a clear signal, and the counter performs a clear operation after one clock. Further, since the load value is substantially “0”, the interrupt signal generator 14 having a decoder function generates the interrupt signal IRQ with “255” instead of the count value “0”. That is, the operation of FIGS. 3 to 6 is performed at a timing one clock earlier.

  9, FIG. 10 and FIG. 11 are operation timing charts of the interrupt generation circuit of FIG. FIG. 9 shows a normal operation, and the external synchronization signal SYNC is supplied at the timing of the count value “254” at time t0, delayed by one clock in the delay circuit 18 and cleared at the timing of the count value “255” at time t1. It is supplied to the counter as a signal. At time t2 after one clock, the counter clears to the count value “0”. The interrupt signal generator 14 having a decoder function generates an interrupt signal IRQ at the timing of the count value “255”.

  FIG. 10 shows a case where the timing of the external synchronization signal SYNC is delayed and shifted to the timing of the count value “255”. When the external synchronization signal SYNC is supplied at the timing of the count value “255” at time t1, the clear signal CLR is supplied at time t2 delayed by one clock. Then, at the time t3 of the timing of the next internal clock, the counter 12 clears to the count value “0”. As a result, the counter 12 repeats the count value “0” at times t2 and t3. Therefore, the counter cycle at that time is 257 clocks, which is longer by one clock. However, after the interrupt signal IRQ is generated at the count value “255”, the counter does not become the count value “255” again, so that the interrupt signal IRQ is not generated continuously.

  If the external synchronization signal SYNC is supplied with a delay of one clock, the cycle becomes as long as 257 clocks. However, in the next cycle, the external synchronization signal SYNC is supplied with a count value “254” after 256 clocks. Return. Further, when the timing of the external synchronization signal SYNC is further delayed, the counter 12 is cleared to “0” and the cycle is only lengthened, and the count value “255” that generates an interrupt signal is repeated in a short time. There is nothing.

  FIG. 11 shows a case where the timing of the external synchronization signal SYNC is advanced and shifted to the count value “253”. In the second cycle in the figure, when the external synchronization signal SYNC is supplied with the count value “253”, the clear signal CLR is supplied with the count value “254” at time t0 after one clock delay. In response to this, the counter 12 is cleared to the clear value “0” at the time t1 of the next internal clock timing. Therefore, in this case, the counter does not become the count value “255”, and the corresponding interrupt signal IRQ is not generated. Since the next external synchronization signal SYNC is supplied at the timing of the count value “254” after 256 clocks, the normal operation is resumed. Thus, the interrupt signal IRQ is not generated only once, but is re-synchronized from the next cycle to return to the normal operation.

  When the timing of the external sync signal SYNC is further advanced, the counter 12 is cleared to “0” at the earlier timing and only the number of clocks until the next normal operation is reduced, and an interrupt signal is generated in a short time. The count value “255” to be repeated is not repeated.

  FIG. 12 is an operation timing chart when the second embodiment is generalized. When generalized, the counter is an n-ary counter with a count value of 0 to n−1, the delay circuit 18 of FIG. 8 is delayed by k clocks, and the interrupt signal generator 14 has a count value “n−k”. An interrupt signal IRQ is generated at the timing. In the normal operation, the external synchronization signal SYNC is supplied from the outside at the timing when the count value is “n−k−1”. It is the same that the counter performs a clear operation in response to the delayed external synchronization signal.

  FIG. 12A shows a normal operation, where the external synchronization signal SYNC is supplied at the timing t0 of the count value “n−k−1” of the counter 12, and the count value “n−k” at the next time t1 An interrupt signal IRQ is generated at the timing. Then, the clear signal CLR is supplied at time t3 (count value “n−1”) after being delayed by k clocks from time t0, and the counter is cleared to the count value “0” at time t4 of the next clock timing. The Therefore, no change occurs in the normal count operation of the counter 12.

  FIG. 12B shows a case where the external synchronization signal SYNC is supplied at the timing t1 of the count value “n−k” with a delay of one clock. In the second cycle in the figure, when the external synchronization signal SYNC is supplied at time t1, it is delayed by k clocks, and the clear signal CLR is supplied at the timing of the count value “0” at time t4. In response to this, the counter is cleared to the clear value “0” at time t5 of the next clock timing. Therefore, the clear value “0” continues. However, since the count value “n−k” generated by the interrupt signal is generated only once, only the interrupt signal IRQ is generated at that timing. In this second cycle, the external synchronization signal SYNC is supplied at the timing of the count value “n−k−1” after n clocks from the time t1, and the same normal operation as in FIG. Return (not shown).

  Since the operation when the external synchronization signal SYNC is advanced can be understood from the comparison with FIG. 11, the description thereof is omitted here.

  FIG. 13 is a configuration diagram of an integrated circuit device having an interrupt generation circuit according to the third embodiment. In this example, the internal clock generator 16 always generates the internal clock ICLK without receiving the supply of the external clock, and the resynchronization operation of the interrupt generation circuit 10 having the counter 12 is performed by the external synchronization signal SYNC. Otherwise, the configuration is the same as in FIG.

  Similarly, in the configuration of FIG. 8, the internal clock generator 16 may always generate an internal clock without receiving an external clock.

  As described above, in the first embodiment, an interrupt signal is generated at the timing of the count value “0”, and the count value “k” is loaded by delaying the external synchronization signal by k clocks. Therefore, the count value “0” of the counter is prevented from being repeated. In the second embodiment, an interrupt signal is generated at the timing of the count value “n−k”, the external synchronization signal is delayed by k clocks, and the counter is cleared to the count value “0”. Since it did in this way, it is prevented that count value "nk" is repeated. In either case, by setting k = 1, the delay circuit can be a simple circuit having a one-clock delay.

  The above embodiment is summarized as follows.

(Supplementary note 1) An n-ary counter that circulates from 0 to n−1 in synchronization with the clock, and an interrupt signal generator that generates an interrupt signal in response to a predetermined count value of the counter, In an interrupt generation circuit having
A delay circuit for delaying the external synchronization signal by k clocks; the counter loads a count value “k” in response to the delay synchronization signal delayed by the delay circuit; and the interrupt signal generator clears the counter An interrupt generation circuit for generating the interrupt signal in response to a value.

(Appendix 2) In Appendix 1,
The delay generation circuit delays an external synchronization signal by one clock, and the counter loads a count value “1” in response to the delay synchronization signal.

(Appendix 3) In Appendix 1,
An interrupt generation circuit further comprising a clock generator which is supplied with an external clock and supplies an internal clock to the counter.

(Appendix 4) In Appendix 3,
The external synchronizing signal is supplied at a timing of a count value “n−1” in normal operation and is supplied every n external clocks.

(Supplementary Note 5) An n-ary counter that circulates from 0 to n-1 in synchronization with the clock, and an interrupt signal generator that generates an interrupt signal in response to a predetermined count value of the counter, In an interrupt generation circuit having
A delay circuit for delaying the external synchronization signal by k clocks; the counter is cleared to a count value “0” in response to the delay synchronization signal delayed by the delay circuit; and the interrupt signal generator is configured to count the counter An interrupt generation circuit for generating the interrupt signal in response to a value “n−k”.

(Appendix 6) In Appendix 5,
The delay circuit delays an external synchronization signal by one clock, and the interrupt signal generator generates the interrupt signal in response to a count value “n−1” of the counter. .

(Appendix 7) In Appendix 5,
An interrupt generation circuit further comprising a clock generator which is supplied with an external clock and supplies an internal clock to the counter.

(Appendix 8) In Appendix 7,
The external synchronization signal is supplied at a timing of a count value “n−k−1” in a normal operation, and is supplied every n external clocks.

It is a figure which shows the structure and operation | movement of an integrated circuit device which incorporates an interrupt generation circuit. FIG. 2 is an operation timing chart of the interrupt generation circuit of FIG. 1. It is a block diagram of the integrated circuit device which has the interrupt generation circuit in this Embodiment. FIG. 4 is an operation timing chart of the interrupt generation circuit of FIG. 3. FIG. 4 is an operation timing chart of the interrupt generation circuit of FIG. 3. FIG. 4 is an operation timing chart of the interrupt generation circuit of FIG. 3. It is an operation | movement timing diagram at the time of generalizing this Embodiment. It is a block diagram of the integrated circuit device which has the interrupt generation circuit in 2nd Embodiment. FIG. 9 is an operation timing chart of the interrupt generation circuit of FIG. 8. FIG. 9 is an operation timing chart of the interrupt generation circuit of FIG. 8. FIG. 9 is an operation timing chart of the interrupt generation circuit of FIG. 8. It is an operation | movement timing diagram at the time of generalization of 2nd Embodiment. It is a block diagram of the integrated circuit device which has the interrupt generation circuit in 3rd Embodiment.

Explanation of symbols

LSI: Integrated circuit device DSP: Processor core 10: Interrupt generation circuit IRQ: Interrupt signal 12: Counter 14: Interrupt signal generator 16: Clock generator 18: Delay circuit 19: Load value register LOAD: Load terminal SYNC: External synchronization signal ICLK: Internal clock

Claims (4)

An interrupt having an n-ary counter that circulates from 0 to n-1 in synchronization with the clock and an interrupt signal generator that generates an interrupt signal in response to a predetermined count value of the counter In the generator circuit,
The counter resynchronizes in response to an external synchronization signal,
Said external synchronizing signal has a delay circuit for k clock delay, the counter is resynchronized by loading a count value "k" in response to the delayed synchronization signal delayed by the delay circuit, the interrupt signal generator Generates an interrupt signal in response to a clear value of the counter. In claim 1,
The delay generation circuit delays an external synchronization signal by one clock, and the counter loads a count value “1” in response to the delay synchronization signal. An interrupt having an n-ary counter that circulates from 0 to n-1 in synchronization with the clock and an interrupt signal generator that generates an interrupt signal in response to a predetermined count value of the counter In the generator circuit,
The counter resynchronizes in response to an external synchronization signal,
Said external synchronizing signal has a delay circuit for k clock delay, the counter is cleared and re-synchronization with the count value "0" in response to the delayed synchronization signal delayed by the delay circuit, the interrupt signal generator Generates an interrupt signal in response to a count value “n−k” of the counter. In claim 3,
The delay circuit delays an external synchronization signal by one clock, and the interrupt signal generator generates the interrupt signal in response to a count value “n−1” of the counter. .

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