JPH08139575A - Pulse output circuit - Google Patents

Abstract

PURPOSE: To output highly accurate pulse signals by providing first and second registers and first and second matching circuits, changing a second value stored in the second register and arbitrarily controlling the output timing of third signals. CONSTITUTION: A counter 1 inputs clocks CLK and counts them. A matching circuit 2 detects whether or not a value stored in a register 3 matches the value counted by the counter 1, and when they match, outputs matching signals to the reset terminal R of an FF 4. The matching circuit 5 detects whether or not the value stored in the register 6 matches the value counted by the counter 1, and when they match, outputs interruption request signals. The FF 4 outputs the PWM pulses for controlling an external equipment of a cycle corresponding to the overflow output of the counter 1 and the matching signals from the matching circuit 2 by outputting H when pulses are inputted to a set terminal S and outputting L when the pulses are inputted to the terminal R.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a pulse output circuit, and more particularly to a pulse output circuit incorporated in, for example, a one-chip microcomputer.

[0002]

2. Description of the Related Art For example, Japanese Unexamined Patent Publication No. 2-165721 discloses a prior art of a pulse output circuit incorporated in a one-chip microcomputer. This pulse output circuit is a so-called PWM output circuit that controls the cycle and duty ratio of pulse output, and can generate various pulses according to the external device to be controlled.

That is, the pulse output circuit shown in this document counts clocks by a counter and sets or resets a flip-flop every time the counted value reaches a value stored in two registers. , A pulse having a desired duty ratio is output from the flip-flop.

Further, this type of pulse output circuit also outputs an interrupt request signal for interrupting the internal CPU, in addition to the pulse for controlling the external equipment. Specifically, here, the signal at the time of setting the pulse output for setting the flip-flop is used as the interrupt request signal to the CPU. As a result, when the value counted by the counter reaches the value stored in one of the registers, an interrupt request signal is output and the CPU performs interrupt processing. The interrupt request signal to the CPU can also be performed by a pulse output signal for resetting the flip-flop.

[0005]

However, in such a conventional pulse output circuit, the interrupt request signal can be generated only when the pulse output is set or reset. Therefore, the interrupt request signal is generated by the pulse output generation operation, and there is a problem that the output pulse of the interrupt request signal of the pulse output circuit cannot be controlled with high accuracy.

The present invention solves the above-mentioned drawbacks of the prior art, and generates a predetermined signal including an interrupt request signal at an arbitrary point in the pulse signal cycle without being affected by the timing of the pulse output signal generating operation. By enabling
An object of the present invention is to provide a pulse output circuit capable of outputting a highly accurate pulse signal.

[0007]

In order to solve the above-mentioned problems, the present invention counts input clocks and outputs a first signal when the count value reaches a predetermined value, and a counter.
The first register that stores the first value, which is a numerical value within the range counted by the counter, is compared with the count value of the counter and the first value stored in the first register, and these values match. In the case, a first matching circuit that outputs a second signal, a second register that stores a second value that is a numerical value within a range that the counter counts, and a count value of the counter and the second register A second matching circuit that compares the stored second value and outputs a third signal when these values match, and a second signal from the first matching circuit that inputs the first signal from the counter And a pulse output section for outputting a pulse having a pulse width corresponding to these signals. In this circuit, the output timing of the third signal is arbitrarily controlled by changing the second value stored in the second register.

Further, a counter that counts the input clock and outputs a first signal when the count value reaches a predetermined value and a first value that is a numerical value within a range counted by the counter are stored. No. 1 register, a second register that stores a second value that is a numerical value within the range counted by the counter, and a second register that selects the first register when the input selection signal is the first selection signal. When the signal is a signal, the first selector that selects the second register is compared with the value stored in the register selected by the first selector and the count value of the counter, and if these values match, they match. A match circuit that outputs a signal and a match signal from the match circuit when the select signal is the first select signal outputs the second signal, and a match circuit outputs when the select signal is the second select signal. If you input the match signal of A second selector that outputs a signal; and a pulse output unit that inputs the first signal from the counter and the second signal from the second selector and outputs a pulse having a pulse width corresponding to these signals. Have. The output timing of the third signal is arbitrarily controlled by changing the second value stored in the second register.

[0009]

According to the present invention, when the counted clock reaches a predetermined value, the counter sends the first signal to the pulse output section to change the value of the output pulse. Also, the counted value is the first
When the value stored in the register is reached, the second signal is sent to the pulse output section and the value of the output pulse changes. An output pulse having a cycle corresponding to the first signal and the second signal is output from the pulse output unit. On the other hand, when the counted clock reaches the value stored in the second register, the third signal becomes the first signal.
Are output without being affected by the timings of the first signal and the second signal.

Further, according to the present invention, when the counted clock reaches a predetermined value, the counter sends the first signal to the pulse output section to change the value of the output pulse. Further, when the counted value reaches the value stored in the first register while the first register is selected by the first selector, the second signal is sent to the second selector and is transmitted through this. The second signal is sent to the pulse output section and the value of the output pulse changes. An output pulse having a cycle corresponding to the first signal and the second signal is output from the pulse output unit. On the other hand, when the counted clock reaches the value stored in the second register while the second register is selected by the first selector, the third signal is sent to the second selector and the first signal is sent. The signal is output without being affected by the timing of the signal and the second signal.

[0011]

Embodiments of the pulse output circuit according to the present invention will now be described in detail with reference to the accompanying drawings. Referring to FIG. 1, there is shown a circuit diagram showing an embodiment of a pulse output circuit according to the present invention. The pulse output circuit shown in the figure is built in, for example, a one-chip microcomputer or the like, outputs a PWM pulse for controlling an external device, and requests an interrupt to an internal CPU (not shown) which is a control unit. Output a signal.

In FIG. 1, the counter 1 has a clock CL.
It is an n-bit (n is a natural number) free-run counter that inputs K and counts it. The output side of the counter 1 is connected to the set terminal S of the flip-flop 4 and outputs an overflow output OVF (hereinafter referred to as OVF output) to the set terminal S when the counted value overflows. The counter 1 is also connected to the matching circuits 2 and 5 and outputs the count value to these matching circuits 2 and 5.

The coincidence circuit 2 is an n-bit coincidence detection circuit which is connected to the register 3 and detects whether or not the value stored in the register 3 coincides with the value counted by the counter. The matching circuit 2 is also connected on the output side to the reset terminal R of the flip-flop 4 and outputs a matching signal to the reset terminal R of the flip-flop 4 when the value stored in the register 3 and the value counted by the counter match.

The coincidence circuit 5 is an n-bit coincidence detection circuit which is connected to the register 6 and detects whether or not the value stored in the register 6 coincides with the value counted by the counter. When the matching circuit 5 detects a match between these values,
Output an interrupt request signal.

The registers 3 and 6 are the same n-bit registers as the n-bit free-run counter 1. These registers 3 and 6 are connected to a data bus 9, and an arbitrary value is set via this bus 9.

The flip-flop 4 is a set-reset type flip-flop having a set terminal S and a reset terminal R. The flip-flop 4 outputs "H" when a pulse is input to the set terminal S and outputs "L" when a pulse is input to the reset terminal R, so that an OVF output of the counter 1 and a match signal from the match circuit 2 are output. The PWM output with the corresponding cycle is performed.

FIG. 2 is a timing chart showing the operation example of FIG. 1, in which the n-bit value is set to 8 bits. The operation of the first embodiment will be described with reference to FIGS. 1 and 2.

First, the time for resetting the flip-flop 4 is stored in the register 3, and the time for generating the interrupt request signal is set in the register 4. These settings are made by an instruction to the internal CPU, and the setting time is set via the data bus 9 to these registers 3, 6
Stored in. In FIG. 2, the value of register 3 is set to "98
The value of the register 6 is set to "H" and "02H".

The counter 1 inputs the clock pulse C
It counts up by LK, and O when overflow
The VF output is output to the flip-flop 4. That is,
In FIG. 2, since the counter 1 is an 8-bit counter,
The counting is started from "00H" and is incremented by "1" every time the clock pulse CLK is input. When the count value reaches "FFH", the OVF output is sent to the set terminal S of the flip-flop 4, the count value is reset to "00H" which is the initial value, and "00H" is returned again.
The clock pulse CLK is counted up.

Since "98H" is set in the register 3, the count value of the counter 1 is "98H".
At that time, the coincidence signal is output to the reset terminal R of the flip-flop 4. The flip-flop 4 outputs "O" level when the OVF output pulse from the counter 1 is input to the set terminal S, and outputs "L" level when the coincidence signal pulse is input to the reset terminal R. A pulse output signal is output from the flip-flop 4 by repeating this operation.

On the other hand, the interrupt request signal is generated by an operation different from the pulse output signal generating operation. That is, in FIG. 2, since “02H” is set in the register 6, the counter 1 counts up and “02H” is set.
Then, the coincidence between the contents of the register 6 and the contents of the counter 1 is detected by the coincidence circuit 5, and the interrupt request signal is output.

As described above, according to the first embodiment, the coincidence circuit 5 and the register 6 can generate an interrupt request signal at an arbitrary point in the pulse signal cycle regardless of the pulse output signal generating operation. Become. Therefore, in the first embodiment, output control of the interrupt request signal can be performed with high accuracy without performing special control.

FIG. 3 shows a second pulse output circuit according to the present invention.
3 is a circuit diagram showing an embodiment of FIG. The difference between the first embodiment and the second embodiment is that the second embodiment reduces the number of coincidence circuits to one, and the coincidence circuit detects the coincidence between two registers to detect the reset signal of the flip-flop 4. The point is to output an interrupt request signal.

That is, the registers 3 and 6 are connected to the selector 7, and the contents of the register selected by the selector 7 are sent to the coincidence circuit 2. The selector 7 selects the register designated by the select signal. Matching circuit 2
Is also connected to the selector 8 and outputs a match signal to the selector 8 when the content of the selected register matches the value of the counter 1.

The selector 8 has two output terminals, one output terminal is connected to the reset terminal R of the flip-flop 4, and the other output terminal is an output terminal for an interrupt request signal. The selector 8 also receives the same select signal as the selector 7. When the match signal is input when the select signal indicates the register 3, the selector 8 outputs this match signal from one output terminal to the reset terminal R of the flip-flop 4. When the selector 8 receives the coincidence signal when the select signal indicates the register 6, the selector 8 outputs this signal as an interrupt request signal from the other output terminal.

In the second embodiment, the same components as those in the first embodiment are designated by the same reference numerals, and the duplicated description is omitted here. In the second embodiment, control by the select signal is added, but the bit number of the counter 1 and the registers 3 and 6
If the value set in is the same as in the first embodiment, the pulse output signal output from the flip-flop 4 and the interrupt request signal output from the selector 8 are output at the same timing.

As described above, according to the second embodiment, since the coincidence circuit having a larger circuit scale can be used in common with the first embodiment, the circuit is provided in addition to the effect of the first embodiment. There is an advantage that the scale can be reduced.

Although the first and second embodiments have been described, the present invention is not particularly limited to these embodiments. That is, the present invention solves the problem that the interrupt request signal cannot be output except at the time of setting or resetting the pulse output, by the register and the matching circuit, and by using the present invention, at any point of the pulse signal cycle. It becomes possible to generate an interrupt request signal.

In the above embodiment, the case where the pulse output signal generating operation and the interrupt request signal generating operation are independent has been described as an example, but the invention is not particularly limited to the interrupt request signal. Specifically, it may be used as a start signal for another built-in peripheral device. When it is used as the activation signal of the peripheral device in this way, real-time processing is possible because the process until the peripheral device is activated can be omitted rather than being activated by the program.

[0030]

As described above, according to the pulse output circuit of the present invention, the interrupt request signal of the CPU, the activation signal of the peripheral device, and the like are output at any time point of the pulse signal cycle regardless of the generation operation of the pulse output signal. It becomes possible to output, and the pulse output can be controlled with high accuracy. Therefore, a highly accurate pulse signal can be output.

[Brief description of drawings]

FIG. 1 is a circuit diagram showing a first embodiment of a pulse output circuit according to the present invention.

FIG. 2 is a waveform chart showing a timing chart in the first embodiment shown in FIG.

FIG. 3 is a circuit diagram showing a second embodiment of the pulse output circuit according to the present invention.

[Explanation of symbols]

 1 counter 2, 5 coincidence circuit 3, 6 register 4 flip-flop 7, 8 selector

Claims (10)

[Claims] 1. A counter which counts an input clock and outputs a first signal when the count value reaches a predetermined value, and a first value which is a numerical value within a range counted by the counter is stored. A first register, a first matching circuit that compares the count value of the counter with a first value stored in the first register, and outputs a second signal when these values match, A second register that stores a second value, which is a numerical value within the range counted by the counter, is compared with a count value of the counter and a second value that is stored in the second register. And a second matching circuit which outputs a third signal when the two match, and a first signal which is input from the counter and a second signal which is input from the first matching circuit. Pulse output to output a pulse with a pulse width And a section, the pulse output circuit, characterized by arbitrarily controlling the output timing of the second of said by changing the value third signal stored in the second register. 2. The pulse output circuit according to claim 1, wherein the third signal is an interrupt request signal for the control unit. 3. The pulse output circuit according to claim 1, wherein the third signal is a start signal for a peripheral device. 4. The pulse output circuit according to claim 1, wherein the counter is an n-bit (n is a natural number) free-run counter, and outputs the first signal when reaching a maximum value. Characteristic pulse output circuit. 5. The pulse output circuit according to claim 4, wherein the first register and the second register are n-bit registers. 6. A counter that counts the input clock and outputs a first signal when the count value reaches a predetermined value, and a first value that is a numerical value within a range counted by the counter is stored. A first register; a second register that stores a second value that is a numerical value within the range counted by the counter; and the first register when the input selection signal is the first selection signal, A first selector that selects the second register when the second selection signal is received is compared with the value stored in the register selected by the first selector and the count value of the counter. A matching circuit that outputs a matching signal when they match, and a second signal is output when the matching signal from the matching circuit is input when the selection signal is the first selection signal, and the selection signal is the second signal. When the selection signal of A second selector that outputs a third signal when a coincidence signal from the circuit is input, and a second signal that is input from the counter while inputting the first signal from the counter. A pulse output section for outputting a pulse having a pulse width according to the pulse width, and controlling the output timing of the third signal arbitrarily by changing the second value stored in the second register. And pulse output circuit. 7. The pulse output circuit according to claim 6, wherein the third signal is an interrupt request signal for the control unit. 8. The pulse output circuit according to claim 6, wherein the third signal is a start signal for a peripheral device. 9. The pulse output circuit according to claim 6, wherein the counter is an n-bit (n is a natural number) free-run counter, and outputs the first signal when reaching a maximum value. Characteristic pulse output circuit. 10. The pulse output circuit according to claim 9, wherein the first register and the second register are n-bit registers.