JPH04262614A - Electronic device used to output periodic signal - Google Patents

Abstract

PURPOSE: To output a period signal with a relatively simple constitution and function and high resolution and precision by using a computer by operating allowing based on the comparison of the count value of a circulating counter with the content of a comparing register. CONSTITUTION: A period signal is outputted by using a computer 10, comparator 12 for setting a prescribed value, and counter 14 necessitating a period tmax for circulating in a counting range Zmax with prescribed frequencies. Then, a period T to be outputted is defined as (n)=INT(T/TZR), and divided into the multiple of a settable unit time TZR and residual periods TRest according to an expression I. Also, corresponding whole count values W are defined as (n)=INT(W/DZ), and divided into the multiple of a settable unit count value DZ and residual values ZRest according to an expression II. The content of the comparator 12 is controlled according to an expression III by defining ZT(t0) as the counter value of a period signal output starting time t0, the Zrest as W-n*DZ, and i*DZ as an isolated value on safety for the count value.

Description

[Detailed description of the invention]

0001

FIELD OF INDUSTRIAL APPLICATION The present invention uses a computer, a comparator that can be set to a predetermined value, and a counter that requires a predetermined period of time to cycle through a counting range at a predetermined counting frequency. The present invention relates to an electronic device that outputs a signal.

0002

[Prior art] German publication DE-OS311068
3 describes "a device that generates a period signal." The device is equipped with two counters,
The first counter counts down from a predetermined residual value, and continuously cycles through the counting range until the second counter detects the first counter passing the zero point a predetermined number of times. In the device further described in this DE-OS 3110683, instead of counting the residual value in a first counter and subsequently cycling through a counting range, the first counter is continuously set to a predetermined initial value. ing.

[0003] As another prior art, US-PS487
3624 "Output comparison device and method for a data processor" and EP-PS298960 "Method and digital control device for determining and controlling the operating quantity of a pulse-width modulated internal combustion engine", but these known devices are not applicable in any case. However, it also has the disadvantage that it is not possible to obtain satisfactory results.

0004

SUMMARY OF THE INVENTION Accordingly, it is an object of the present invention to provide a device which uses a computer, has a relatively simple configuration and function, and is capable of outputting a period signal with high resolution and precision.

[0005]

[Means for Solving the Problems] According to the present invention, a computer, a comparator that can be set to a predetermined value, and a period tmax for cycling through a counting range Zmax at a predetermined counting frequency. In an electronic device that outputs a period signal using a necessary counter, assuming that the period T to be output is n=INT(T/TZR),

[0006]

[Math 4]

Divide into multiples of settable unit time TZR and remaining period TRest according to the formula, or set the corresponding overall count value W as n=INT(W/DZ),

[0008]

[Math 5]

A unit count value D that can be set according to the formula
Divided into a multiple of Z and the remaining value ZRest, ZT(t0) is the counter value of t0 at the start of period signal output, and ZRest is W-
Let n*DZ, i*DZ be the safety distance values for the count value, and calculate the contents of the comparator.

0010

[Math 6]

This is solved by a configuration that controls according to the equation: ##EQU1##

0012

It has been found that the electronic device of the present invention for outputting period signals is relatively simple in structure and function. This is because we can use a counter that is always rotating. Thereby, the resolution and accuracy of the signal can be increased. Furthermore, it has been revealed that it is extremely difficult to generate noise.

[0013]

Embodiments of the invention are shown in the drawings and explained in detail below.

FIG. 1 schematically shows the individual hardware configuration of a device for outputting period signals. Reference numeral 10 indicates a computer, which is connected via a data line 11 to a comparator 12 (comparison register CR). This comparator is further connected via a data line 13 to a counter 14, which is also supplied via an input 15 with a counting frequency clock (Cl). The conductors 16 transmit the current counting state of each of the counters 14 to the computer 10.
used to supply The block 18 is a signal output stage, and from its output 19 a signal can be taken out for a desired period. The signal output stage 18 is supplied with an input quantity from the computer 10 which defines the beginning of the period signal, and from a comparator 12 with an input quantity which defines the end of the period signal.

Further, block 20 is a system part of the control device for the internal combustion engine, and outputs data to an output line 22 to be finally converted into a desired period signal based on the input amount input to the input 21. .

The device described above with a comparator operates on the basis of a comparison of the count value of a rotating counter or timer and the contents of a comparison register. If the count value of the counter and the contents of the comparison register are equal, the computer hardware automatically switches the output port associated with comparator 12.

Depending on the hardware configuration of the computer or microcontroller, an interrupt can also be generated when a comparison result occurs, so that the program can react to this comparison result.

In order to output an arbitrary pulse length in a period signal, the counting range of the counter must be cycled several times because the number of digits of the counter and comparator is limited. If it is necessary to increase the resolution and absolute accuracy of the pulse length to be output, the real-time burden on the computer must be limited to a minimum.

Next, the apparatus of the present invention will be explained using FIG.

FIG. 2 shows the count value of the counter 14 and the respective comparison value of the comparator 12 with respect to time t. In the figure, sawtooth lines 25 indicate the respective count values of the counters, and stepped lines 26 indicate the respective contents of the comparators 12.

What is important is that the counter 14 be able to cycle through the counting region continuously and be independent of when the desired period signal is output. The counter measures the time tma with a predetermined counting frequency.
The maximum count value Zmax is reached at x.

In the illustrated embodiment, the counter tm
It is assumed that a period T greater than ax is output.

FIG. 3 shows the situation again. The difference from the illustration in FIG. 2 is that the starting points of tmax and T coincide. The length of the period signal T to be output is tma
The range W of count values necessary for each count exceeds the maximum count range Zmax provided by the counter 14 and the comparator 12, in the same way as the range W of count values required for each count exceeds the maximum count range Zmax provided by the counter 14 and the comparator 12.

The basic idea of the present invention is that each period T>t
max is divided into a multiple of the unit time TZR and the remaining time TRest according to the following equation.

[0025]

[Math 7]

[0026] However, n=INT(T/TZR).

The total value W is also divided into a multiple of the unit count value DZ and a residual value ZRest, and the same is done for the count value. In other words, it is as follows.

[0028]

[Math. 8]

However, n=INT(W/DZ).

In that case, the period of unit time TZR corresponds to unit count value DZ at a predetermined counting frequency. According to the invention, the comparator 12 is constructed, as shown in FIG. 2, in such a way that the initial value and the instantaneous value always exceed the respective counter value or timer value.

As an initial value, the comparator is loaded with the following sum of values:

Counter value at time t0
=ZT(t0) Remaining value corresponding to remaining time TRest =ZRest Safety gap value of circulating counter =i*DZ
By adding i times the unit count value (DZ) to the sum of the initial value ZT(t0) and the residual value ZRest, a sufficient safety gap is created for each state of the operation counter 14. Thereby, even if the reloading is delayed, the contents of the counter 14 and the comparator do not coincide prematurely. Note that the following conditions apply to i.

1<i<INT(tmax/TZR-1) or 1<i
<INT(Zmax/DZ-1) Next, unit time TZR
For each period, the unit count value DZ is added to the value of the comparator 12, and this addition is performed for every unit time. This reload must be controlled by a software counter. Regarding the instantaneous value of the comparator,

[0034]

[Math. 9]

[0035] applies.

When the comparator 12 has been reloaded (increased j) and the initially loaded value has been counted, the counting process is completed or the comparison result is output. In that case the comparator and counter have the same value.

The calculation process will be explained in the form of a simple flowchart in relation to the period signal.

Program start counter 14 operation, Z(t) Setting safety difference value i*DZ However, 1<i<INT(tmax/TZR-1) or 1<i<INT(Zmax/ZD-1)DZ Unit count value Unit time value TZR Total calculation period T n times n = INT (T/TZR) Remaining period TRest = T-n * TZR residual value
Remaining period TRest and quantization or ZRest=
W-n*D Determine time output start ZT (t0) at startup (t0) from Z. Contents of comparator or comparison register (CR)

0039
]

[Math. 10]

[0040]

When ZCR(t(n-i)) is reached, the standby period output signal ends until the counter value becomes Z(t)=ZCR(t(n-i)).

[0042]

[Effects of the Invention] As is clear from the above description, according to the present invention, the structure and function are relatively simple, the resolution and accuracy of the signal can be improved, and the signal can be output for a period with less noise. can.

[Brief explanation of the drawing]

FIG. 1 is a block diagram schematically illustrating the individual hardware components.

FIG. 2 is a diagram showing a flow when forming a period signal.

FIG. 3 is a diagram showing a flow when forming a period signal.

[Explanation of symbols]

10 Computer 12 Comparator 14 Counter 18 Signal output stage

Claims (3)

[Claims] 1. A computer (10), a comparator (12) that can be set to a predetermined value, and a counter (14) that requires a period tmax to cycle through a counting range Zmax at a predetermined counting frequency. In an electronic device that outputs a period signal by using
/TZR), divide it into a multiple of unit time TZR and the remaining period TRest that can be set according to the formula [Equation 1], or set the corresponding overall count value W as n=INT(W/DZ), [Equation 2 ] Divide into a multiple of the settable unit count value DZ and the residual value ZRest, ZT(t0) is the counter value at t0 at the start of period signal output, ZRest is W-n*DZ,i
*DZ is the safety distance value for the count value,
An electronic device for outputting a period signal, characterized in that the contents of a comparator are controlled according to the following equation. 2. Regarding the i, 1<i<INT(tmax/TZR-1) or 1<
2. Device according to claim 1, characterized in that the value of i<INT(Zmax/DZ-1) is selected. 3. Device according to claim 1, characterized in that it is used in connection with the control of an internal combustion engine.