JPH05181709A - Watchdog timer for intermittent operation - Google Patents

Abstract

PURPOSE:To provide a watchdog timer for monitoring the operation of a CPU executing intermittent operation. CONSTITUTION:The watchdog timer for counting up pulses generated from a pulse generating means 1 at a fixed period by a counter 2, resetting the counted value by a reset signal outputted from a CPU, comparing the counted value of the counter 2 with a constant value generated from a constant generating means 4 by a comparing means 3, and when the counted value exceeds the constant value, outputting an abnormality detecting signal indicating the abnormality of the CPU is provided with any one among a pulse control means 5 for changing the pulse period of pulses generated from the means 1, a constant control means 6 for changing a constant value generated from the means 4, a reset control means for controlling the supply of a reset signal to the counter 2, an output control means for controlling the output of an abnormality detecting signal from the means 3, and a loading value control means for loading an initial value at the time of resetting the counter 2.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION The present invention relates to a central processing unit (CP
The present invention relates to a watchdog timer for monitoring the operation U), and more particularly to a watchdog timer for monitoring the operation of the CPU which performs intermittent operation.

The watchdog timer is supplied with a reset signal (pulse) from the CPU at a constant cycle, and when the reset signal is not input for a predetermined time,
It is a device (circuit) for determining that the CPU is abnormal, and has been conventionally used in various devices for the purpose of monitoring the normality of the operation of the CPU.

On the other hand, among devices using a CPU, in a device using a battery as a power source such as a mobile phone, intermittent power supply is often performed to reduce power consumption, and the CPU is intermittently supplied. Works properly.

Therefore, there is a demand for a watchdog timer capable of monitoring the operation of the CPU which operates intermittently.

[0005]

2. Description of the Related Art FIG. 15 shows the structure of a conventional watchdog timer, which comprises a pulse generator 11, a counter 12, a comparator 13, and a constant generator 14. The pulse generator 11 generates a pulse of a constant cycle, the counter 12 counts up with this pulse, and the count value is reset to 0 by a reset signal from a CPU (not shown). The comparator 13 compares the count value of the counter 12 with the constant generated by the constant generator 14, and when the count value is larger than the constant, outputs a signal for determining abnormality detection.

[0006]

The conventional watchdog timer is constructed on the assumption that the monitored CPU is constantly operating and generates a reset signal within a fixed time, and the CPU intermittently operates. It is always operating, even at times.

However, in the case of a device such as a mobile phone which performs an intermittent operation to reduce power consumption, the reset signal is not supplied from the CPU during the idle period, so that the C
Although the PU is operating normally, the watchdog timer determines that the CPU is abnormal. Therefore, the conventional watchdog timer has a problem that it cannot be used in a device that performs an intermittent operation.

The present invention is intended to solve such a problem of the prior art, and a watchdog timer capable of operating normally and performing CPU abnormality monitoring even in an apparatus which performs intermittent operation. Is intended to provide.

[0009]

According to the present invention, a counter counts up a pulse having a constant period from a pulse generating means and resets it by a reset signal from a CPU, and a comparing means counts a counter value and a constant generating means. When the count value exceeds the constant value by comparing with the constant value from, the watchdog timer that outputs the abnormality detection signal indicating the abnormality of the CPU changes the pulse period from the pulse generation means or disconnects the pulse. Is provided to increase the count-up time until the abnormality detection signal of the counter is generated or stop the count during the intermittent operation of the CPU.

Further, according to the present invention, in the counter, the pulse of the constant period from the pulse generating means is counted up to C
The reset signal from the PU is used for resetting, and the comparing means compares the count value of the counter with the constant value from the constant generating means. When the count value exceeds the constant value, an abnormality detection signal indicating an abnormality of the CPU is output. In the watchdog timer, the constant control means for changing the constant value in the constant generation means is provided, and the count-up time for generating the abnormality detection signal of the counter is lengthened during the intermittent operation of the CPU. Is.

Further, according to the present invention, in the counter, the pulse of the constant period from the pulse generating means is counted up to C
The reset signal from the PU is used for resetting, and the comparing means compares the count value of the counter with the constant value from the constant generating means. When the count value exceeds the constant value, an abnormality detection signal indicating an abnormality of the CPU is output. In the watchdog timer, the reset control means for controlling the supply of the reset signal to the counter is provided.
It is characterized in that the supply of the reset signal to the counter is continued during the intermittent operation of the PU.

Further, according to the present invention, in the counter, the pulse of the constant period from the pulse generating means is counted up and C is counted.
The reset signal from the PU resets the counter, and the comparing means compares the count value of the counter with the constant value from the constant generating means. When the count value exceeds the constant value, an abnormality detection signal indicating an abnormality of the CPU is output. In the watchdog timer, the output control means for controlling the output of the abnormality detection signal from the comparison means is provided, and the output of the abnormality detection signal is cut off during the intermittent control of the CPU. ..

Further, according to the present invention, in the counter, the pulse of the constant period from the pulse generating means is counted up to C
The reset signal from the PU is used for resetting, and the comparing means compares the count value of the counter with the constant value from the constant generating means. When the count value exceeds the constant value, an abnormality detection signal indicating an abnormality of the CPU is output. In the watchdog timer, the load value control means for loading the initial value at the time of resetting the counter is provided, and the count-up time for generating the abnormality detection signal of the counter is lengthened during the intermittent operation of the CPU. It is a thing.

[0014]

FIG. 1 shows the principle configuration of the present invention, and shows the case where the count-up time of the counter is controlled by controlling the pulse generator. Reference numeral 1 is a pulse generation means, 2 is a counter, 3 is a comparison means, 4 is a constant generation means, and 5 is a pulse control means.

The pulse generating means 1 generates a pulse having a constant cycle, and the counter 2 counts this pulse.
The comparing means 3 compares the count value of the counter 2 with the constant value generated from the constant generating means 4, and when the count value exceeds the constant value, outputs an abnormality detection signal for determining abnormality. When the monitored CPU (not shown) is normal, the reset signal is given to the counter 2 before the count value of the counter 2 exceeds the constant value, so that the comparing unit 3 does not output the abnormality detection signal. When the CPU performs the intermittent operation, the pulse control means 5 controls the pulse generation means 1 before the next reset signal is supplied from the CPU.
Make sure that the count value of the counter 2 does not exceed a constant value. Therefore, in the case of the principle configuration of FIG. 1, even if the CPU performs the intermittent operation, the watchdog timer does not detect the abnormality.

FIG. 2 shows another principle structure of the present invention, showing a case where the count-up time of the counter is controlled by controlling a constant to be compared with the count value of the counter. .. The same parts as those in FIG. 1 are indicated by the same numbers, and 6 is a constant control means.

When the CPU performs the intermittent operation, the constant control means 6 changes the constant value generated from the constant generation means 4 and the count value of the counter 2 before the reset signal is next supplied from the CPU. Does not exceed a constant value. Therefore, in the case of the principle configuration of FIG.
Even if U performs the intermittent operation, the watchdog timer does not detect the abnormality.

FIG. 3 shows still another principle structure of the present invention. By continuing the supply of the reset signal to the counter, the occurrence of an abnormality detection signal from the counter during intermittent operation is suppressed. The case is shown.
The same parts as those in FIG. 1 are indicated by the same numbers, and 7 is a reset control means.

When the CPU performs the intermittent operation, the reset control means 7 generates another reset signal different from the reset signal of the CPU and supplies it to the counter 2, so that the counter is supplied before the reset signal is supplied. Make sure that the count value of 2 does not exceed the constant value. Therefore, in the case of the principle configuration of FIG. 3, even if the CPU performs the intermittent operation, the watchdog timer does not detect the abnormality.

FIG. 4 shows still another principle structure of the present invention, showing a case where the output of the comparator is controlled to suppress the generation of the abnormality detection signal during the intermittent operation. There is. The same parts as those in FIG. 1 are shown by the same numbers, and 8 is an output control means.

When the CPU performs the intermittent operation, the output control means 7 prevents the abnormality detection signal of the comparison means 3 from being output. Therefore, in the case of the principle configuration of FIG.
The watchdog timer does not detect any abnormalities even if the intermittent operation is performed.

FIG. 5 shows still another principle configuration of the present invention, showing a case where the count-up time of the counter is controlled by controlling the value to be loaded (initialized) in the counter. ing. The same parts as those in FIG. 1 are indicated by the same numbers, and 9 is a load value control means.

The counter 2 is loaded with a constant value when reset by a reset signal from the CPU. When the CPU performs the intermittent operation, the load value control means 9 controls the constant value to be loaded into the counter 2 as the initial value to be a different constant value, and thus the CPU
Before the reset signal is supplied from, the count value of the counter 2 is prevented from exceeding a constant value. Therefore, in the case of the principle configuration of FIG. 5, even if the CPU performs the intermittent operation, the watchdog timer does not detect the abnormality.

[0024]

FIG. 6 shows the structure of an embodiment of the present invention, which corresponds to the principle structure shown in FIG. 15 which are the same as those in FIG.
Is a switch.

In the embodiment shown in FIG. 6, the CPU
The intermittent control signal given in response to the intermittent operation is the CPU
The output of the pulse generator 11 is turned on to perform the count-up operation of the counter at the time of ON indicating the operation of the pulse generator 11. However, when the intermittent control signal is OFF indicating that the CPU is stopped, the pulse generator 11 is turned off. The output is turned off and the count-up operation of the counter is stopped. Therefore, according to the embodiment shown in FIG. 6, even if the CPU performs the intermittent operation, the watchdog timer does not detect the abnormality.

FIG. 7 shows the configuration of another embodiment of the present invention, which corresponds to the principle configuration shown in FIG. The same parts as those in FIG.
Is a frequency divider.

In the embodiment shown in FIG. 7, by controlling the switch 15 according to the intermittent control signal,
When the intermittent control signal is on, the output of the pulse generator 11 is directly connected to the counter, but when the intermittent control signal is off, the output of the pulse generator 11 is applied to the counter via the frequency divider 16. , Increase the count-up time for generating the abnormality detection signal of the counter during intermittent operation. Therefore, according to the embodiment shown in FIG. 7, even if the CPU performs the intermittent operation, the watchdog timer does not detect the abnormality.

FIG. 8 shows the configuration of still another embodiment of the present invention, which corresponds to the principle configuration shown in FIG. The same components as those in FIG. 6 are designated by the same reference numerals, and 17 is a variable frequency divider.

In the embodiment shown in FIG. 8, the output of the pulse generator 11 is supplied to the counter via the variable frequency divider 17, and the frequency division ratio of the variable frequency divider 17 is set according to the intermittent control signal. When the intermittent control signal is ON, the frequency division ratio of the variable frequency divider 17 is set to a pulse interval value when the intermittent operation is not performed, and the output is connected to the counter. On the other hand, when the intermittent control signal is off, the frequency division ratio of the variable frequency divider 17 is increased and the output thereof is connected to the counter, thereby increasing the count-up time for generating the abnormality detection signal of the counter during the intermittent operation. Lengthen.
Therefore, according to the embodiment shown in FIG. 8, even if the CPU performs the intermittent operation, the watchdog timer does not detect the abnormality.

FIG. 9 shows a structure of still another embodiment of the present invention, and corresponds to the principle structure shown in FIG. The same parts as those in FIG. 15 are designated by the same reference numerals, and 18 is a constant generator.

In the embodiment shown in FIG. 9, by switching the switch 15 in response to the intermittent control signal, when the intermittent control signal is on, there is a constant (constant 1) for not performing the intermittent operation. The output of the constant generator 14 is input to the comparator 13. On the other hand, when the intermittent control signal is off, the output of the constant generator 18 having another constant (constant 2) is input to the comparator 13. At this time, constant 1 << constant 2
By doing so, the count-up time for generating the abnormality detection signal of the counter during the intermittent operation is lengthened. Therefore, according to the embodiment shown in FIG. 9, even if the CPU performs the intermittent operation, the watchdog timer does not detect the abnormality.

FIG. 10 shows the structure of still another embodiment of the present invention, and corresponds to the principle structure shown in FIG. The same parts as those in FIG. 9 are indicated by the same numbers, and 19 is a constant register.

In the embodiment shown in FIG. 10, a constant (constant 1) when the intermittent operation is not performed by the CPU is set in the constant register 19 immediately before returning from the intermittent operation to the normal operation. On the other hand, immediately before entering the intermittent operation from the normal operation,
Another constant (constant 2) is set in the constant register 19. At this time, by setting the constant 1 << constant 2, the count-up time for generating the abnormality detection signal of the counter during the intermittent operation is lengthened. Therefore, according to the embodiment shown in FIG. 10, even if the CPU performs the intermittent operation, the watchdog timer does not detect the abnormality.

FIG. 11 shows the structure of still another embodiment of the present invention, and corresponds to the principle structure shown in FIG. The same components as those in FIG. 15 are designated by the same reference numerals, and 20 is a reset pulse generator.

In the embodiment shown in FIG. 11, the switch 15 is switched according to the intermittent operation signal so that the reset signal from the CPU is input to the counter 12 when the intermittent control signal is on. On the other hand, when the intermittent control signal is off, the reset signal from the separately provided reset pulse generator 20 is input to the counter 12.
Therefore, according to the embodiment shown in FIG. 11, even if the CPU performs the intermittent operation, the watchdog timer does not detect the abnormality.

FIG. 12 shows the structure of still another embodiment of the present invention, which corresponds to the principle structure shown in FIG. The same parts as those in FIGS. 7 and 11 are indicated by the same numbers.

In the embodiment shown in FIG. 12, the switch 15 is switched according to the intermittent operation signal so that the reset signal from the CPU is input to the counter 12 when the intermittent control signal is on. On the other hand, when the intermittent control signal is off, the pulse from the pulse generator 11 is divided by the frequency divider 16 and input to the counter 12 as a reset signal. Therefore, according to the embodiment shown in FIG.
Even if U performs the intermittent operation, the watchdog timer does not detect the abnormality.

FIG. 13 shows still another embodiment of the present invention, in which (a) is a block diagram showing the configuration.
(B) is a time chart showing the operation. This corresponds to the principle configuration shown in FIG. 4 and is the same as in FIG. 15 with the same number, and 21 is an output control unit.

In the embodiment shown in FIG. 13, the output control unit 21 controls the switch 15 in response to the intermittent control signal, so that when the intermittent control signal is on, the switch 15 is turned on and comparison is performed. Although the abnormality detection signal from the comparator 13 is output, when the intermittent control signal is off, the switch 15 is turned off so that the abnormality detection signal from the comparator 13 is not output. However, when the switch 15 is turned on, an abnormality detection signal may be output. Therefore, immediately before the switch 15 is switched from off to on, the CPU
A reset signal is applied from the counter 12 to reset the counter 12. Therefore, according to the embodiment shown in FIG. 13, even if the CPU performs the intermittent operation, the watchdog timer does not detect the abnormality.

FIG. 14 shows still another embodiment of the present invention, in which (a) is a block diagram showing the configuration.
(B) is a time chart showing the operation. 15 corresponds to the principle configuration shown in FIG. 5 and is the same as that in FIG. 15 and FIG.

In the embodiment shown in FIG. 14, when the intermittent control changes from OFF indicating the stop of the CPU to ON indicating the operation of the CPU, the load value control unit 22 causes the switch 1 to operate.
5 is controlled to set a constant (constant 1) when the intermittent operation is not performed from the constant generator 14 in the counter 12, and the intermittent control changes from ON indicating the operation of the CPU to OFF indicating the stop of the CPU. , Load value control unit 22 is switch 1
5 to control another constant from the constant generator 18 (constant 2)
Is set in the counter 12. At this time, by setting the constant 1 << constant 2, the count-up time for generating the abnormality detection signal of the counter during the intermittent operation is lengthened. Therefore, according to the embodiment shown in FIG. 14, even if the CPU performs the intermittent operation, the watchdog timer does not detect the abnormality.

[0042]

As described above, according to the present invention, C
A watchdog timer that monitors the operation of the PU
Can be used even when performing intermittent operation.

[Brief description of drawings]

FIG. 1 is a diagram showing a principle configuration of the present invention.

FIG. 2 is a diagram showing another principle configuration of the present invention.

FIG. 3 is a diagram showing still another principle configuration of the present invention.

FIG. 4 is a diagram showing still another principle configuration of the present invention.

FIG. 5 is a diagram showing still another principle configuration of the present invention.

FIG. 6 is a diagram showing a configuration of an exemplary embodiment of the present invention.

FIG. 7 is a diagram showing the configuration of another embodiment of the present invention.

FIG. 8 is a diagram showing a configuration of still another embodiment of the present invention.

FIG. 9 is a diagram showing the configuration of still another embodiment of the present invention.

FIG. 10 is a diagram showing a configuration of still another exemplary embodiment of the present invention.

FIG. 11 is a diagram showing the configuration of still another embodiment of the present invention.

FIG. 12 is a diagram showing the configuration of still another embodiment of the present invention.

13A and 13B show still another embodiment of the present invention, wherein FIG. 13A is a block diagram showing a configuration, and FIG. 13B is a time chart showing an operation.

14A and 14B show still another embodiment of the present invention, wherein FIG. 14A is a block diagram showing a configuration, and FIG. 14B is a time chart showing an operation.

FIG. 15 is a diagram showing a configuration of a conventional watchdog timer.

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 1 pulse generating means 2 counter 3 comparing means 4 constant generating means 5 pulse controlling means 6 constant controlling means 7 reset controlling means 8 output controlling means 9 load value controlling means

Claims (5)

[Claims] 1. A counter (2) counts up a pulse having a constant period from a pulse generating means (1) to obtain C.
When reset by a reset signal from the PU and comparing the count value of the counter (2) with the constant value from the constant generating means (4) in the comparing means (3), the count value exceeds the constant value. In a watchdog timer that outputs an abnormality detection signal indicating an abnormality of the CPU, pulse control means (5) for changing the pulse period from the pulse generating means (1) or for interrupting the pulse is provided, and the CPU is intermittently operated. A watchdog timer for intermittent operation, characterized in that, during operation, a count-up time for generating an abnormality detection signal of the counter (2) is lengthened or stopped. 2. A counter (2) counts up a pulse having a constant period from the pulse generating means (1) and C
When reset by a reset signal from the PU and comparing the count value of the counter (2) with the constant value from the constant generating means (4) in the comparing means (3), the count value exceeds the constant value. In a watchdog timer that outputs an abnormality detection signal indicating an abnormality of the CPU, a constant control means (6) for changing the constant value in the constant generation means (4) is provided, and the counter (2) is provided during the intermittent operation of the CPU. A watchdog timer for intermittent operation, characterized in that the count-up time up to the generation of the abnormality detection signal of is increased. 3. A counter (2) counts up a pulse having a constant period from the pulse generating means (1) to obtain C.
When reset by a reset signal from the PU and comparing the count value of the counter (2) with the constant value from the constant generating means (4) in the comparing means (3), the count value exceeds the constant value. In a watchdog timer that outputs an abnormality detection signal indicating an abnormality of the CPU, reset control means (7) for controlling the supply of the reset signal to the counter (2) is provided, and the counter (2) is provided during the intermittent operation of the CPU. A watchdog timer for intermittent operation, characterized in that the supply of a reset signal to the device is continued. 4. A counter (2) counts up a pulse having a constant period from the pulse generating means (1) to obtain C.
When reset by a reset signal from the PU and comparing the count value of the counter (2) with the constant value from the constant generating means (4) in the comparing means (3), the count value exceeds the constant value. In a watchdog timer that outputs an abnormality detection signal indicating an abnormality of the CPU, an output control means (8) for controlling the output of the abnormality detection signal from the comparison means (3) is provided, and the abnormality occurs during the intermittent control of the CPU. A watchdog timer for intermittent operation, characterized in that the output of a detection signal is cut off. 5. A counter (2) counts up a pulse having a constant period from the pulse generating means (1) to obtain C.
When reset by a reset signal from the PU and comparing the count value of the counter (2) with the constant value from the constant generating means (4) in the comparing means (3), the count value exceeds the constant value. In a watchdog timer that outputs an abnormality detection signal indicating an abnormality of the CPU, load value control means (9) for loading an initial value at the time of resetting the counter (2) is provided, and the counter (2 ) The watchdog timer for intermittent operation, characterized in that the count-up time leading to the generation of the abnormality detection signal in (1) is increased.