JPH07129278A - Resetting control circuit of multiprocessor system - Google Patents

Abstract

PURPOSE:To securely reset a master CPU and prevent the system from running away when a momentary break of a slave-CPU side power source is made by resetting a master processor with a power-ON reset signal generated in response to variation in the voltage of a slave-processor side power source. CONSTITUTION:The master CPU 2 and slave CPU 41 are equipped with a master-CPU side power source and the slave-CPU side power source of different systems. Then a slave-CPU power-ON reset generator 42 detects variation in the voltage of the slave-CPU side power source 40 and generates the reset signal (e). A power-ON reset signal control circuit 5 once detecting the signal (e) outputs a signal (h) for resetting the master CPU 2. In this constitution, the master CPU 2 can securely be reset without providing the master CPU 2 with an analog input port for monitoring the source voltage of a control block.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a reset control circuit for a multiprocessor system, and more particularly to a reset control circuit for a system in which a master processor and a slave processor have power supplies of different systems.

[0002]

2. Description of the Related Art Conventionally, in a processor system,
In some cases, one processor is used for control, but since there are many control targets, one control is used for each control block in the system, that is, control is performed using multiple processors in the system. There may be cases.

Usually, the above-mentioned plurality of processors are divided into a master CPU that controls the overall state of the entire system and a slave CPU that controls each control block. In this case, in order to reduce power consumption, etc., during the normal operation of the entire system, the master CP may be operated according to the operation of the entire system.
A system in which U controls ON / OFF of power supplied to each control block is conceivable.

For example, as shown in FIG. 3, a master CPU 21 for controlling the entire system and a control block 24.
A system composed of two slave CPUs 26 that perform internal control is conceivable.

In this system, the master CPU 21 is supplied with power from the master CPU power supply 20, and the slave CPU 26 is supplied with power from the slave CPU side power supply 25. The control circuit 28 controlled by the control signal 29 from the slave CPU 26 also has the slave C
Power is supplied from the PU-side power supply 25.

The power source 25 on the slave CPU side is the master CPU
ON / OFF is controlled by 21, and the master CPU 25
The communication between the slave CPU 26 and the slave CPU 26 is performed by serial communication via the serial interface 23.

From the master CPU power source 20 to the master CPU
21 and the change in the voltage state in the power supply from the slave CPU side power supply 25 to the slave CPU 26 is caused by the power-on reset generator 22 for the master CPU and the slave C.
It is monitored by the PU power-on reset generator 27.

Power-on reset generator 22 for master CPU and power-on reset generator 2 for slave CPU
When detecting a momentary interruption of the power supplied to the master CPU 21 and the slave CPU 26, 7 outputs a reset signal to the master CPU 21 and the slave CPU 26 to reset them.

In the above system, the slave CPU
When the load of the control circuit 28 controlled by 26 is large, voltage fluctuation may occur in the power source from the slave CPU side power source 25 due to momentary interruption or the like.

At this time, since the power supply voltage of the slave CPU side power supply 25 is lowered, the slave CPU 26 is powered by the slave CPU power-on reset generator 27 even though the master CPU 21 is operating normally.
Only may be reset.

By resetting only the slave CPU 26, the master CPU 21 and the slave CPU
Communication with 26 may fail, causing the system to crash.

In order to solve the above problems, as shown in FIG. 4, in the master CPU 31, the slave CPU
There is also a system configured to constantly monitor the power supply voltage of the slave CPU side power supply 35 supplied to the analog input terminal 36.

In this case, the master CPU 31 is the slave C
When a decrease in the power supply voltage supplied from the PU-side power supply 35 to the slave CPU 36 is detected, the slave CPU-side power supply 35
The slave CPU 36 is restarted by once turning off the power of the above, and the runaway of the system is prevented.

Further, a drive system power supply for supplying power to the power element, a means for on / off controlling the output of the drive system power supply, a means for forcibly discharging the power supply output at the same time as turning off the drive system power supply, When a decrease in power output due to power off is detected at the analog input port of the master CPU by means for preventing current from flowing backward from the load system capacitor toward the power when the output of the drive system power is turned off, The drive system power is turned on again, and the slave CP
A technique of operating the reset circuit of U to reset the slave CPU has also been proposed. This technique is described in detail in Japanese Patent Laid-Open No. 4-276812.

[0015]

In the reset control circuit of the conventional multiprocessor system described above, it is necessary to constantly monitor the voltage state of the power supply of the slave CPU side by the analog input port. When the system is configured by using a CPU or the like that is not provided, it is necessary to grasp the voltage state of the slave CPU-side power source by a dedicated peripheral circuit or the like.

Also, when the reset signal input to the slave CPU is monitored by the input port of the master CPU, the input port for inputting the reset signal is the master CP.
Required for U.

Therefore, an object of the present invention is to solve the above-mentioned problems, and to input a reset signal to the slave CPU without grasping the voltage state of the power source on the slave CPU side by a dedicated peripheral circuit or the like. Port is master C
It is an object of the present invention to provide a reset control circuit for a multiprocessor system that can reliably reset the master CPU and prevent system runaway when a power interruption occurs in the slave CPU side power supply without providing the PU.

[0018]

According to the reset control circuit of the present invention, there is provided a reset control circuit for a multiprocessor system comprising a master processor and a slave processor to which powers independent of each other are supplied. A means for controlling ON / OFF of the power supply on the slave processor side, a means for detecting a voltage change of the power supply on the slave processor side to generate a power-on reset signal, and a generation of the power-on reset signal And means for resetting the master processor.

[0019]

DESCRIPTION OF THE PREFERRED EMBODIMENTS Next, the present invention will be described with reference to the drawings.

FIG. 1 is a block diagram showing the configuration of an embodiment of the present invention. In the figure, a master CPU side power supply 1 supplies a power supply a to a master CPU 2 and a master CPU power-on reset generator 3, respectively.

The master CPU 2 controls the overall state of the entire system, and also controls on / off of the slave CPU side power supply 40 by the power supply control signal c. The power supply control signal c is also output to the power-on reset signal control circuit 5.

The master CPU power-on reset generator 3 detects the voltage state of the power supply from the master CPU-side power supply 1 and outputs a reset signal b to the power-on reset signal control circuit 5 when a momentary interruption of the power supply is detected. To do.

The slave CPU side power supply 40 in the control block 4 is on / off controlled by a power supply control signal c from the master CPU 2, and the slave CPU 41 and the slave CP are connected.
The power supply d is supplied to the U power-on reset generator 42 and the control circuit 43, respectively.

The slave CPU 41 controls the control circuit 43 by the control signal 44, and the serial interface 10
Communication with the master CPU 2 is performed via serial communication via.

The slave CPU power-on reset generator 42 detects the voltage state of the power source d from the slave CPU side power source 40, and when the instantaneous interruption of the power source a is detected, the reset signal e is sent to the slave CPU 41 and the power-on reset signal. Output to the control circuit 5.

Here, the master CPU 2 and the slave CPU
41 is a master CPU power-on reset generator 3 and a slave CPU power-on reset generator 42, respectively.
It is a low active CPU that is reset when the reset signals b and e from the above are low level.

The power-on reset signal control circuit 5 comprises a rising edge detection circuit 6, an inverting circuit 51, a NAND circuit 52, a delay circuit 53 and an AND circuit 54.
In the rising edge detection circuit 6, the reset signal e from the power-on reset generator 42 for the slave CPU is inverted by the inversion circuit 5.
It is a circuit for detecting the rising edge of the signal inverted by 1, and is composed of an inverting circuit 61, a delay circuit 62 and an AND circuit 63.

The delay circuit 62 is often composed of an integrating circuit or the like using resistors and capacitors. Also,
The delay circuit 53 is a circuit for adjusting the reset timing of the master CPU 2.

In the power-on reset signal control circuit 5, the inverting circuit 51 inverts the reset signal e from the slave CPU power-on reset generator 42, and the inverted signal is supplied to the inverting circuit 61 and the AND of the rising edge detection circuit 6. Output to the circuit 63.

The inversion circuit 61 of the rising edge detection circuit 6 inverts the inversion signal from the inversion circuit 51 and outputs the inversion signal to the delay circuit 62. The delay circuit 62 is the inverting circuit 61.
Delays the inverted signal from the
Output to 3. The AND circuit 63 ANDs the inverted signal from the inverting circuit 51 and the delayed signal from the delay circuit 62, and outputs the operation result to the NAND circuit 52 as an edge detection signal f.

The NAND circuit 52 takes the NAND of the power supply control signal c from the master CPU 2 and the edge detection signal f from the rising edge detection circuit 6 and outputs the operation result to the delay circuit 5.
Output to 3. The delay circuit 53 delays the output of the NAND circuit 52 and outputs the delayed signal g to the AND circuit 54.

The AND circuit 54 receives the reset signal b from the master CPU power-on reset generator 3 and the delay circuit 5.
The AND of the delayed signal g from 3 is taken, and the operation result is output to the master CPU 2 as a reset signal h.

FIG. 2 is a timing chart showing the operation of one embodiment of the present invention. The operation of the embodiment of the present invention will be described with reference to FIGS.

When the power supply a output from the master CPU power supply 1 rises and its voltage stabilizes, the reset signal b of the master CPU power-on reset generator 3 changes from low level to high level at time t1. , Master C
PU2 starts operation.

The master CPU 2 is a slave CPU side power source 4
In order to turn on 0, the power supply control signal c to the power supply 40 on the slave CPU side is changed from low level to high level at time t2. As a result, the slave CPU side power supply 40 is turned on at time t2, and the power supply d from the slave CPU side power supply 40 to the slave CPU 41 rises at time t2.

In the control block 4, similarly to the above operation, when the voltage of the power source d output from the slave CPU power source 40 is stable, the reset signal e of the slave CPU power-on reset generator 42 is t3. At the time of, the slave CPU changes from low level to high level.
41 starts operation.

The power control signal c from the master CPU 2 is t
When it goes low at time 4, the power d supplied from the slave CPU side power supply 40 to the control circuit 43 is turned off, and the reset signal e of the slave CPU power-on reset generator 42 goes from high to low. Then, the slave CPU 42 is reset.

At this time, the reset signal e output from the slave CPU power-on reset generator 42 is input to the power-on reset signal control circuit 5, and the inverting circuit 5 is supplied.
1 is input to the rising edge detection circuit 6.

In the rising edge detection circuit 6, the slave CP
The rising edge of the inverted value of the reset signal e from the U power-on reset generator 42 is detected. When the rising edge detection circuit 6 detects the rising edge, a high-level pulse signal is output as the edge detection signal f for a fixed time determined by the delay circuit 62, that is, from the time t5 to the time t6.

This pulse signal is NANDed by the NAND circuit 52 with the power supply control signal c from the master CPU 2.
When the power supply control signal c from the master CPU 2 is at the low level, the delay signal g from the delay circuit 53 that delays the output signal of the NAND circuit 52 remains at the high level as at t5.

The delay signal g from the delay circuit 53 is ANDed with the reset signal b from the power-on reset generator 3 for the master CPU by the AND circuit 54. Since the reset signal b is at the high level in the normal operation state, in this case, the output of the AND circuit 54, that is, the reset signal h to the master CPU 2 remains at the high level. Therefore, the master CPU 2 is never reset.

Now, when the load of the control block 4 is large,
If the power supply d supplied from the slave CPU side power supply 40 to the control circuit 43 is interrupted at t7, the master CPU
The reset signal b of the power-on reset generator 3 for the master CPU that is input to
Only the reset signal e of the power-on reset generator 42 for the slave CPU, which is input to 41, may go low.

At this time, the reset signal e from the power-on reset generator 42 for the slave CPU is the slave CP.
It is input to U41, resets the slave CPU 41, and is input to the power-on reset signal control circuit 5.

The reset signal e is inverted by the inversion circuit 51 of the power-on reset signal control circuit 5 and input to the rising edge detection circuit 6. The rising edge detection circuit 6 detects the rising edge of the reset signal e inverted by the inverting circuit 51.

When the rising edge detection circuit 6 detects a rising edge in the signal, it outputs a high-level pulse signal as the edge detection signal f for a fixed time determined by the delay circuit 62, that is, from time t8 to time t9. .

This pulse signal is NANDed by the NAND circuit 52 with the power supply control signal c from the master CPU 2.
At this time, since the master CPU 2 has not been reset, the power control signal c output from the master CPU 2
High level is output to.

Therefore, the NAND circuit 52 outputs a low level pulse signal. This pulse signal is delayed by the delay circuit 53, and the AND circuit 5 along with the reset signal b from the power-on reset generator 3 for the master CPU.
And is taken at 4.

In this state, since the reset signal b is at high level, the reset signal h from the AND circuit 54 is at low level for a certain period of time from the time t9. Since this low-level pulse signal is input to the reset input terminal of the master CPU 2, the master CPU 2 is reset.

Accordingly, since the master CPU 2 is reset, the master CPU 2 supplies power to the slave CPU side power source 4
The power control signal c to 0 is also in the initial state, and the slave CPU side power supply 40 is turned off.

If a non-volatile memory (not shown) is used for the master CPU 2 and the master CPU 2 itself has a function of holding data in a state before reset, the state before reset is Since the power supply output is in the ON state, when the master CPU 2 rises again, the power supply control signal c goes to the high level after it goes to the low level for the time required for the initial setting of the master CPU 2, that is, the time t10.

When the power supply control signal c goes high, the slave CPU side power supply 40 is turned on and the system is restarted.

That is, according to this embodiment, the master CP
If the slave CPU 41 is reset due to a momentary interruption during the period when the power control by U2 is on, the master CPU 2 is reset and the system is restarted. Therefore, the communication runaway between the master CPU 2 and the slave CPU 41 Can be prevented.

In this embodiment, the system in which each of the master CPU 2 and the slave CPU 41 is one has been described, but the present invention is not limited to this, and the slave CPU 41 is composed of two or more units. The present invention can also be applied to a processor system.

In this case, the slave C in each control block
The above configuration can be realized by inputting the output signal of the power-on reset circuit input to the PU to the AND circuit to obtain a logical product and inputting the output signal to the power-on reset signal control circuit 5. it can.

As described above, in the system in which the master CPU 2 and the slave CPU 41 have the master CPU side power source 1 and the slave CPU side power source 40 of different systems, respectively, the slave CPU power-on reset generator 42 has the slave CPU side power source. Resetting the master CPU 2 with a reset signal h from the power-on reset signal control circuit 5 when the power-on reset signal control circuit 5 detects that a reset signal e has been generated by detecting a voltage change of the power supply d of 40. As a result, the master CPU 2 does not need an analog input port for monitoring the power supply voltage of the control block, etc., so that a reliable reset operation can be performed even if a CPU having no analog input port is used as the master CPU 2. .

Further, in the software processing of the master CPU 2, when a momentary interruption of the power supply d of the slave CPU side power supply 40 is detected, the processing for restarting the master CPU 2 is the same as when the system is normally started up. Can be configured with.

Therefore, the slave CPU does not need to grasp the voltage state of the slave CPU side power supply 40 by a dedicated peripheral circuit or the like, and the master CPU 2 does not have an input port for inputting the reset signal e to the slave CPU 41. When a momentary interruption occurs in the side power supply 40, the master CPU 2 can be reliably reset to prevent system runaway.

[0058]

As described above, according to the present invention, in a multiprocessor system including a master processor and a slave processor, which are supplied with power sources independent of each other, a power change is detected by detecting a voltage change of the power source on the slave processor side. By resetting the master processor when it detects that an on-reset signal has been generated,
A momentary interruption occurs in the power supply of the slave CPU without knowing the voltage state of the power supply of the slave CPU with a dedicated peripheral circuit, and without providing the master CPU with an input port for inputting a reset signal to the slave CPU. In this case, there is an effect that the master CPU can be reliably reset to prevent system runaway.

[Brief description of drawings]

FIG. 1 is a block diagram showing the configuration of an embodiment of the present invention.

FIG. 2 is a timing chart showing the operation of the embodiment of the present invention.

FIG. 3 is a block diagram showing a configuration of a conventional example.

FIG. 4 is a block diagram showing a configuration of a conventional example.

[Explanation of symbols]

 1 Master CPU power supply 2 Master CPU 3 Master CPU power-on reset generator 4 Control block 5 Power-on reset signal control circuit 6 Rising edge detection circuit 40 Slave CPU side power supply 41 Slave CPU 42 Slave CPU power-on reset generator 51 , 61 Inversion circuit 52 NAND circuit 53, 62 Delay circuit 54, 63 AND circuit

Claims (3)

[Claims] 1. A reset control circuit for a multiprocessor system comprising a master processor and a slave processor, which are supplied with power sources independent of each other, wherein the reset control circuit is provided in the master processor and controls ON / OFF of the power source of the slave processor side. Means for detecting a voltage change of the power source on the slave processor side and generating a power-on reset signal, and means for detecting the generation of the power-on reset signal and resetting the master processor. Characteristic reset control circuit. 2. The reset control circuit according to claim 1, wherein the means for detecting generation of the power-on reset signal includes an edge detection circuit for detecting an edge of a change point of the power-on reset signal. 3. A means for resetting the master processor, wherein at least one of a power-on reset signal generated when a voltage change of a power supply on the master processor side and a voltage change of a power supply on the slave processor side is detected. 3. The reset control circuit according to claim 1, wherein the reset control circuit is configured to reset the master processor when detected.