JPS6389941A - Monitor and control equipment for microprocessor applied equipment - Google Patents

Abstract

PURPOSE:To perform simultaneous control for initialization, an urgent processing, and restart-up, by using the interruption input terminal of a CPU commonly for a power source abnormal disconnection signal and a stop detection monitoring timing signal, and the reset input terminal for initialization signals at the times of applying a power source and detecting the stop of the power source. CONSTITUTION:The CPU (a), when accepting an interruption signal E at the interruption input terminal (d), refers the power source abnormal disconnection signal C supplied from a power source abnormal disconnection signal supplying circuit (h) as an interruption processing. And when the signal C is set in an ON state, a prescribed urgent processing is executed. Also, when it is set in an OFF state, a stop detection reset signal F is outputted to a stop detection circuit (c). Also, when the initialization signal B from a first OR circuit (k) being inputted to the rest input terminal (e) of the CPU (a), is turned ON, a stop detection holding signal H being inputted from a state holding circuit (i) is referred. When the signal H is set at the On state, the output of the reset signal is outputted to the stop detecting circuit (c), and also, a signal J to cut off a power source circuit (f) is outputted, and when it is set in the OFF state, a regular operation is started.

Description

[Detailed Description of the Invention] [Field of Industrial Application] The present invention is applicable to microprocessor-applied equipment, including initial settings of a microprocessor system at startup, emergency processing when power is cut off during operation, and operation stoppage due to noise, etc. The present invention relates to a monitoring and control device that enables efficient monitoring and control of three functions and operations for restarting a computer.

[Conventional technology]

In recent years, microprocessors have been widely applied to equipment such as office equipment and communication equipment. The environments in which these devices are used are also wide-ranging, and in many cases they are not necessarily used in environments with adequate vibration, noise, power supply, etc.

In such an environment, a significant portion of failures that occur in these devices are due to runaway microprocessors or malfunctions of the microprocessors. In the event of such a failure, if the user notices the failure, he or she can recover by manually turning off part of the power and then turning it back on again using the power-on reset function of the equipment. However, when operating unmanned, it may cause serious accidents or unnecessary wear and waste. In order to solve such problems, it is necessary to strengthen the resistance against the environment and add functions such as restarting when the operation stops.

- Figure 3 shows a block diagram of the general concept of the restart method when operation is stopped. To explain the outline of the operation with reference to the same figure, the timer circuit issues an interrupt to the interrupt input terminal d of the central processing unit (CPU) a at a constant cycle, and the (CPU) a sends a normal operation signal as an interrupt process. The stop detection circuit C restarts the system by sending a reset signal to the reset input terminal e of the CPU when the normal operation signal disappears. It is something to do.

Next, Fig. 4(a) shows how to initialize the system when the main power is turned on, and Fig. 4(b) shows how to deal with an abnormal power cut during operation.
Each is shown.

In the former, a power-on reset circuit g that constitutes a part of the power supply circuit f inputs a reset signal when the power is turned on as an initial setting signal (a) to the reset terminal e of the (CPU) a, and initializes the system. It will be done. In the latter case, the power supply abnormality detection circuit that constitutes a part of the power supply circuit f,
A signal indicating an abnormal power outage during operation is input to the interrupt terminal d of (CPU) a, and the CPU executes emergency processing.

Now, in realizing the circuit operation shown in Figure 3, (CPU) a
It is essential that the interrupt input terminal d of the interrupt input terminal d is always capable of accepting interrupts (non-masked), but there is normally only one such terminal, and moreover, there is usually only one, as shown in Fig. 4(b). It is already used as an emergency interrupt to save important data and perform fail-safe processing of the input/output section in the event of a power failure during operation, so it is necessary to share this function and the terminal and distinguish the subsequent operation. be.

Furthermore, as shown in Figure 4(a), the reset input terminal e of the CPU is normally used for initializing the entire system (power-on reset) when the main power is turned on at the beginning of use. In this case, the terminals are also shared, and if it is necessary to distinguish subsequent operations, some kind of function must be added.

[Problem that the invention seeks to solve]

Traditionally, the initial system settings at startup, emergency processing when the power supply is abnormally cut off during operation, and restarting when operation stops due to noise, etc. have been handled separately, but these three functions can be performed simultaneously. If this is to be realized, it will be necessary to add identification control functions for the three functions.

The problem to be solved by the present invention is to simultaneously realize these three functions in a microprocessor-applied device. Therefore, the purpose of the present invention is to perform three functions in microprocessor-applied equipment: initial system settings at startup, which have conventionally been individually controlled; emergency processing when the power supply is abnormally cut off during operation; and restart when operation stops due to noise, etc. An object of the present invention is to provide a monitoring and control device for microprocessor-applied equipment that enables simultaneous control of functions.

[Means for solving problems]

The present invention uses the highest priority non-masked interrupt terminal of the central processing unit to receive two signals: a monitoring timing signal that triggers an operation stop detection operation, and an abnormal power disconnection signal that triggers emergency processing in the event of an abnormal power disconnection during operation. In addition, the reset input terminal of the central processing unit can be used as a power-on initial setting signal when the equipment is powered on, and as a stop detection circuit. The stop detection initial setting signal is shared by the CPU, and the distinction is made by referring to the stop detection holding signal after the central processing unit is reset.Once the stop detection circuit detects that the central processing unit has stopped operating, the central processing The main feature for solving the problem is to hold the stop detection holding signal until receiving the stop detection recent signal given from the device.

In a microprocessor-applied device that includes a central processing unit equipped with a reset input terminal and a constant top-priority interrupt input terminal, and is attached with a power supply circuit, a timer circuit that outputs a monitoring timing signal at a constant cycle, and a starts operation according to a monitoring timing signal of the central processing unit, and outputs a stop detection initial setting signal when the stop detection reset signal from the central processing unit does not arrive within a certain predetermined time, and also outputs the stop detection initial setting signal. a stop detection circuit for holding the stop detection reset signal until the stop detection reset signal is input, and outputting the stop detection holding signal from the state holding circuit to the central processing unit; and the power supply circuit. From the power-on reset circuit inside the
The power-on initial setting signal that is output when the power is turned on and the stop detection initial setting signal that is output from the stop detection circuit are logically summed, and the result is used as an initial setting signal to be sent to the reset input terminal of the central processing unit. A first OR circuit outputs, a monitoring timing signal outputted from the timer circuit, and a power abnormality detection circuit inside the power supply circuit, which outputs power when the power being supplied from the power supply circuit stops. a second OR circuit that calculates a logical sum with the abnormality disconnection signal and outputs the result as an interrupt signal to the interrupt input terminal of the central processing unit; and a power supply abnormality signal supply circuit that also supplies the power supply to the processing device.

[Effect]

When the central processing unit receives an interrupt signal at its interrupt input terminal, the central processing unit performs interrupt processing by turning on the signal by referring to the power abnormality disconnection signal supplied from the power abnormality disconnection signal supply circuit. If (valid), the specified emergency processing will be carried out.
If it is off, a stop detection reset signal is output to the stop detection circuit, and the initial setting signal from the first OR circuit input to its reset input terminal is turned on (
When it becomes valid), it refers to the stop detection holding signal input from the state holding circuit and if the signal is on,
A stop detection reset signal is output to the stop detection circuit, and a signal for disconnecting the power supply circuit is output, and if it is off, normal operation is started.

Previously, three functions were handled individually: initial settings when turning on the power to equipment, emergency processing when the power supply is abnormally cut off during operation, and detection and restart of central processing unit operation, and it is now possible to realize these three functions simultaneously. There is no concrete example of this, and even if an attempt was made to simply implement the three functions, it would be impossible due to the limitations of the input terminals of the central processing unit, as described above.

〔Example〕

The present invention will now be described in detail with reference to the drawings.

FIG. 1 is a block diagram showing one embodiment of the present invention. In the figure, a is a central processing unit, d is its interrupt input terminal (highest priority, non-masked), and e is a reset input terminal.

A timer circuit b generates a monitoring timing signal (1) at certain regular intervals, and this signal is connected to a stop detection circuit C and an OR circuit j. Stop detection circuit C is central processing bag Wa
A stop detection reset signal (power) is inputted via the bus interface BS between the terminals and the stop detection holding signal (ri) is output from the internal state holding circuit i.

The stop detection circuit C knows that its operation has stopped because the stop detection reset signal (power) from the central processing unit a has disappeared, and outputs a stop detection initial setting signal (K) to the OR circuit k. The internal state holding circuit i is operated to hold the stop detection holding signal (ri) from the state holding circuit i until the initial setting of the central processing unit a is completed and the central processing unit a refers to the stop detection holding signal (ri) from the state holding circuit i.

f is a power supply circuit, and its internal circuit, the power supply abnormality detection circuit, outputs a power supply abnormality disconnection signal (x) when a power supply abnormality occurs during system operation;
The other signal is input to the central processing unit a via S, and the other signal is directly input to the OR circuit j. Further, the power-on reset circuit g, which is an internal circuit, outputs a power-on initial setting signal (k) to the OR circuit k when the power is turned on.

Note that the central processing unit a outputs a power-off instruction signal (k) for automatic power-off to the power supply circuit f via the bus interface BS.

The OR circuit j calculates the logical sum of the monitoring timing signal from the timer circuit S and the power supply abnormality disconnection signal (two) from the power supply abnormality detection circuit f, and uses this as an interrupt signal (O) to output the highest value of the central processing word Wa. Output to priority/non-masked interrupt input terminal d. The OR circuit calculates the logical sum of the stop detection initial setting signal (k) from the stop detection circuit C and the power-on initial setting signal (k) from the power-on reset circuit g, and converts this into the initial setting signal (a). It is output to the reset input terminal e of the central processing unit a.

FIG. 2 is a flowchart for explaining a monitoring and control method for obtaining a desired function in the embodiment (configuration) of the present invention shown in FIG. This is a monitoring flow for detecting a stoppage of device a.

A monitoring timing signal (1
) is logically summed with the power supply abnormality disconnection signal (X) from the power supply abnormality detection circuit via the OR circuit j, and then input as an interrupt signal (O) to the interrupt input terminal d of the central processing unit a. In response to this interrupt input signal (O), the central processing unit a starts executing the interrupt process specified by the interrupt vector.

First, it is determined whether the interrupt factor is due to the abnormal power interruption signal (2) or the monitoring timing signal (1) by referring to the abnormal power interruption signal (2) via the bus interface BS.

As a result of the reference, if the cause is the former, it is a power failure, so jump to the corresponding emergency process and execute that process.
If the cause is the latter, the interruption processing is terminated after outputting the stop detection reset signal (force) to the stop detection circuit C via the bus interface BS, and the original processing that was interrupted is resumed. Return to.

At this time, if the stop detection reset signal (force) from the central processing unit a arrives within a certain period of time after the input of the monitoring timing signal, the stop detection circuit C operates to generate the stop detection initial setting signal (K) and hold the stop detection. If the stop detection reset signal (force) does not arrive, the two signals are generated.

Note that the state holding circuit i that generates the stop detection holding signal (ri) loses the stop detection initial setting signal (k) when the entire system including the stop detection circuit C is initialized by the initial setting signal. This is to make it possible since it is impossible to determine the cause of the initial settings after the initial settings. Further, the state holding circuit i is reset by a stop detection reset signal (force).

FIG. 2(b) is an initial setting control flow.

The initial settings are triggered when you turn on the power to use the device (
(can be done manually or automatically), and when the above-mentioned figure 2 (
This is a case where the operation stoppage of the central processing unit is detected according to the flow of a).

In order to differentiate the subsequent operations as follows depending on the factors of this initial setting, after executing the initial setting on the hardware, the central processing unit a refers to the stop detection holding signal (ri). As a result of the reference, if the stop detection holding signal (RI) is off, it can be assumed that the power has been turned on normally, and normal operation is started. If this signal is on, it can be considered that the operation of the central processing unit a has stopped, so after outputting the stop detection reset signal (power) and resetting the stop detection circuit C and the state holding circuit i, Generates an alarm with a sound or display message, etc., and after executing this for a certain period of time, sends a power-off instruction signal (
), which automatically turns off the system power.

Note that when determining the cause of the interrupt signal, it is also possible to refer to the monitoring timing signal (1) instead of the power supply abnormality cutoff signal (2).

By adopting the above configuration and the monitoring and control method that makes it function, the only highest priority interrupt input terminal of the central processing unit can be shared by the power supply abnormality disconnection signal and the monitoring timing signal for stop detection, and it is possible to In addition, the only reset input terminal of the central processing unit is shared by the initial setting signal at power-on and the initial setting signal at the time of stop detection, and it is possible to determine which one is causing the reset. As a result, it is possible to effectively perform three functions in microprocessor-applied equipment: initial system settings at startup, emergency processing when power is cut off during operation, and restart when operation stops due to noise, etc. It has become possible to monitor and control three functions that were previously impossible.

〔Effect of the invention〕

As explained above, the present invention simultaneously realizes, in a single microprocessor-applied device, the following functions: initial system settings at startup, emergency processing when power is cut off during operation, and restart when operation stops due to noise, etc. This is effective in improving the safety of the system (equipment).

[Brief explanation of the drawing]

Fig. 1 is a block diagram showing an embodiment of the present invention, Fig. 2 is a monitoring/control flow diagram in the embodiment of the present invention, Fig. 3 is a conceptual diagram of a conventional restart method when operation is stopped, and Fig. 4 is a conceptual diagram of the conventional system initial settings and how to deal with power failure. Explanation of symbols a...Central processing unit, b...Timer circuit, C...
Stop detection circuit, d... Interrupt input terminal, e... Reset input terminal, f... Power supply circuit, g... Power-on reset circuit, h... Power supply abnormality detection circuit, i... Status Holding circuit, j, k...OR circuit, (A)...Normal operation signal, (B)...Initial setting signal, (T)...Power supply abnormality cutoff signal, (1)...Monitoring Timing signal, (o)...Interrupt signal, (force)...stop detection reset signal, (ki)...stop detection initial setting signal, (ri)...
Stop detection holding signal, (k)...Power-on initial setting signal, (k)...Power-off instruction signal.

Claims (1)

[Claims] 1) A timer that outputs a monitoring timing signal at a constant cycle in a microprocessor-applied device that includes a central processing unit equipped with a reset input terminal and a constant top priority interrupt input terminal and is attached with a power supply circuit. circuit and a monitoring timing signal from the timer circuit to start operation, and if the stop detection reset signal from the central processing unit does not arrive within a predetermined time, output a stop detection initial setting signal and at the same time , comprising a state holding circuit for holding the stop detection initial setting signal until the stop detection reset signal is input, and outputting the stop detection holding signal from the state holding circuit to the central processing unit. A detection circuit and a power-on reset circuit inside the power supply circuit calculate the logical sum of a power-on initial setting signal output when the power is turned on and a stop detection initial setting signal output from the stop detection circuit. a first OR circuit that outputs the result as an initial setting signal to the reset input terminal of the central processing unit; a monitoring timing signal output from the timer circuit; and a power supply abnormality detection circuit within the power supply circuit;
A second controller that calculates a logical sum with a power abnormality disconnection signal that is output when the power being supplied from the power supply circuit stops, and outputs the result as an interrupt signal to the interrupt input terminal of the central processing unit. an OR circuit, and a power abnormality disconnection signal supply circuit that also supplies an abnormal power disconnection signal from the power abnormality detection circuit to a central processing unit, and the central processing unit receives an interrupt signal at its interrupt input terminal. is received, as an interrupt process, the abnormal power failure signal supplied from the abnormal power failure signal supply circuit is referenced, and if the signal is on (valid), the specified emergency process is turned off. If so, a stop detection reset signal is output to the stop detection circuit, and when the initial setting signal from the first OR circuit input to the reset input terminal is turned on (valid), the stop detection reset signal is output to the stop detection circuit. Referring to a stop detection holding signal inputted from the state holding circuit, if the signal is on, outputting a stop detection reset signal to the stop detection circuit and outputting a signal for disconnecting the power supply circuit; A monitoring and control device for microprocessor-applied equipment, characterized in that it starts normal operation if it is off.