JPH0535460B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a computer system having a plurality of central processing units.

[Conventional technology]

Conventionally, in this type of computer system, when one central processing unit malfunctioned, the other central processing units were notified of the failure by communication between the central processing units and mutual confirmation. .

[Problem that the invention seeks to solve]

The conventional computer system monitoring method described above becomes more difficult as the number of central processing units increases.
This has the disadvantage of reducing system performance due to increased communication between central processing units.

[Means for solving problems]

The computer system of the present invention interprets that a failure has occurred when the program processing by the central processing unit does not end within a preset monitoring time, and selects a preset number of 1 to 1 for each central processing unit. A time monitoring device is provided that causes an interrupt to a plurality of other central processing units and notifies them, and each central processing unit sets the monitoring time and the central processing unit that causes the interrupt to the corresponding time monitoring device. The present invention is characterized by comprising a control means for transmitting an operation start command to start a time monitoring operation after the time monitoring operation is performed.

Therefore, communication between central processing units does not increase and system performance does not deteriorate.

〔Example〕

Embodiments of the present invention will be described with reference to the drawings.

FIG. 1 is a schematic diagram of an embodiment of a computer system according to the present invention.

The computer system of this embodiment includes two central processing units 1 and 3, time monitoring devices 2 and 4 that monitor the processing time of programs executed by the central processing units 1 and 3, respectively, and an input/output control device 6, 7
and a program or input/output control device 6 or 7 executed by the central processing unit 1 or the central processing unit 3.
A memory device 5 in which data transferred between the two is stored is connected to a common bus 8 of the system.

When initializing the system, the central processing units 1 and 3 send a command to set the monitoring time to the time monitoring units 2 and 4, respectively, and then send a command to the central processing unit 3, which is the notification destination in the event of a failure. , 1 is transmitted, and thereafter a command to start the monitoring operation of the time monitoring devices 2 and 4 is transmitted. Note that the processing time of one program executed by the central processing units 1 and 3 is
It is designed to be completed within the time monitored by Each time the central processing unit 1 processes one program, the time monitoring devices 2 and 4 are started, and the time monitoring devices 2 and 4 are activated by the central processing units 1 and 3.
Monitor the processing time of programs executed in .

FIG. 2 is a block diagram of the time monitoring device 2 (the same applies to the time monitoring device 4).

The bus control circuit 22 transmits and receives signals to and from the central processing units 1 and 3 via the common bus 8. The bus register control circuit 22 has an internal register, and the monitoring time sent from the central processing unit 1 and the number of the notification destination information processing device (in this case, the central processing unit 3) when a failure occurs are held in this register. be done. The memory 24 stores the monitoring time set in the bus register control circuit 21 and the number of the notification destination information processing device 3. When the processor 23 detects the operation start command sent from the central processing unit 1, it sets the monitoring time stored in the memory 24 in the time monitoring circuit 25, activates the time monitoring circuit 25, and transmits the monitoring time via the signal line 52. When notified that the monitoring time has passed, the bus register control circuit 21 stores the number of the central processing unit 3 stored in the memory 24.
, and activates the bus control circuit 22 to generate an interrupt. When the processor 23 detects the operation start command transmitted from the central processing unit 1, the time monitoring circuit 25 sets the monitoring time stored in the memory 3 and starts time monitoring, and the time monitoring circuit 25 starts time monitoring for a predetermined period of time. When elapses, the internal counter is decremented by 1, and when it reaches zero, it is notified to the processor 23 via the signal line 52.

Next, the operation of this embodiment will be explained.

In initializing the system, the central processing unit 1 sends a command to the time monitoring device 2 to set a monitoring time. Upon receiving the time setting command from the central processing unit 1, the time monitoring device 2 controls the bus control circuit 22.
The set time is set in the register in the bus register control circuit 21 and at the same time is notified to the processor 23 via the signal line 51. When the processor 23 detects this, it transfers the setting time set in the register in the bus register control circuit 21 to the memory 2.
Store it in the designated area in step 4. The central processing unit 1 then sends a command to the time monitoring device 2 to set the number of the central processing unit 3 in order to notify the central processing unit 3 of any subsequent failure. Upon receiving a command to set the number of the central processing unit 3 from the central processing unit 1, the time monitoring device 2 uses the bus control circuit 22 to set the number to the bus register control circuit 21.
At the same time, processor 2
3 via the signal line 51. processor 2
3 stores the number of the set time in a designated area of the memory 24.

When the above processing is completed, the central processing unit sends an operation start command to start the operation of the time monitoring device 2. When the time monitoring device 2 receives an operation start command from the central processing unit 1 through the bus control circuit 22, the processor 22 similarly detects this and interprets it as the start of operation, and outputs the settings stored in a designated area of the memory 24. The operation is started at the same time as the time value is set in the time monitoring circuit 25. Time monitoring circuit 2
5 sets an internal counter to -1 when a predetermined time has elapsed. This operation is repeated until the next operation start command is received from the central processing unit 1, but when the next operation start command is received, the time monitoring circuit 25 is reset, the set time value is fetched from the memory 24 again, and the time The monitor circuit 25 is set, and the above operation is repeated.

Now, if the start command is not received from the central processing unit 1 due to some failure, the counter in the time monitoring circuit 25 becomes zero and this is notified to the processor 23 via the signal line 52. When the processor 23 detects this, it interprets it as a failure in the program processing by the central processing unit 1, and sets the number of the central processing unit 3 stored in a designated area of the memory 24 in the bus register control circuit 21 in advance. Then, the bus control circuit 22 is activated and an interrupt is generated.

As described above, when a failure occurs in the processing by the central processing unit 1, the time monitoring device 2 can cause an interrupt to the central processing unit 3 to notify it.

Further, when a failure occurs in processing by the central processing unit 3, the central processing unit 1 is similarly notified by an interrupt. In addition, in this embodiment, the central processing unit is
If the central processing unit is connected to three
The present invention can be similarly applied to cases where the number of units is more than 1000 yen.

〔Effect of the invention〕

As explained above, the present invention provides a time monitoring device, and when the processing of a program by a designated central processing unit does not end at a time other than the designated time, it is interpreted that a failure has occurred. By causing an interrupt in multiple other central processing units to notify them, communication between central processing units does not increase, and
This has the effect that system performance does not deteriorate.

[Brief explanation of the drawing]

FIG. 1 is a schematic diagram of an embodiment of the computer system of the present invention, and FIG. 2 is a block diagram of the time monitoring device 2 shown in FIG. 1, 3... Central processing unit, 2, 4... Time monitoring device, 5... Memory device, 6, 7... Input/output control device, 8... Common bus, 21... Bus register control circuit, 22... ... Bus control circuit, 23 ... Processor, 24 ... Memory, 25 ... Time monitoring circuit.

Claims (1)

[Claims] 1. In a computer system having a plurality of central processing units, a failure occurs when program processing by the central processing unit does not finish within a preset monitoring time corresponding to each central processing unit. A time monitoring device is provided that interprets the time as the current time and interrupts one or more other central processing units set in advance to notify the user of the interruption, and each central processing unit monitors the corresponding time monitoring device. 1. A computer system with a failure detection function, comprising a control means for transmitting an operation start command to start a time monitoring operation after setting a central processing unit that causes a time and interrupt.