JPH06149686A - Channel interruption control system - Google Patents

Abstract

PURPOSE:To attain the accurate timer monitoring of a DMAC and to reduce overhead by providing an operation status informing terminal and a stop terminal at every channel of the DMAC, directly activating/stopping a timer by hardware, and at the time of generating time-out, directly stopping a CMA in the DMAC. CONSTITUTION:At the time of activating the DMAC 11, the timer 2 is directly activated by an operation status informing signal outputted from an operation status informing terminal 12 at every channel, and at the time of generating time-out, a stop signal is inputted to the stop terminal 13 so as to directly stop the operation of the DMAC 11. An interruption signal IRQ generated with the stop signal obtained when the timer 2 generates time-out as one of interruption factors is informed to a DMA requesting source to generate an interruption, the effect of the stop signal generated at the time of time-out in the interrupting processing is read out from a buffer 17 as status and a DMA transfer requesting source is allowed to recognize the generation of time-out.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a channel interrupt control system which controls a timer by monitoring a timer for each channel.

[0002]

2. Description of the Related Art Conventionally, an IC having a DMAC and I / O control on one chip as shown in FIG. 5 operates a channel from the outside when a timer monitoring from start to stop of DMA transfer of I / O is performed. Since there is no signal terminal for checking the status or a signal terminal for stopping the channel from the outside, the timer was monitored by software. The configuration and operation of FIG. 5 will be briefly described below.

In FIG. 5, a DMAC 21 controls data transfer between memories. I / O control 22
Controls input / output to / from the I / O.

The data bus control 23 controls input / output to / from the data bus. The timer 24 measures time. The MPU 25 performs various processes according to a program, and here, when the DMA transfer is activated, the timer 24 is activated by software to monitor the timeout.

Next, the operation will be described. (1) DM that has accepted the activation of DMA from the MPU 25
The AC 21 starts the DMA transfer. At this time, MPU2
5 activates the timer 24 by software.

(2) When the DMAC 21 normally completes the DMA transfer, the MPU 2 receives an interrupt of * IRQ.
5 is notified of the normal end. On the other hand, when the DMA transfer does not end due to some failure, the MPU 25 notified by the timer 24 started in (1) by the interrupt indicating the timeout determines that the DMA transfer has failed.

[0007]

As described above, since the timer 24 is conventionally activated by software, there is a problem that a software process is required to activate the timer 24 and the start is delayed. For example, as shown in FIG. 6, when the transmission DMA operation is performed at the position and the reception DMA operation is performed next, the timer 24 is activated by software when the reception DMA operation is activated. It cannot be done because reception may start first. Therefore, the timer start is performed by software at the position.

However, starting the timer at this position requires a process for changing the timer value by software depending on the transmission data length, and if the timer 24 is often used by software, the OS will be There was a problem that the overhead increased and the overall processing speed decreased.

The present invention solves these problems.
The purpose of the present invention is to provide an operating state notification terminal and a stop terminal for each channel of the DMAC to start / stop the timer by hardware to realize accurate timer monitoring and reduce overhead.

[0010]

[Means for Solving the Problems] Means for solving the problems will be described with reference to FIG. In FIG. 1, the DMAC
11 and I / O control 14 are integrated into one chip IC1
Etc., and performs DMA transfer control.

The operating state notifying terminal 12 is a terminal for notifying the operating state of the DMAC 11 to the outside. The stop terminal 13 is a terminal for stopping the DMAC 11 from the outside.

The timer 2 measures the time and sends out a timeout when a predetermined time has elapsed.

[0013]

According to the present invention, as shown in FIG. 1, when the DMAC 11 is started, the timer 2 is directly started by the operation status notification signal from the operation status notification terminal 12 for each channel, and when the time-out occurs, the stop signal is stopped. The operation of the DMAC 11 is directly stopped by inputting it to the line 13.

An interrupt signal I generated by using a stop signal when the timer 2 times out as one of interrupt factors.
The RQ is notified to the DMA request source to generate an interrupt, and the status indicating that it is a stop signal when a timeout occurs during the processing of this interrupt is read from the buffer 17,
The DMA transfer requester recognizes that a time-out has occurred.

Therefore, the timer 2 is provided with the operation state notification terminal 12 and the stop terminal 13 for each channel of the DMAC 11.
The DMAC by starting / stopping the
It is possible to realize 11 accurate timer monitoring and reduce the overhead.

[0016]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS Next, the construction and operation of an embodiment of the present invention will be described in detail with reference to FIGS.

FIG. 1 shows a block diagram of an embodiment of the present invention.
In FIG. 1, IC1 is a DMAC 11 and I / O control 1
4, an IC in which the data bus controller 15, the OR circuit 16, the buffer 17, and the like are integrated in one chip, and controls data transfer between memories.

The DMAC 11 controls the DMA transfer, and is provided with an operation state notification terminal 12 and a stop terminal 13 for each channel to send an operation state notification signal to the outside or take in a stop signal from the outside. And so on. The operation state notification signal transmitted from the operation state notification terminal 12 to the outside is a signal indicating that the channel of the DAMC 11 has started DMA transfer. The stop signal input from the stop terminal 13 is the DM of the corresponding channel of the DMAC 11.
This is a signal for stopping A transfer. Where DMAC11
Internally, * INT is generated when the count of the byte counter is completed during DMA transfer, the end code of the I / O control unit 14 is detected, or a transfer error occurs, and the OR circuit 16 performs an OR operation with other interrupt factors. And generate * IRQ,
Interrupt notification is sent to MPU3.

The I / O control 14 controls the data transfer to the I / O, such as sending output data to the I / O and fetching input data from the I / O. It is composed of an input control unit that takes in input data from the I / O and an output control unit that sends output data to the I / O.

The data bus controller 15 controls the input / output of data to / from the data bus. OR circuit 16
Is a circuit for performing a logical sum operation of the timeout (stop signal) for each channel from the timer 2 and * INT (interrupt signal for notifying completion of DMA transfer) from the DMAC 11. The signal * IRQ obtained as the result of the logical sum operation in the OR circuit 16 is input to the MPU 3 as an interrupt signal.

The buffer 17 is a buffer for the MPU 3 to read the interrupt factor in the interrupt processing when the interrupt is generated by * IRQ. Timer 2
Is for measuring time, and here is the DMAC.
A timer is started when an operation status notification signal for each channel is input from the operation status notification terminal 12 of 11 or a stop signal is sent to the stop terminal 13 of the DMAC 11 when a preset time elapses and a timeout occurs. To stop the DMA operation for each channel of the DMAC 11 concerned.

The MPU 3 performs various controls according to a program, and here, a DMA transfer request is DMed.
Notify AC11 or * IR from DMAC11 etc.
The content of the buffer 17 is read in the interrupt process activated by the interrupt by Q to recognize which interrupt factor (timeout, normally completed DMA transfer requested, etc.).

Next, the operation of the configuration of FIG. 1 during normal DMA transfer will be described in detail with reference to FIG. In FIG. 2, S1
Accepts activation of DMA from the MPU. this is,
The DMAC 11 of FIG. 1 starts the DMA from the MPU 3 (D
(Activation of MA transfer) is accepted.

In step S2, DMA is activated. This is DMA
In response to the C11 accepting the DMA activation in S1, the DMA transfer is activated. In S3, DMA transfer is performed.
This transfers data between memories under the control of the DMAC 11.

At this time, the timer is started by the operation state notification signal in S7. This sends an operation state notification signal from the operation state notification terminal 12 of the DMAC 11 to the timer 2,
Start the timer directly.

In step S4, the DMA transfer ends. At this time, S
The timer stops at 8. This causes the DMAC 11 to deactivate the operation state notification signal from the operation state notification terminal 12 of the DMAC 11, and stops the timer 2.

In step S5, the MPU is notified of interruption. This corresponds to the fact that the DMAC 11 has completed the DMA transfer normally in S4 and inputs * INT to the OR circuit 16 to input * I.
The RQ notifies the MPU3 of interruption.

In step S6, the MPU 3 reads the status and DMs
A is recognized as completed. This is because the MPU 3 which has received the interrupt notification in S5 reads the contents of the buffer 17 during the interrupt processing, recognizes that the interrupt notification is based on * INT, and judges that the DMA transfer is normally completed.

As described above, the DMAC 11 accepts the DMA activation, the DMA activation is performed, and the operation state notification terminal 1
2 notifies the external timer 2 of the operation state notification signal and starts the timer. In this case, since the DMA transfer is normally completed, the interrupt is notified to the MPU 3 triggered by * INT,
During the interrupt process, the MPU 3 determines that the DMA transfer is normally completed. At this time, since the timer 2 is directly activated by the operation state notification signal sent from the operation state notification terminal 12 to the outside, there is no delay in starting the timer and no burden on the MPU 3.

Next, referring to FIG. 3, FIG.
The operation of the above configuration will be described in detail. In FIG. 3, S11
Accepts activation of DMA from the MPU. this is,
The DMAC 11 of FIG. 1 starts the DMA from the MPU 3 (D
(Activation of MA transfer) is accepted.

In step S12, DMA is activated. This is DM
In response to the AC11 accepting the DMA activation in S11, the DMA transfer is activated. In S13, DMA transfer is performed. This transfers data between memories under the control of the DMAC 11.

At this time, the timer is started by the operation state notification signal in S15. This sends an operation state notification signal from the operation state notification terminal 12 of the DMAC 11 to the timer 2 to directly start the timer.

In S16, a time-out occurs. This means that the timer 2 is timer-started in S15, and a timeout occurs after a preset predetermined time has elapsed. S1
7 notifies the MPU of interruption. This is directly received from the timer 2 and an interrupt is notified to the MPU. That is, in response to the time-out of the timer 2 in S16, the time-out signal (stop signal) is directly input to the DMAC 11 via the stop terminal 13, and the OR circuit 1
The interrupt is notified to the MPU 3 as * IRQ via 6.

At this time, in S14, the DMAC which directly receives the stop signal (timeout signal) from the stop terminal 13
11 forcibly stops the DMA transfer. S18 is MP
U reads the status and determines that it has timed out. This is because the MPU 3 which received the interrupt notification in S17 reads the contents of the buffer 17 during the interrupt processing, recognizes that the interrupt notification is due to a timeout, and determines that the DMA transfer has timed out.

As described above, the DMAC 11 accepts the DMA activation, the DMA activation is performed, and the operation state notification terminal 1
2 notifies the external timer 2 of the operation status notification signal and starts the timer. In this case, the DMA transfer does not end normally, and an interrupt is issued when the time-out triggers the MPU 3
In the interrupt processing, the MPU 3 determines that the DMA transfer ended abnormally due to a timeout. At this time,
The timer 2 is directly activated by the operation status notification signal sent from the operation status notification terminal 12 to the outside, and the timeout signal (stop signal) is directly input to the stop terminal 13 of the DMAC 11 at the time-out to stop the DMA transfer and * I.
Since the interrupt notification is sent to the MPU 3 by the RQ, there is no delay in the start of the timer start, and the overhead is reduced without burdening the MPU 3 for starting the timer 3 or stopping the DMA transfer of the DMAC 11 at the time-out. .

FIG. 4 shows an operation explanatory diagram of the present invention. This is a time chart in the configuration of FIG. FIG. 4A shows a normal time chart. This is shown in Figure 2.
7 is a time chart at the time of normal DMA transfer. here,
* CH * ST is the operating state notification terminal 12 of the DMAC 11.
Is an operation state notification signal transmitted from each channel at the time of starting the DMA transfer, such as * CH0ST (channel CH0 operation state notification signal) or * CH1ST (CH1 operation state notification signal).

* TOUT * is a signal (stop signal) for each channel transmitted when the timer 2 times out, and is * TOUT0 (timeout signal of channel CH0) or * TOUT1 (timeout signal of channel CH1). is there.

* INT is a signal transmitted when the DMA transfer of the DMAC 11 is completed normally. In (a) of FIG. 4, * CH * ST (operating state notification signal) becomes active in response to DMA activation, and the DMAC 11 sends this operating state notification signal to the timer 2
Is activated to activate the system (S7 of FIG. 2).

In response to the occurrence of an interrupt request in the chip, the above-mentioned signal is sent * INT to notify the MPU 3 of the end of the DMA transfer by an interrupt, and * CH * ST is made inactive to operate the timer 2. To stop.

By the above, the DMAC 11 is DMA
When it is activated, the timer 2 is directly activated by * CH * ST, the termination is notified to the MPU 3 by * INT at the end of the DMA transfer, and the timer 2 is stopped by deactivating * CH * ST. With these, start of timer 2,
It is possible for the DMAC 11 to directly stop the signal using * CH * ST (operation status notification signal), thereby not burdening the MPU 3 and starting it up without delay.

FIG. 4B shows a time chart at the time of timeout. This is a time chart at the time of timeout in FIG. Where * CH * ST, * TOUT
Since * and * INT are the same as in (a) of FIG. 4,
The description is omitted.

In FIG. 4B, * CH * ST (operating state notification signal) becomes active in response to DMA activation, and the DMAC 11 notifies the timer 2 of this operating state notification signal. It is activated and brought into an operating state (S15 in FIG. 3).

In response to the timer 3 having timed out, * TOUT * (stop signal) is sent to the DMAC1.
Input to 1 to stop DMA transfer. To be more specific, *
TOUT * (stop signal) is sent and input from the stop terminal 13 of the DMAC 11, and the DMAC 11 is directly DMA-transmitted.
Stop * MPMP * IRQ via OR circuit 16
The U3 is notified and the MPU 3 reads the timeout from the buffer 17 and recognizes it in the interrupt. And DM
The AC 11 inactivates * CH * ST and activates * INT when necessary.

By the above, the DMAC 11 is DMA
When it is started, * CH * ST is used to directly start timer 2, and when a timeout occurs in, * TOUT * is set to D
Directly input to MAC11 to stop DMA and * IRQ
To the MPU 3 to notify the end of the timeout. With these, the start and stop of the timer 2 is DMA
C11 directly uses * CH * ST (operation status notification signal), and * TOUT * when timeout occurs
DMA by the DMAC 11 directly by (stop signal)
This makes it possible to stop the operation so that the MPU 3 is not burdened and the timer can be started without delay.

[0045]

As described above, according to the present invention,
The operation state notification terminal 12 and the stop terminal 13 for each channel of the DMAC 11 are provided to directly start / stop the timer 2 by hardware, and when the time-out occurs, the DMAC 11
Since the DMA is stopped directly, it is possible to realize accurate timer monitoring of the DMAC 11 and reduce the overhead. Also, DM
Space can be saved by accommodating the AC 11 and the I / O control 14, and the necessary external circuits (OR circuit 16, buffer 17, etc.) in the chip.

[Brief description of drawings]

FIG. 1 is a configuration diagram of an embodiment of the present invention.

FIG. 2 is a flowchart at the time of normal DMA transfer of the present invention.

FIG. 3 is a flowchart of the present invention at the time of timeout.

FIG. 4 is an explanatory diagram of the operation of the present invention.

FIG. 5 is a configuration diagram of a conventional technique.

FIG. 6 is an operation explanatory diagram of a conventional technique.

[Explanation of symbols]

 1: IC 11: DMAC 12: Operating state terminal 13: Stop terminal 14: I / O control 15: Data bus control 16: OR circuit 17: Buffer 2: Timer 3: MPU

Claims (2)

[Claims] 1. A channel interrupt control system for controlling an interrupt by monitoring a timer for each channel, wherein an operation state notification terminal (1) for each channel of a DMAC (11) is provided.
2) and a stop terminal (13) are provided, and the timer (2) is directly activated by the operation state notification signal from the operation state notification terminal (12) and is stopped when the activated timer (2) times out. A channel interrupt control system characterized in that a signal is directly input to the stop terminal (13) to stop the signal. 2. A stop signal when an interrupt signal IRQ generated by using the stop signal as one of the interrupt factors is notified to a DMA request source to generate an interrupt and a timeout occurs in the processing of this interrupt. 2. The channel interrupt control system according to claim 1, wherein the status is read from the buffer (17).