JPS61221849A - Bus control system - Google Patents

Bus control system

Info

Publication number
JPS61221849A
JPS61221849A JP60062409A JP6240985A JPS61221849A JP S61221849 A JPS61221849 A JP S61221849A JP 60062409 A JP60062409 A JP 60062409A JP 6240985 A JP6240985 A JP 6240985A JP S61221849 A JPS61221849 A JP S61221849A
Authority
JP
Japan
Prior art keywords
bus
timer
processor
signal
separation
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP60062409A
Other languages
Japanese (ja)
Inventor
Satoshi Tomono
Original Assignee
Nec Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Nec Corp filed Critical Nec Corp
Priority to JP60062409A priority Critical patent/JPS61221849A/en
Publication of JPS61221849A publication Critical patent/JPS61221849A/en
Pending legal-status Critical Current

Links

Abstract

PURPOSE: To detect easily a faulty processor by using a state monitor circuit, a bus monitor circuit containing a timer and a separation control circuit and a bus connection control circuit which performs separation from a common bus of a processor by means of the separation control signal.
CONSTITUTION: When a processor 1 is occupying a common bus 10, a timer start signal 12 is kept on and a timer 6 keeps its counting action. Then the timer 6 is set in a time-out state when the processor 1 occupies the bus 10 for a prescribed period of time or longer. The timer 6 turns on a timer-out signal 13 and gives information to a separation control circuit 7. The circuit 7 detects the ON state of the signal 13 and then turns on a separation control signal 11 to give an indication of separation to each processor 1. A bus connection control circuit 2 of the processor 1 occupying the bus 10 detects the ON state of the signal 11 and invalidates the connection with the bus 10 to release the bus 10.
COPYRIGHT: (C)1986,JPO&Japio
JP60062409A 1985-03-27 1985-03-27 Bus control system Pending JPS61221849A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP60062409A JPS61221849A (en) 1985-03-27 1985-03-27 Bus control system

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP60062409A JPS61221849A (en) 1985-03-27 1985-03-27 Bus control system

Publications (1)

Publication Number Publication Date
JPS61221849A true JPS61221849A (en) 1986-10-02

Family

ID=13199313

Family Applications (1)

Application Number Title Priority Date Filing Date
JP60062409A Pending JPS61221849A (en) 1985-03-27 1985-03-27 Bus control system

Country Status (1)

Country Link
JP (1) JPS61221849A (en)

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS642159A (en) * 1987-06-25 1989-01-06 Matsushita Electric Works Ltd Bus controller for multiprocessor
JPH01310449A (en) * 1988-06-08 1989-12-14 Nec Corp Fault processing system
JPH02224051A (en) * 1989-02-23 1990-09-06 Nec Corp Multi-processor system

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS642159A (en) * 1987-06-25 1989-01-06 Matsushita Electric Works Ltd Bus controller for multiprocessor
JPH01310449A (en) * 1988-06-08 1989-12-14 Nec Corp Fault processing system
JPH02224051A (en) * 1989-02-23 1990-09-06 Nec Corp Multi-processor system

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