JPS61221849A - Bus control system - Google Patents

Abstract

PURPOSE:To detect easily a faulty processor by using a state monitor circuit, a bus monitor circuit containing a timer and a separation control circuit and a bus connection control circuit which performs separation from a common bus of a processor by means of the separation control signal. CONSTITUTION:When a processor 1 is occupying a common bus 10, a timer start signal 12 is kept on and a timer 6 keeps its counting action. Then the timer 6 is set in a time-out state when the processor 1 occupies the bus 10 for a prescribed period of time or longer. The timer 6 turns on a timer-out signal 13 and gives information to a separation control circuit 7. The circuit 7 detects the ON state of the signal 13 and then turns on a separation control signal 11 to give an indication of separation to each processor 1. A bus connection control circuit 2 of the processor 1 occupying the bus 10 detects the ON state of the signal 11 and invalidates the connection with the bus 10 to release the bus 10.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a Kelbus control method for a multiprocessor system.

[Conventional technology]

Conventionally, in a system where two or more microprocessors are connected to a common bus as shown in Figure 2, if one processor fails, the other processors disconnect the failed processor from the common bus. However, if a failure occurs that occupies the common bus, other processors cannot acquire the common bus, so they cannot use the failed processor as a common bus. fC has the drawbacks of not only not being able to disconnect from the bus, not being able to take full advantage of the catechesis and multiprocessor functions, but also that it is difficult to detect a faulty processor.

[Problem that the invention seeks to solve]

Accordingly, an object of the present invention is to provide a bus control method that can make full use of multiprocessor functions and at the same time facilitate the detection of faulty processors. In a system where multiple microprocessors are connected to a common bus consisting of an address bus, a data bus, and a control signal, n is a bus monitoring circuit consisting of a status monitoring circuit, a timer, and a disconnection control circuit, and a common bus of the processors. A bus control type car is obtained, which includes a signal for controlling the disconnection and disconnection of the bus, and a bus connection control circuit that disconnects and disconnects from the common bus based on the signal.

〔Example〕

Next, embodiments of the present invention will be described with reference to the drawings.

Referring to FIG. 1, each processor 1 includes a bus connection control circuit 2t, and the bus monitoring circuit 4 includes a status monitoring circuit 5, a timer 6, and a disconnection control circuit 7t.

When processor 1 accesses memory 8 or %109, it issues a bus acquisition request to bus arbiter 3,
Once acquired, the bus connection control circuit 2 enables the connection to the common bus 10 and allows access to the memory 8 or IO9. When the access is completed, the bus connection control circuit 2 disables the connection to the common bus 10 and connects the common bus 1.
Release 0.

Each processor 1 performs all the processing by repeatedly executing the above operations.

In the path monitoring circuit 4, in the status monitoring circuit 5, the common bus 10
monitors the state of the common bus 10, and if the common bus 10 is occupied by one of the processors 1, turns on the timer start signal 12, starts the timer 6, and releases the common bus 10.
When all detections are made, the timer activation signal 12 is turned off and the timer 6 is reset.

When the processor 1 occupies the common bus 1 (l), the timer activation signal 12 is kept on and the n1 timer 6 continues counting. If occupied, timer 6 times out and turns on timer out signal 13;
The disconnection control circuit 7 is notified. When the disconnection control circuit 7 detects that the timeout signal 13 is turned on,
Disconnection control signal 11? Turn on and instruct each processor 1 to disconnect.

When the bus connection control circuit 2 of the processor 1 occupying the common bus 10f detects that the disconnection control signal 11 is on, it disables the connection with the common bus 10, and the common bus 101! - released and kept disconnected from the common bus 10;

When the common bus 10 is released, the disconnection control circuit 7
The disconnection control signal 11 is turned off. Other processor 1
can acquire the common bus 10t, and can continue processing while being disconnected from the common bus 10 of the faulty processor 1t.

〔effect〕

As explained above, the present invention has the effect of making full use of the multiprocessor function and at the same time facilitating the detection of a faulty processor.

[Brief explanation of the drawing]

FIG. 1 is a system block diagram of an embodiment of the present invention, and FIG. 2 is a block diagram showing a conventional system.

Claims (1)

[Claims] In a system in which a plurality of microprocessors are connected to a common bus consisting of an address bus, a data bus, and a control signal, a bus monitoring circuit having a status monitoring circuit, a timer, and a disconnection control circuit is disconnected from the common bus of the processors. A bus control system comprising: a bus connection control circuit that disconnects from the common bus according to a control signal.