JPH088889A - External synchronizer - Google Patents

Abstract

(57) [Abstract] [Purpose] The purpose is to accurately determine the state of the external clock in an external synchronizer and perform switching control to a stable clock. In the external synchronizer, the pulse width of the external clock q is counted by the counter unit 11 using the clock of the internal reference clock source 14, and based on this count value, the comparison data from the comparison set value information unit 13 The state of the external clock is determined by comparison, and the external clock is selectively switched based on the determination result.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an external synchronizing device having a frequency monitoring function.

[0002]

2. Description of the Related Art FIG. 3 is a block diagram showing a schematic configuration of a clock controller of an external synchronizer.

In FIG. 3, reference numeral 21 is a working clock source selected by an external synchronizer as a synchronization reference, 22 is a first spare clock source, and 23 is an nth clock source. This spare clock source is redundant. It becomes the externalized clock. Note that, in FIG. 3, there are three inputs of the working clock a and the spare clocks b and c, but the ratio of the number of working clocks for this input and the spare clocks is 1: n, and n is an arbitrary integer.

In FIG. 2, reference numeral 24 is a frequency monitoring unit for the working clock a, 25 is a frequency monitoring unit for the spare clock b, and 26 is a frequency monitoring unit for the spare clock c, which are detected by the respective frequency monitoring units 24 to 26. Frequency monitoring information, d, e,
f is output to the clock state monitoring control unit 27. The clock state monitoring control unit 27 monitors the state of each external clock input into the external synchronizer based on each frequency monitoring information d, e, f, and judges and instruct the selection of the external clock. The clock selection information g output from the monitor control unit 27 is input to the clock selection switching unit 28. The clock selection switching unit 28 performs selection switching operation of the external clock based on the clock selection information g, and outputs the selection reference clock h used in the external synchronizer.

FIG. 4 is a block diagram showing a schematic configuration of a conventional frequency monitoring unit. In FIG. 4, the frequency monitoring unit for the external clock includes a counter unit 31 that measures the number of pulses of the external clock within a certain fixed period, and a first memory unit 32 that holds the count data j in the current measurement period.
And a second memory unit 33 that holds the count data m in the measurement period before the count data j, the count data k held in the first memory unit 32, and the second memory unit 23. It is composed of a comparator unit 34 for comparing and calculating the count data 1 and an up / down counter unit 35 for detecting the count difference p between the count data k collected in two measurement periods and 1.

Next, the operation of the above conventional example will be described. In FIG. 3, the external clock a of the external clock source,
b and c are redundantly input to the external synchronizer. When the clock h that serves as the synchronization reference in the external synchronizer is selected from the redundant external clocks a, b and c,
The frequency monitoring information d, e, and h of each clock detected by the frequency monitoring units 24-26 is fetched into the clock state monitoring control unit 27, and according to the monitoring contents and the preset priority order, the abnormality of the active clock a is detected. Is detected, the clock selection switching unit 28 is controlled to select from the preliminary clocks b and c and output.

At this time, in the frequency monitoring units 24-26,
The counter unit 31 counts the number of pulses of the external clock i for a certain period, inputs the count data j in the current measurement period into the memory unit 32, and inputs the count data m in the previous measurement period into the memory 32. , The count data m of the previous measurement period is held in the memory unit 33, the count data k of the memory unit 32 and the count data 1 of the memory unit 33 are compared by the comparator unit 34, and the comparison result is the up-count number. The data of n or the down count number o is sent to the up / down counter section 35, and the count difference p between the collected count data k and l is detected.

As described above, in the above-mentioned conventional external synchronizer, the frequency monitoring section 24 to
When the count difference p detected by 26 exceeds a certain value, the clock state monitoring control unit 27 detects an abnormality in the clock frequency fluctuation, and controls the clock selection switching unit 28 by the clock selection information g according to the set priority. By doing so, one of the external clocks a, b, and c used as a reference in the external synchronizer is selected and supplied as the selected reference clock h.

[0009]

However, the above-mentioned conventional external synchronizer by frequency monitoring has the following problems.

That is, in a synchronizing device in which an external clock to be selected is made redundant and a priority is assigned to the external clocks a to c for clock switching control, the frequency of the external clock is unstable, Switching when the active system clock a is switched to the standby system clock b or c due to the disturbance of the clock due to the interface failure during the supply from the clock source to the synchronizer, or when the standby system is in an unstable state In that case, there is a problem that the clock state monitoring control unit 27 repeats the normal and abnormal monitoring states, and the clock switching operation frequently occurs. As a result, the PLO (Phase) is set in the synchronous system device that is slave-synchronized with the clock h supplied by the external synchronizer.
When a Lock Oscillator is provided, the frequency tracking range may be exceeded, and there is a risk of causing a synchronization system failure such as falling into a state of synchronization instability.

The present invention solves the above-mentioned problems of the prior art by accurately determining each external clock state,
An object of the present invention is to provide an external synchronizer capable of performing stable clock switching control.

Another object of the present invention is to provide an external synchronizer capable of protecting clock switching control against disturbance of the frequency of the external clock.

[0013]

In order to achieve the above object, the present invention provides a counting means for measuring a predetermined final pulse width of an external clock with an internal reference clock, and an external clock based on the count value of the counting means. Clock frequency monitoring means for determining whether the frequency is normal or abnormal and outputting alarm information for frequency monitoring according to the determination result, and priority of a clock to be used as a reference for synchronization from an external clock depending on the content of the alarm information for frequency monitoring The clock state monitoring control means outputs a command for selecting an external clock to be supplied according to the order, and the clock selection switching means for selectively switching the external clock according to the command.

In order to achieve another object, the present invention provides a frequency monitoring function of an external clock with hysteresis characteristics in the normal / abnormal operation range of the frequency monitoring alarm information.

[0015]

According to the present invention, the pulse width of a predetermined cycle of the external clock supplied to the external synchronizer as a synchronization reference is measured using the internal reference clock, and the clock frequency is monitored based on the count value. Therefore, the state of each external clock can be accurately determined, and switching can be controlled so that the clock is always stable.

Further, according to the present invention, in the frequency monitoring function of the external clock, by providing a hysteresis characteristic in the normal / abnormal operation range of the frequency monitoring alarm information, the clock can be switched with respect to the disturbance state of the external clock. This has the effect that the operation can have a protection function.

[0017]

Embodiments of the present invention will be described below with reference to the drawings.

FIG. 1 is a block diagram showing a schematic configuration of a clock frequency monitoring unit of an external synchronizer according to the present invention.

Referring to FIG. 1, the clock frequency monitor used in the external synchronizer uses the external input clock q by counting clock pulses from the internal reference clock source 14.
Counter section 11 for measuring the pulse width of a predetermined cycle of the counter, and the comparison setting value information section 1 of the count data s and the frequency state.
3 and a comparator unit 12 for generating the frequency monitoring information u by comparing the comparison data t output from the comparator 3.

Next, the operation when the frequency monitoring unit having the above configuration is applied to the frequency monitoring units 24 to 26 of FIG. 3 will be described.

Working clock a supplied to the external synchronizer
Alternatively, the spare clocks b and c are the respective frequency monitoring units 2
4 to 26, and the monitoring information is notified to the clock state monitoring control unit 27. Here, for example, when the frequency monitoring unit 24 detects that the clock frequency disturbance has occurred in the working clock a, the clock state monitoring control unit 27 which has received the monitoring information d receives the preliminary clock b and the preliminary clock c. The clock selection information g is generated based on the priority order of 1 and the monitoring information e and f, and is output to the clock selection switching unit 35. The clock selection switching unit 35 selects one of the spare clocks b and c according to the instruction of the clock selection information g and supplies it as the selection reference clock h.

Next, the alarm state of the clock frequency monitoring function will be described. The comparison setting value information section 13 of FIG.
The comparator data t of the count numbers N1, N2, N3, and N4 indicated by is set, and the monitoring information content shown below is defined by the range compared by the comparator unit 12.

That is, when the count data S of the counter unit 11 is N2 or more and N3 or less, normal monitoring information is output, and when the count data S is less than N1 or greater than N4, alarm level 2 monitoring information corresponding to an abnormality is output as N1. Above, and N2
In the smaller range and the range larger than N3 and smaller than N4, if the monitoring information in the previous monitoring period is normal, the alarm level is 1, and the range is larger than N4 or smaller than N1. If there is, the monitoring information of the alarm level 2 is maintained, and in other cases, the previous monitoring information is maintained.

Regarding the priority order according to the monitoring information U, in the normal state, the priority order is high, then in the case of the alarm level 1, the previous priority order is maintained, and the alarm level 2 has the lowest priority order. Further, if the monitoring information has the same content among the selectable clocks, the monitoring information is selected according to a preset priority order.

A case where the frequency monitoring units 24 to 26 of FIG. 3 are operated based on the monitoring information defined as above will be described.

The working clock a and the spare clock b or c are input to the external synchronizer, and the respective frequency monitoring units 2
In the state where the monitoring information d, e, and f detected in 4 to 26 are notified to the clock state monitoring control unit 27, the frequency monitoring unit 24 generates the monitoring information d as the frequency disturbance occurs in the working clock a. When the alarm level 2 is detected, the standby clock state monitoring control unit 27 determines to select one of the standby clocks b and c according to the priority and the monitoring information e and f, and sets the clock selection information g to the clock selection switching unit. To 28. Upon receiving this, the clock selection switching unit 28 changes the selected clock to the selection reference clock h
Supply as.

Therefore, the determination of clock switching is determined by whether the monitoring information d to f of the frequency monitoring units 24 to 26 is normal or the alarm level 2 (corresponding to an abnormal state).

In the range of the count value shown by (*) in FIG. 2, it is possible to give a dead band width to the error of the count value and the frequency disturbance to some extent. In addition, a PLO (Phase Lock Oscillator) is provided in a synchronous system device that is subordinately synchronized with a clock h supplied from an external synchronizer.
When r) is provided, the range of the alarm level 2 can be determined so as not to exceed the frequency tracking range.

[0029]

As is apparent from the above embodiment, the present invention can realize a stable frequency monitoring function by monitoring the frequency of the external clock by using the internal reference clock. Has the effect of being able to significantly reduce

Further, according to the present invention, the dead band width can be provided to the error of the count value and the disturbance of the frequency to some extent within the range of the alarm level, and accordingly, the normality and abnormality of the clock state monitoring information can be confirmed. In addition to solving the problem that the clock switching operation frequently occurs repeatedly,
A PLO (Phase Lock OSill) is provided in a synchronous system device that is subordinately synchronized with a clock supplied by an external synchronizer.
In the case where the alarm system is also provided, the failure of the synchronous system can be suppressed as much as possible by determining the alarm level range so that the frequency tracking range is not exceeded. Also, if the alarm content is notified as maintenance information,
It also has the effect of speeding up the decision on how to deal with fault maintenance.

[Brief description of drawings]

FIG. 1 is a block diagram showing a schematic configuration of a clock frequency monitoring unit of an external synchronizer according to an embodiment of the present invention.

FIG. 2 is an explanatory diagram showing the contents of frequency monitoring information in the present embodiment.

FIG. 3 is a block diagram showing a schematic configuration of a clock control unit of an external synchronizer.

FIG. 4 is a block diagram showing a schematic configuration of a clock frequency monitoring unit of a conventional external synchronizer.

[Explanation of symbols]

 11 counter section 12 comparator section 13 comparison set value information section 14 internal reference clock source 21 working clock source 22, 23 backup clock source 24-26 frequency monitoring section 27 clock state monitoring control section 28 clock selection switching section a working clock b, c Backup clock df Frequency monitoring information g Clock selection information

 ─────────────────────────────────────────────────── ─── Continuation of front page (72) Inventor Akira Sakai 4-3 Tsunashima Higashi, Kohoku-ku, Yokohama, Kanagawa Matsushita Communication Industrial Co., Ltd. 3-3-1 Matsushita Communication Industrial Co., Ltd.

Claims (2)

[Claims] 1. One of a plurality of external clocks for working and protection.
One is an external synchronizer which is supplied as a reference for synchronization, and counting means for measuring a predetermined last pulse width of the external clock by an internal reference clock, and a normal / normal external clock frequency based on the count value of the counting means. Clock frequency monitoring means for determining abnormality and outputting alarm information for frequency monitoring according to the determination result, and supply according to the priority of clocks to be used as a reference for synchronization from an external clock according to the content of the alarm information for frequency monitoring An external synchronizing device comprising a clock state monitoring control means for outputting a command for selecting an external clock to be generated, and a clock selection switching means for selectively switching the external clock according to the command. 2. The external synchronizer according to claim 1, wherein in the frequency monitoring of the external clock, a hysteresis characteristic is provided in an operating range when the frequency monitoring alarm is normal / abnormal.