CN110690894B - Clock failure safety protection method and circuit - Google Patents
Clock failure safety protection method and circuit Download PDFInfo
- Publication number
- CN110690894B CN110690894B CN201910890101.3A CN201910890101A CN110690894B CN 110690894 B CN110690894 B CN 110690894B CN 201910890101 A CN201910890101 A CN 201910890101A CN 110690894 B CN110690894 B CN 110690894B
- Authority
- CN
- China
- Prior art keywords
- clock
- clock source
- external
- detection module
- sources
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Active
Links
- 238000000034 method Methods 0.000 title claims abstract description 24
- 238000001514 detection method Methods 0.000 claims abstract description 124
- 230000002159 abnormal effect Effects 0.000 claims abstract description 30
- 230000005856 abnormality Effects 0.000 claims description 21
- 230000002452 interceptive effect Effects 0.000 claims description 4
- 230000008569 process Effects 0.000 description 8
- 238000007689 inspection Methods 0.000 description 6
- 238000010586 diagram Methods 0.000 description 4
- 230000005540 biological transmission Effects 0.000 description 3
- 230000008859 change Effects 0.000 description 2
- 230000000630 rising effect Effects 0.000 description 2
- 230000001360 synchronised effect Effects 0.000 description 2
- 238000013459 approach Methods 0.000 description 1
- 230000000903 blocking effect Effects 0.000 description 1
- 239000013078 crystal Substances 0.000 description 1
- 230000007547 defect Effects 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- 230000002431 foraging effect Effects 0.000 description 1
- 230000007246 mechanism Effects 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 238000012544 monitoring process Methods 0.000 description 1
- 238000012216 screening Methods 0.000 description 1
- 238000012795 verification Methods 0.000 description 1
Images
Classifications
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
- H03L7/00—Automatic control of frequency or phase; Synchronisation
- H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
- H03L7/08—Details of the phase-locked loop
- H03L7/0807—Details of the phase-locked loop concerning mainly a recovery circuit for the reference signal
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F1/00—Details not covered by groups G06F3/00 - G06F13/00 and G06F21/00
- G06F1/04—Generating or distributing clock signals or signals derived directly therefrom
- G06F1/08—Clock generators with changeable or programmable clock frequency
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
- H03L7/00—Automatic control of frequency or phase; Synchronisation
- H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
- H03L7/08—Details of the phase-locked loop
- H03L7/085—Details of the phase-locked loop concerning mainly the frequency- or phase-detection arrangement including the filtering or amplification of its output signal
-
- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
- Y02D—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN INFORMATION AND COMMUNICATION TECHNOLOGIES [ICT], I.E. INFORMATION AND COMMUNICATION TECHNOLOGIES AIMING AT THE REDUCTION OF THEIR OWN ENERGY USE
- Y02D10/00—Energy efficient computing, e.g. low power processors, power management or thermal management
Landscapes
- Engineering & Computer Science (AREA)
- Theoretical Computer Science (AREA)
- Physics & Mathematics (AREA)
- General Engineering & Computer Science (AREA)
- General Physics & Mathematics (AREA)
- Hardware Redundancy (AREA)
- Synchronisation In Digital Transmission Systems (AREA)
Abstract
A clock failure safety protection method and circuit. The invention is provided with a plurality of clock source detection modules, which are used for respectively checking each different clock source and calculating the deviation between the clock frequency of the clock source and the clock frequencies of other clock sources; and finally, switching the clock source to stabilize the output of the clock signal when the abnormal indication signal meets the clock source switching condition. Therefore, when the external clock source encounters external attack and is abnormal or invalid, the clock signal of the system can be recovered through other clock sources, and the risk of dead halt or safety information loss of the system is avoided.
Description
Technical Field
The invention relates to the field of chip security, in particular to a clock failure security protection method and a clock failure security protection circuit.
Background
Most complex SoC chips today have an internal clock source and an external clock source. Both clock sources may use a crystal oscillator or other signal output device to provide the clock signal. The internal clock source has short starting time, poor precision, slow starting time of the external clock source and high precision.
Because the external clock source has very good frequency stability and external interference resistance, most SoC chips use the external clock source as the clock source for the chip to stably run. However, in order to speed up the system start-up time, most SoC chips use an internal clock source as the clock source at the time of chip start-up. After the system is started, the running clock source is switched from the internal clock source to the external clock source in a hardware or software mode.
Because the system relies on the clock signal provided by the clock source as a reference, external clock sources are often the target of foreign attacks. When an external clock source is abnormal or hacked during the running process of the system, the external clock source fails, and when the external clock source fails, the system loses the clock source. At this point, if there is no efficient way to recover the system clock source, there is a risk of system crashes or loss of security information.
Disclosure of Invention
The invention aims at the defects of the prior art and provides a clock failure safety protection method and a circuit. The invention adopts the following technical scheme.
Firstly, to achieve the above object, a clock failure safety protection method is provided, which is used for a chip system connected with at least two clock sources, and the steps include: the clock sources respectively check the deviation between the clock frequency of the clock sources and the clock frequencies of other clock sources; generating an abnormal indication signal corresponding to the deviation when the deviation exceeds a preset range; and when the abnormality indication signal meets the clock source switching condition, switching the clock source and outputting a clock signal of the clock source after switching.
Optionally, the clock failure safety protection method, wherein the clock sources include at least 2 external clock sources.
Optionally, the clock failure safety protection method includes that the clock source includes an external clock source and an internal clock source.
Optionally, the clock failure safety protection method, wherein the step of checking the deviation between the clock frequencies includes: for each external clock source, checking the deviation between the clock frequency of the external clock source and the clock frequency of the other external clock source by taking the clock frequency of the external clock source as a reference; further comprises: and for the internal clock sources, taking the internal clock sources as a reference, and respectively checking deviation between clock frequencies of each external clock source.
Optionally, the clock failure safety protection method, wherein the deviation between the clock frequencies between the two clock sources is obtained by checking the following steps: the two clock sources respectively count according to the same rule in each period corresponding to the clock frequency of the clock sources by taking the clock frequency of the clock sources as a reference, and update the count value; when one of the count values reaches a configuration value, calculating a difference value between the count values obtained by updating the two clock sources respectively; the difference between the two count values is output as the deviation between the clock frequencies of the two clock sources.
Optionally, in the clock failure safety protection method, the clock source switching condition includes: an abnormality indication signal obtained by checking the deviation between the clock frequency of one external clock source and the clock frequencies of other external clock sources corresponds to an abnormality indication signal obtained by checking the deviation between the clock frequencies of the external clock sources by using the internal clock source as a reference.
The invention also provides a clock failure safety protection circuit, which comprises: the external clock source detection modules comprise at least 2 external clock source detection modules, wherein each external clock source detection module is correspondingly connected with one external clock source respectively, the external clock source detection modules are connected with each other respectively and detect the deviation between the clock frequency of the external clock source connected with each external clock source detection module and the clock frequency of the external clock source connected with other external clock source detection modules, and when the deviation exceeds a preset range, an abnormal indication signal corresponding to the deviation is generated; the internal clock source detection modules comprise at least 1 internal clock source detection module, wherein the internal clock source detection module is connected with one internal clock source and each external clock source detection module, and are used for respectively checking the deviation between clock frequencies of each external clock source detection module by taking the internal clock source connected with the internal clock source detection module as a reference, and generating an abnormal indication signal corresponding to the deviation when the deviation exceeds a preset range; and the clock source arbitration module is connected with the internal clock source detection module and is used for switching the clock source and outputting the clock signal of the clock source after switching when the abnormality indication signal meets the clock source switching condition.
Optionally, the clock failure safety protection circuit above, wherein each of the external clock source detection module or the internal clock source detection module includes: a counter for counting in each period of the clock source according to a set rule with reference to the clock frequency of the clock source to which the module itself is connected; the interactive interface is connected with the other external clock source detection module or the internal clock source detection module, outputs a trigger signal to the other external clock source detection module or the internal clock source detection module when the counter starts counting or ends counting, and triggers the other external clock source detection module or the internal clock source detection module to count; a configuration value comparison module for comparing a difference value between the count value of the other external clock source detection module or the internal clock source detection module and the configuration value when the count value of the counter reaches the configuration value, wherein the difference value is a deviation between clock frequencies of different clock sources; and the interrupt output module is used for generating an abnormal indication signal corresponding to the deviation when the difference value exceeds a preset range.
Optionally, in the clock fail safe circuit, the interrupt output module further triggers the counter or another external clock source detection module or another internal clock source detection module to restart counting.
Optionally, the clock failure safety protection circuit, wherein the clock source switching condition is: the abnormal indication signals corresponding to the external clock source detection modules or the internal clock source detection modules are corresponding and consistent.
Optionally, the clock failure safety protection circuit further includes a clock switching register, configured to switch an external clock source or switch an internal clock source according to the abnormality indication signal flag; and the clock source switching circuit is used for switching the signal output by the clock source arbitration module into a clock signal of a corresponding external clock source or internal clock source according to the clock switching register.
On the basis, the invention also provides a chip system, which comprises a chip, wherein the chip is connected with at least 2 clock sources, and the clock failure safety protection circuit is connected between the chip and the 2 clock sources, or the clock failure safety protection circuit is integrated inside the chip.
Advantageous effects
According to the invention, a plurality of clock source detection modules are used for respectively checking each different clock source, and calculating the deviation between the clock frequency of the clock source and the clock frequencies of other clock sources; and finally, switching the clock source to stabilize the output of the clock signal when the abnormal indication signal meets the clock source switching condition. Therefore, when the external clock source encounters external attack and is abnormal or invalid, the clock signal of the system can be recovered through other clock sources, and the risk of dead halt or safety information loss of the system is avoided.
In particular, the invention judges whether the clock sources are synchronous or not by comparing the count values by counting each other, and whether the deviation between the clock sources is within an acceptable range or not. The judging mode has the advantages that the interface signal is relatively simple, a clock signal or a counting value of a plurality of bits is not required to be transmitted to another detecting module, the operation cost of the judging mode for clock abnormality is low, the dyssynchrony among clocks can be timely obtained, and the abnormal clock source is directly determined through calculation so as to be convenient for switching. Moreover, the judging mode has higher flexibility. The interface signal is not affected in the case of a need to change the counter bit width or in the case of a need to change the counting mode.
The invention can further introduce an internal clock source to further judge on the basis of mutual inspection of the external clock sources. Therefore, when two external clock sources are damaged or are illegally stopped by a hacker, the system for performing the constant failure protection can still detect the clock abnormality according to the internal clock source, and the risk of stopping the system is solved.
Additional features and advantages of the invention will be set forth in the description which follows, and in part will be obvious from the description, or may be learned by practice of the invention.
Drawings
The accompanying drawings are included to provide a further understanding of the invention and are incorporated in and constitute a part of this specification, illustrate the invention and together with the embodiments of the invention, and do not limit the invention. In the drawings:
FIG. 1 is a schematic diagram of a clock fail safe circuit of the present invention;
FIG. 2 is a schematic diagram of the connection relationship between the clock fail safe circuit and the system-on-chip of the present invention;
FIG. 3 is a schematic diagram of an external clock source detection module or an internal clock source detection module according to the present invention;
FIG. 4 is a signal timing diagram of each clock source in the present invention.
Detailed Description
In order to make the purpose and technical solutions of the embodiments of the present invention more clear, the technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings of the embodiments of the present invention. It will be apparent that the described embodiments are some, but not all, embodiments of the invention. All other embodiments, which can be made by a person skilled in the art without creative efforts, based on the described embodiments of the present invention fall within the protection scope of the present invention.
It will be understood by those skilled in the art that, unless otherwise defined, all terms (including technical and scientific terms) used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this invention belongs. It will be further understood that terms, such as those defined in commonly used dictionaries, should be interpreted as having a meaning that is consistent with their meaning in the context of the prior art and will not be interpreted in an idealized or overly formal sense unless expressly so defined herein.
Fig. 1 is a clock fail safe circuit according to the present invention for detecting 2 external clock sources and 1 internal clock source, alarming when any clock source is abnormal, and automatically switching to the normal clock source when the external clock source is abnormal, affects normal operation, or is lost. The implementation of the technology can effectively improve the safety and reliability of the system.
The circuit comprises:
the external clock source detection modules comprise at least 2 external clock source detection modules, wherein each external clock source detection module is correspondingly connected with one external clock source respectively, the external clock source detection modules are connected with each other respectively and detect the deviation between the clock frequency of the external clock source connected with each external clock source detection module and the clock frequency of the external clock source connected with other external clock source detection modules, and when the deviation exceeds a preset range, an abnormal indication signal corresponding to the deviation is generated;
the internal clock source detection modules comprise at least 1 internal clock source detection module, wherein the internal clock source detection module is connected with one internal clock source and each external clock source detection module, and are used for respectively checking the deviation between clock frequencies of each external clock source detection module by taking the internal clock source connected with the internal clock source detection module as a reference, and generating an abnormal indication signal corresponding to the deviation when the deviation exceeds a preset range;
and the clock source arbitration module is connected with the internal clock source detection module and is used for switching the clock source and outputting the clock signal of the clock source after switching when the abnormality indication signal meets the clock source switching condition.
The external clock source detection module and the internal clock source detection module respectively detect deviations between clock frequencies in the following manners: firstly, respectively counting by the two clock sources in each period corresponding to the self clock frequency according to the same rule by taking the self clock frequency as a reference, and updating the count value; then, when one of the count values reaches a configuration value, calculating a difference value between the two clock sources respectively updating the obtained count values, and then restarting counting; and finally, outputting a difference value between the two count values as a deviation between the clock frequencies of the different clock sources.
The above-described deviation between clock frequencies can be achieved in particular by the circuit shown in fig. 3. The circuit can be applied to any external clock source detection module or the internal clock source detection module, and comprises:
a counter for counting in each period of the clock source according to a set rule with reference to the clock frequency of the clock source to which the module itself is connected;
the interactive interface is connected with the other external clock source detection module or the internal clock source detection module, outputs a trigger signal to the other external clock source detection module or the internal clock source detection module when the counter starts counting or ends counting, and triggers the other external clock source detection module or the internal clock source detection module to count;
a configuration value comparison module for comparing a difference value between the count value of the other external clock source detection module or the internal clock source detection module and the configuration value when the count value of the counter reaches the configuration value, wherein the difference value is a deviation between clock frequencies of different clock sources;
and the interrupt output module is used for generating an abnormal indication signal corresponding to the deviation when the difference value exceeds a preset range.
In a preferred manner, the circuit of fig. 3 may be further connected to:
the clock switching register is used for marking the need of switching the external clock source or the internal clock source when the abnormal indication signals corresponding to the external clock source detection modules or the internal clock source detection modules are corresponding to each other according to the abnormal indication signal mark;
and the clock source switching circuit is used for switching the signal output by the clock source arbitration module into the clock signal of the corresponding external clock source or internal clock source according to the mark stored by the clock switching register.
And the interrupt output module triggers the counter or another external clock source detection module or another internal clock source detection module connected with the module to restart counting while generating a corresponding abnormal indication signal.
The above-described clock source detection process is described taking the clock source 2 detecting the clock source 1 as an example. All decision criteria in this process are provided by the registers of the pre-configured left side of fig. 3. Deviation detection process between clock frequencies:
1. after receiving the software enable signal "clock detection enable", the clock source detection module 2 generates a start count indication signal, and starts the internal counter.
2. The clock source detection module 1 takes a rising edge from the start count indication signal, starts the internal counter of the clock source detection module 1, and generates a count reaching a preset value to indicate to the clock source detection module 2 when the count value reaches a configuration value, and simultaneously restarts the internal counter of the clock source detection module 2.
3. The clock source detection module 2 receives the indication that the count reaches the preset value and then takes the rising edge
4. The value of the internal counter is compared with the counter indication default value to judge the speed of the clock source 1 and the clock source 2, and corresponding interrupt and opposite clock loss indication signals are generated.
5. The internal counter is restarted.
The unstable threshold is used to set the error of the clock source 1 and the clock source 2 to be more or less abnormal. The comparison stable frequency configuration value is used for setting how many times of reporting abnormality appear continuously in the abnormality of the clock source 1 and the clock source 2, and the two values can be set according to the requirements of functional safety and flexibility.
The external clock source 1 detects the external clock source 2, and the internal clock source detects the external clock source 1 and the external clock source 2 in the same manner as described above.
In another manner, referring to fig. 2, in the above circuit, an output terminal of the clock source arbitration module is connected to a Phase Locked Loop (PLL) of the chip system to provide a stable clock signal to the chip system. The clock signal is obtained by respectively checking the deviation between the clock frequency of the clock source and the clock frequencies of other clock sources by at least two clock sources, generating an abnormal indication signal corresponding to the deviation when the deviation exceeds a preset range, screening the corresponding clock sources when the abnormal indication signal meets the clock source switching condition, and switching the clock sources.
Taking two external clock sources and 1 internal clock source for arbitration and switching as an example, in the implementation manner of fig. 2, through the external clock source detection module 1, the external clock source detection module 2 and the internal clock source detection module 3, arbitration and switching of clock sources under any abnormal condition between the two external clock sources and one internal clock source are realized by matching with corresponding clock source arbitration modules.
The external clock source detection module 1 uses the external clock source External Clock Source 1 as a reference to check the external clock source External Clock Source. The external clock source detection module 2 checks the external clock source External Clock Source 1 with the external clock source External Clock Source 2 as a reference. The checking flow comprises the following steps:
step S101: the clock source inspection, wherein the two external clock source detection modules count each other, compare the count values, if the deviation of the count values is within the preset range preset by software, the inspection is finished, and the next inspection is started after a period of time; if the count value deviation is outside the preset range, the step S102 is entered;
step S102: an abnormality indication signal is generated, the abnormality indication signal is reported to a CPU of the chip system in an interrupt mode, and a clock source detection result is output and sent to the internal clock source detection module 3.
The internal clock source detection module 3 uses the internal clock source INTERNAL CLOCK SOURCE Hz as a reference to simultaneously check the external clock source External Clock Source and the external clock source External Clock Source. The checking step flow comprises the following steps:
step S201: the external Clock Source 1 and the external Clock Source 2 are checked, counted each other, and the count values are compared by using the Internal Clock Source international_clock_source as a reference. If the deviation of the count value is within a preset range preset by software, ending the check, and starting the next check after a period of time interval; if the count value deviation is outside the preset range, the step S202 is entered;
step S202: generating an abnormality indication signal, and judging whether an abnormality state corresponding to the abnormality indication signal is consistent with detection results sent by the external clock source detection module 1 and the external clock source detection module 2;
step S203: according to the judgment result of step S202, a clock source switching instruction signal is generated. For example, when the external clock source External Clock Source 1 is lost, the external clock source External Clock Source 1 is lost as a result of detection by the external clock source detection module 2, and the external clock source External Clock Source 1 is also lost as a result of detection by the internal clock source detection module 3, a switching instruction signal for the external clock source External Clock Source 1 is generated at this time.
Therefore, the clock source arbitration module arbitrates the clock source of the chip according to the clock source switching indication signal output by the internal clock source detection module 3, and checks and obtains the clock source currently used by the chip. The checking flow comprises the following steps:
step S301: clock Source checking to check whether the current Clock Source is external Clock Source External Clock Source 1, external Clock Source External Clock Source 2, or Internal Clock Source international Clock Source. Judging whether the clock source clock switching indication signal selected currently corresponds to a state needing to be switched;
step S302: and when the switching indication signal indicates that switching is needed, driving corresponding hardware to perform clock switching.
The above-described process corresponds to fig. 4. The system-on-chip provides a Clock signal using an external Clock Source External Clock Source 1, external Clock Source External Clock Source and Internal Clock Source internal_clock_source, which are frequency consistent or multiple or have a fixed frequency difference or period difference. In the process of starting the chip, the International_clock_Source is selected as the chip Clock Source at first, and when the chip is started stably, the system can select External Clock Source 1 as the chip Clock Source.
When External Clock Source 1 is lost, the external clock source detection circuit 2 and the internal clock source detection circuit 3 both detect External Clock Source that 1 is lost, the clock source arbitration module judges that the current clock source is External Clock Source 1, and simultaneously receives a External Clock Source 1 switching instruction signal output by the internal clock source detection module 3 to perform arbitration, so that the chip clock source is switched from External Clock Source 1 to External Clock Source. In the switching process, selected Functional Clock Source is always used as a clock signal output port to provide clocks for units such as a phase-locked loop of a chip for aging control.
It should be noted that the present invention can also implement similar clock failure protection only according to two external clock sources by checking and detecting the clock sources. Similarly, an external clock source can be detected by an internal clock source, and when the external clock source is attacked and abnormal, the external clock source is switched to a stable internal clock source by the synchronous detection process between the clock sources, so as to avoid the failure or the blocking of the system due to the abnormal clock source.
The protection against clock failures can be achieved by just checking the external clock sources against each other, but its reliability is not as high as in the previous embodiment using both internal and external clock sources. This is because, in the above-described schemes of the internal and external clock sources, the internal clock source and the external clock source are double-secured by the interactive detection, and the inspection result of the external clock source is identical to the result of the internal clock source, so that the automatic switching operation is performed.
If only the external clock sources are included for mutual inspection, when both external clock sources are bad or illegally stopped by a hacker, both clock signals cannot be detected due to the failure of both external clock sources, and the detection mechanism between the two clock sources still cannot detect the abnormality due to the failure of the reference standard used for detection, so that the risk of stopping the system can not be solved.
Meanwhile, it should be understood by those skilled in the art that the detection manner of the deviation between clock frequencies of the clock sources in the above embodiment is only a preferable manner selected in consideration of the flexibility of clock verification and the complexity of interface implementation. In general, the above-mentioned detection of the deviation between clock frequencies can also be achieved by means of phase locking techniques, time synchronization, frequency synchronization, phase monitoring or by means of additional time alignment signals. However, the comparison between clocks is achieved by the indication signal of the mutual count, the transmission count to the set value (register configuration value) in the above embodiment, which still has the following advantages over other approaches:
1. the interface signal is simple, the clock signal or the count value of a plurality of bits is not required to be transmitted to another detection module (generally, as the chip scale is larger and larger, the clock detection module can be far away, the clock transmission or the transmission of a multi-bit counter can be complex, and the physical realization is relatively difficult)
2. The flexibility is higher, and if the bit width of the counter needs to be changed, or the counting mode is changed, the interface signal is not affected.
The foregoing is a description of embodiments of the invention, which are specific and detailed, but are not to be construed as limiting the scope of the invention. It should be noted that it will be apparent to those skilled in the art that several variations and modifications can be made without departing from the spirit of the invention, which are all within the scope of the invention.
Claims (9)
1. A method for clock fail safe protection for a system on a chip having at least two clock sources connected thereto, comprising the steps of:
the clock sources respectively check the deviation between the clock frequency of the clock source and the clock frequencies of other clock sources, and the clock sources comprise at least 2 external clock sources and internal clock sources;
generating an abnormal indication signal corresponding to the deviation when the deviation exceeds a preset range;
when the abnormality indication signal meets the clock source switching condition, switching the clock source and outputting a clock signal of the clock source after switching;
wherein the clock source switching conditions include: an abnormality indication signal obtained by checking the deviation between the clock frequency of one external clock source and the clock frequencies of other external clock sources corresponds to an abnormality indication signal obtained by checking the deviation between the clock frequencies of the external clock sources by using the internal clock source as a reference.
2. The clock fail-safe method of claim 1, wherein the step of checking for deviations between the clock frequencies comprises: for each external clock source, checking the deviation between the clock frequency of the external clock source and the clock frequency of the other external clock source by taking the clock frequency of the external clock source as a reference;
further comprises:
and for the internal clock sources, taking the internal clock sources as a reference, and respectively checking deviation between clock frequencies of each external clock source.
3. The method of claim 2, wherein the deviation between the clock frequencies between two clock sources is obtained by checking in particular: the two clock sources respectively count according to the same rule in each period corresponding to the clock frequency of the clock sources by taking the clock frequency of the clock sources as a reference, and update the count value;
when one of the count values reaches a configuration value, calculating a difference value between the count values obtained by updating the two clock sources respectively;
the difference between the two count values is output as the deviation between the clock frequencies of the two clock sources.
4. A clock fail-safe protection circuit for use in the clock fail-safe protection method of any one of claims 1 to 3, comprising:
the external clock source detection modules comprise at least 2 external clock source detection modules, wherein each external clock source detection module is correspondingly connected with one external clock source respectively, the external clock source detection modules are connected with each other respectively and detect the deviation between the clock frequency of the external clock source connected with each external clock source detection module and the clock frequency of the external clock source connected with other external clock source detection modules, and when the deviation exceeds a preset range, an abnormal indication signal corresponding to the deviation is generated;
the internal clock source detection modules comprise at least 1 internal clock source detection module, wherein the internal clock source detection module is connected with one internal clock source and each external clock source detection module, and are used for respectively checking the deviation between clock frequencies of each external clock source detection module by taking the internal clock source connected with the internal clock source detection module as a reference, and generating an abnormal indication signal corresponding to the deviation when the deviation exceeds a preset range;
and the clock source arbitration module is connected with the internal clock source detection module and is used for switching the clock source and outputting the clock signal of the clock source after switching when the abnormality indication signal meets the clock source switching condition.
5. The clock fail safe circuit of claim 4, wherein each of the external clock source detection modules or the internal clock source detection modules comprises: a counter for counting in each period of the clock source according to a set rule with reference to the clock frequency of the clock source to which the module itself is connected;
the interactive interface is connected with the other external clock source detection module or the internal clock source detection module, outputs a trigger signal to the other external clock source detection module or the internal clock source detection module when the counter starts counting or ends counting, and triggers the other external clock source detection module or the internal clock source detection module to count;
a configuration value comparison module for comparing a difference value between the count value of the other external clock source detection module or the internal clock source detection module and the configuration value when the count value of the counter reaches the configuration value, wherein the difference value is a deviation between clock frequencies of different clock sources;
and the interrupt output module is used for generating an abnormal indication signal corresponding to the deviation when the difference value exceeds a preset range.
6. The clock fail safe circuit of claim 5, wherein the interrupt output module further triggers the counter or another external clock source detection module or another internal clock source detection module to restart counting.
7. The clock fail safe circuit of claim 5, wherein the clock source switching condition is: the abnormal indication signals corresponding to the external clock source detection modules or the internal clock source detection modules are corresponding and consistent.
8. The clock fail safe circuit of claim 5, further comprising a clock switching register for switching an external clock source or an internal clock source according to the abnormality indication signal flag;
and the clock source switching circuit is used for switching the signal output by the clock source arbitration module into a clock signal of a corresponding external clock source or internal clock source according to the clock switching register.
9. A chip system comprising a chip, wherein at least 2 clock sources are connected to the chip, and the clock fail-safe circuit according to claim 4 is connected between the chip and 2 clock sources, or the clock fail-safe circuit according to claim 4 is integrated inside the chip.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201910890101.3A CN110690894B (en) | 2019-09-20 | 2019-09-20 | Clock failure safety protection method and circuit |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201910890101.3A CN110690894B (en) | 2019-09-20 | 2019-09-20 | Clock failure safety protection method and circuit |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN110690894A CN110690894A (en) | 2020-01-14 |
| CN110690894B true CN110690894B (en) | 2023-05-12 |
Family
ID=69109753
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201910890101.3A Active CN110690894B (en) | 2019-09-20 | 2019-09-20 | Clock failure safety protection method and circuit |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN110690894B (en) |
Families Citing this family (8)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN111611768B (en) * | 2020-05-21 | 2023-04-25 | 北京百度网讯科技有限公司 | Method and device for monitoring clock signals |
| CN111726190B (en) * | 2020-06-18 | 2022-10-04 | 四川艾贝斯科技发展有限公司 | System time calibration method for street lamp control system |
| CN112114616B (en) * | 2020-08-04 | 2022-10-25 | 深圳市宏电技术股份有限公司 | Switching method of real-time clock, electronic equipment and computer storage medium |
| CN112083755A (en) * | 2020-08-10 | 2020-12-15 | 合肥市芯海电子科技有限公司 | Clock control circuit, chip and clock control method |
| CN112181047B (en) * | 2020-09-03 | 2023-08-11 | 华帝股份有限公司 | Self-adaptive method based on power frequency clock source of power grid |
| CN114637370B (en) * | 2022-03-25 | 2024-02-20 | 北京中科飞鸿科技股份有限公司 | Internal and external different frequency reference clock signal switching circuit, device and method |
| CN115328267A (en) * | 2022-07-15 | 2022-11-11 | 无锡芯领域微电子有限公司 | Dynamic clock adjusting method and device based on-chip clock comparison |
| CN116722868B (en) * | 2023-08-08 | 2023-11-03 | 苏州浪潮智能科技有限公司 | Clock holding system, method and storage device |
Citations (9)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5146585A (en) * | 1988-10-25 | 1992-09-08 | International Business Machines Corporation | Synchronized fault tolerant clocks for multiprocessor systems |
| JPH088889A (en) * | 1994-06-22 | 1996-01-12 | Matsushita Electric Ind Co Ltd | External synchronization device |
| JPH1155234A (en) * | 1997-07-30 | 1999-02-26 | Fujitsu Ltd | Clock frequency precision monitor circuit |
| JP2000286702A (en) * | 1999-03-31 | 2000-10-13 | Mitsubishi Electric Corp | Synchronous clock generation circuit and clock switch device using the same |
| JP2001345789A (en) * | 2000-06-05 | 2001-12-14 | Nec Eng Ltd | Frequency monitoring circuit for network synchronizer |
| KR20030026741A (en) * | 2001-09-28 | 2003-04-03 | 엘지전자 주식회사 | Clock source auto change apparatus by data transmission rate |
| CN1578197A (en) * | 2003-07-28 | 2005-02-09 | 华为技术有限公司 | Clock source frequency shift detecting method |
| CN101860365A (en) * | 2010-06-12 | 2010-10-13 | 中兴通讯股份有限公司 | Reference clock source switching method and device |
| CN205750769U (en) * | 2016-05-30 | 2016-11-30 | 珠海市一微半导体有限公司 | Clock monitoring circuit |
Family Cites Families (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US9595972B2 (en) * | 2015-04-08 | 2017-03-14 | Microsemi Semiconductor Ulc | Digital phase locked loop arrangement with master clock redundancy |
-
2019
- 2019-09-20 CN CN201910890101.3A patent/CN110690894B/en active Active
Patent Citations (9)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5146585A (en) * | 1988-10-25 | 1992-09-08 | International Business Machines Corporation | Synchronized fault tolerant clocks for multiprocessor systems |
| JPH088889A (en) * | 1994-06-22 | 1996-01-12 | Matsushita Electric Ind Co Ltd | External synchronization device |
| JPH1155234A (en) * | 1997-07-30 | 1999-02-26 | Fujitsu Ltd | Clock frequency precision monitor circuit |
| JP2000286702A (en) * | 1999-03-31 | 2000-10-13 | Mitsubishi Electric Corp | Synchronous clock generation circuit and clock switch device using the same |
| JP2001345789A (en) * | 2000-06-05 | 2001-12-14 | Nec Eng Ltd | Frequency monitoring circuit for network synchronizer |
| KR20030026741A (en) * | 2001-09-28 | 2003-04-03 | 엘지전자 주식회사 | Clock source auto change apparatus by data transmission rate |
| CN1578197A (en) * | 2003-07-28 | 2005-02-09 | 华为技术有限公司 | Clock source frequency shift detecting method |
| CN101860365A (en) * | 2010-06-12 | 2010-10-13 | 中兴通讯股份有限公司 | Reference clock source switching method and device |
| CN205750769U (en) * | 2016-05-30 | 2016-11-30 | 珠海市一微半导体有限公司 | Clock monitoring circuit |
Non-Patent Citations (2)
| Title |
|---|
| On-Chip Glitch-Free Backup Clock Changer with Noise Canceller and Edge Detector for Safety MCU Clock System;Joonghyun An;《2015 IEEE 4th Global Conference on Consumer Electronics (GCCE)》;20151231;487-488 * |
| 一种新颖的内外频标自适应式时钟源的设计;侯武斌;《现代电子技术》;20091231;175-177 * |
Also Published As
| Publication number | Publication date |
|---|---|
| CN110690894A (en) | 2020-01-14 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| CN110690894B (en) | Clock failure safety protection method and circuit | |
| US7107484B2 (en) | Fault-tolerant computer system, re-synchronization method thereof and re-synchronization program thereof | |
| US7154305B2 (en) | Periodic electrical signal frequency monitoring systems and methods | |
| KR102355424B1 (en) | Apparatus and method for enhancing reliability of watchdog timer controlling central processing unit for use in vehicle | |
| JPH07177130A (en) | Error count circuit | |
| US6141757A (en) | Secure computer with bus monitoring system and methods | |
| US10649487B2 (en) | Fail-safe clock monitor with fault injection | |
| CN101796489A (en) | Clock supervision unit | |
| CN112083755A (en) | Clock control circuit, chip and clock control method | |
| US7089462B2 (en) | Early clock fault detection method and circuit for detecting clock faults in a multiprocessing system | |
| US7872505B2 (en) | Semiconductor apparatus and anomaly detection method of the same | |
| CA2435001C (en) | Fault-tolerant computer system, re-synchronization method thereof and re-synchronization program thereof | |
| CN100461065C (en) | Frequency regulation method and device for clock/data restoring circuit | |
| US20020114409A1 (en) | Serial data communication apparatus and detection method for communication error | |
| CN111447333B (en) | TDM bus fault detection method, device, equipment and readable storage medium | |
| JPH0784667A (en) | Method and device for monitoring abnormality of clock driver | |
| US11764771B2 (en) | Event detection control device and method for circuit system controlled by pulse wave modulation signal | |
| JP3652232B2 (en) | Microcomputer error detection method, error detection circuit, and microcomputer system | |
| US11579995B2 (en) | Electronic element, system comprising such an electronic element and method for monitoring and cutting off a processor on occurrence of a failure event | |
| US20240160176A1 (en) | Safety power management | |
| JPS5855535B2 (en) | Multi-computer device for vehicles | |
| JP5664540B2 (en) | Monitoring circuit, microcomputer and communication system | |
| CN115877917A (en) | Signal processing system | |
| CN117195234A (en) | Safety starting device, method and system | |
| JPH0573360A (en) | Watchdog timer |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| PB01 | Publication | ||
| PB01 | Publication | ||
| SE01 | Entry into force of request for substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| GR01 | Patent grant | ||
| GR01 | Patent grant |