CN112083755A - Clock control circuit, chip and clock control method - Google Patents
Clock control circuit, chip and clock control method Download PDFInfo
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Abstract
The invention discloses a chip with a clock control circuit and a clock control method, wherein the clock control circuit is applied to the chip, a first clock source is arranged in the chip, and the clock control circuit comprises a failure detection circuit and a clock gating circuit; the failure detection circuit is respectively connected with a first clock source and a preset second clock source and is used for detecting whether a main clock source of the chip fails or not, wherein the main clock source of the chip is the first clock source or the second clock source; the clock gating circuit is respectively connected with the failure detection circuit, the first clock source and the second clock source, and the clock gating circuit is used for switching the main clock source of the chip when the main clock source of the chip fails according to the output signal of the failure detection circuit. The chip provided by the invention needs to select different clock sources as chip clocks, and the clock sources can be switched in time through the clock control circuit, thereby providing enough safety guarantee measures for a chip system.
Description
Technical Field
The invention belongs to the technical field of chips, and particularly relates to a chip with a clock control circuit and a clock control method using the chip.
Background
The system clock is a source power and metronome for driving the whole chip system to work in order, and is the heart of the whole chip system. Once the system clock fails and stops working, the whole chip system is directly hung up.
Chip development has been used in industry to a great extent, and more chips are applied to scenes relating to life and property safety of users, so that how to ensure chip safety and ensure that the chip has the capability of coping with system clock faults is a problem to be considered by chip technical designers.
In many SOC chips, one or more fixed-frequency clock sources are usually provided inside the chip to ensure that the system can start up normally. In the use of a specific scene, because the internal clock does not meet the requirements of clock frequency or clock precision, a high-frequency or high-precision clock is still required to be directly or indirectly used as a chip system clock source through the external irrigation of chip pins. The external clock is typically provided on the system board using an external crystal or oscillator. Compared with an internal clock source, the external board-level clock source is more likely to have a fault of clock stop or clock discontinuity due to various reasons, and when the system clock adopts the external clock directly or indirectly as the clock source and the external clock has a fault, if special treatment is not performed, the whole chip system can be directly hung up.
Disclosure of Invention
In order to solve the above problems, an object of the present invention is to provide a clock control circuit, a chip and a clock control method, which can switch clock sources in time, provide sufficient security measures for a chip system, and ensure that the chip system is not directly hung up due to an external clock failure.
Another objective of the present invention is to provide a clock control circuit, a chip and a clock control method, which can freely select an external clock source or an internal clock source as a clock according to requirements, so as to ensure the clock supply of the chip, and monitor the working condition of the external clock source in real time when the external clock source is used as the chip clock, thereby improving the security level of the chip system and effectively ensuring the clock security of the chip.
In order to achieve the purpose, the technical scheme of the invention is as follows:
a clock control circuit is applied to a chip, a first clock source is arranged in the chip, and the clock control circuit comprises a failure detection circuit and a clock gating circuit;
the failure detection circuit is respectively connected with the first clock source and a preset second clock source, and is used for detecting whether a main clock source of the chip fails, wherein the main clock source of the chip is the first clock source or the second clock source;
the clock gating circuit is respectively connected with the failure detection circuit, the first clock source and the second clock source, and the clock gating circuit is used for switching the main clock source of the chip when the main clock source of the chip fails according to the output signal of the failure detection circuit.
The clock control circuit provided by the invention takes an internal clock source as a first clock source, takes other clock sources as a second clock source, and simultaneously accesses the first clock source and the second clock source into the failure detection circuit, the failure detection circuit carries out fault detection on the clock source, different clock sources are gated for a chip through the clock gating switch, and the chip clock is switched between the first clock source and the second clock source.
The second clock source may be off-chip or on-chip.
Further, the clock gating circuit is configured to:
when the currently gated main clock source of the chip is the first clock source and the first clock source fails, switching the main clock source of the chip to the second clock source;
and when the currently gated main clock source of the chip is the second clock source and the second clock source fails, switching the main clock source of the chip to the first clock source.
Further, the failure detection circuit includes:
the detection module is used for detecting the clock frequency of a currently gated master clock source and generating a reset pulse, wherein the currently gated master clock source is the first clock source or the second clock source;
the failure comparison module is used for comparing a time interval from the moment generated by the latest reset pulse to the current moment with a preset time threshold and outputting a clock switching signal when the comparison result meets a preset condition;
the clock gating circuit is used for switching the main clock source of the chip according to the clock switching signal.
The failure detection circuit adopts the methods of detecting the frequency of an access clock, generating reset pulses, periodically resetting the counting module and comparing the counting result with the upper limit value of failure time, so that technicians can conveniently and flexibly adjust the corresponding threshold setting according to different application scenes, the adaptability of the chip is improved, the existing structure of the chip is fully utilized, the area and the design complexity of the chip are greatly saved, and the performance of the chip is improved.
Still further, the detection module includes:
the frequency detection circuit is used for detecting the clock frequency of the currently gated main clock source according to a preset detection time interval;
the reset pulse generating circuit is used for generating a corresponding reset pulse according to the clock frequency;
a timer for starting timing from zero after receiving the reset pulse;
the failure comparison module is used for comparing the timing duration of the timing module with the preset time threshold and outputting the clock switching signal when the timing duration is greater than the preset time threshold.
Still further, the chip further comprises:
the failure time register is connected with the failure comparison module and used for storing the preset time threshold;
and the detection time register is connected with the frequency detection circuit and used for storing the detection time interval.
A chip is provided with a first clock source and the clock control circuit.
A clock control method is applied to a chip, a first clock source is arranged in the chip, and the method comprises the following steps:
detecting whether a main clock source of the chip is invalid or not, and generating a detection signal, wherein the main clock source of the chip is the first clock source or a preset second clock source;
and switching the main clock source of the chip when the main clock source of the chip fails according to the detection signal.
Further, in the method, the detecting whether the first clock source and a preset second clock source are failed includes:
detecting whether a main clock source currently gated by the chip is invalid, wherein the main clock source is the first clock source or the second clock source;
the switching of the master clock source of the chip includes:
when the master clock source currently gated by the chip is the first clock source and the first clock source fails, switching the master clock source currently gated by the chip to the second clock source;
and when the current master clock source gated by the chip is the second clock source and the second clock source fails, switching the current master clock source gated by the chip to the first clock source.
Further, the detecting whether the master clock source currently gated by the chip fails includes:
detecting the clock frequency of a currently gated main clock source and generating a reset pulse;
and comparing the time interval from the moment of the generation of the last reset pulse to the current moment with a preset time threshold, and determining that the currently gated master clock source is invalid when the comparison result meets the preset condition.
Further, the detecting a clock frequency of a currently gated master clock source and generating a reset pulse includes:
detecting the clock frequency of the currently gated master clock source according to a preset detection time interval;
generating a corresponding reset pulse according to the clock frequency;
comparing the time interval from the moment of the last reset pulse to the current moment with a preset time threshold, and determining that the currently gated master clock source is invalid when the comparison result meets a preset condition, the method includes:
and timing from zero according to the reset pulse, and determining that the currently gated master clock source is invalid when the timing duration is greater than the preset time threshold.
Therefore, compared with the prior art, the clock control circuit and the chip provided by the invention can select different clock sources as the main clock of the chip according to requirements, monitor the state of the main clock in time through the clock control circuit, switch the clock sources in time when the main clock fails, provide enough safety guarantee measures for a chip system, effectively guarantee the clock safety of the chip, ensure that the chip system is not directly hung up due to external clock failure, and improve the safety of the chip system.
Drawings
Fig. 1 is a block diagram of a clock control circuit according to an embodiment of the present invention.
Fig. 2 is a block diagram of a clock control circuit according to another embodiment of the present invention.
Fig. 3 is a block diagram of a clock control circuit according to another embodiment of the invention.
Fig. 4 is a flowchart illustrating a clock control method according to an embodiment of the invention.
Fig. 5 is a flowchart illustrating a clock control method according to another embodiment of the invention.
Detailed Description
In order to make the objects, technical solutions and advantages of the present invention more apparent, the present invention is described in further detail below with reference to the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are merely illustrative of the invention and are not intended to limit the invention.
Fig. 1 is a block diagram of a clock control circuit implemented by the present invention, and the clock control circuit can be applied to a chip. As shown in fig. 1, a first clock source is disposed in the chip, and the clock control circuit 10 includes a failure detection circuit 110 and a clock gating circuit 120; the failure detection circuit 110 is respectively connected to the first clock source 20 and the preset second clock source 30, and the failure detection circuit 120 is configured to detect whether a currently gated chip master clock source is failed, where the currently gated chip master clock source is any one of the first clock source 20 and the second clock source 30. The clock gating circuit 120 is connected to the failure detection circuit, the first clock source 20 and the second clock source 30, respectively, and the clock gating circuit is configured to switch the master clock source of the chip according to the output signal of the failure detection circuit when the output signal of the failure detection circuit indicates that the currently gated chip master clock source fails. That is, the master clock source of the chip is switched from the failed clock source to the non-failed clock source in the first clock source 20 and the second clock source 30.
The first clock source 20 is disposed in the chip and is an internal clock source of the chip, such as an on-chip low-frequency clock source. The preset second clock source 30 may be an external clock source, or may be another clock source inside the chip, for example, a high frequency inside the chip such as a phase-locked loop clock source. Of course, the second clock source 30 is not limited to the above two cases, and may be any clock source set by a client, and may be switched as long as it is distinguishable from the first clock source 20. In the embodiment of the present invention, the second clock source 30 is a generic name of other clock sources except the first clock source 20, and may specifically be one clock source, or may be two or more clock sources. The second clock source may provide one or more clock signals.
Generally speaking, a chip usually has an internal clock source, the internal clock source is often low-speed, and can be used as a clock source when the chip is started or clock excitation of an internal timer of the chip, so that the chip is not easy to lose effectiveness, and after calibration, a clock error of the chip can be controlled within a certain precision range, so that the chip is stable and reliable.
The external clock source is generally divided into a high-frequency external clock source and a low-frequency external clock source, and the external clock source can be generally directly connected with the chip or connected with the chip after frequency multiplication through a phase-locked loop. Compared with an internal clock source of a chip, the external clock source often has the characteristics of higher frequency and higher precision, and if the chip is applied to the fields with higher calculation rate and higher safety requirements, such as vehicle control systems, medical equipment, fire detection systems, nuclear reactor systems and other systems, the chip only has the internal clock source and cannot meet the requirements of calculation and operation control.
The clock control circuit provided by the invention takes a relatively stable internal clock source as a first clock source, takes other clock sources as second clock sources, the first clock source and the second clock source are simultaneously and respectively connected with the failure detection circuit, the failure detection circuit carries out fault detection on the first clock source and the second clock source so as to determine whether the first clock source and the second clock source fail, and then switches a main clock source of a chip between the first clock source and the second clock source according to the fault detection result through the clock gating circuit so as to gate an effective clock source as a main clock source for the chip. Specifically, during fault detection, the master clock source of the chip is any one of the first clock source and the second clock source. And if the fault detection result indicates that the main clock source of the chip fails, switching the main clock source of the chip to another clock source.
The clock control circuit can correspondingly select an external clock source or an internal clock source as a clock according to a fault detection result, so that the clock supply of the chip is guaranteed, the clock source can be switched in time, sufficient safety guarantee measures are provided for the chip system, and the chip system is prevented from being directly hung up due to the fault of the external clock.
The clock control circuit and the chip provided by the embodiment of the invention can monitor the state of the main clock of the chip, and switch the clock source in time when the main clock fails, so that enough safety guarantee measures are provided for a chip system, the clock safety of the chip is effectively guaranteed, and the integral safety of the chip system is improved.
In one embodiment, the clock gating circuitry is primarily for: when the currently-gated chip master clock source is a first clock source and the first clock source fails, switching the currently-gated chip master clock source to a second clock source; and when the currently-gated chip master clock source is a second clock source and the second clock source fails, switching the currently-gated chip master clock source to the first clock source. The clock gating circuit switches the clock source according to the state of the main clock source, can effectively guarantee the clock supply of the chip, provides enough safety guarantee measures for the chip system, effectively guarantees the clock safety of the chip, and accordingly improves the overall safety of the chip system.
In one embodiment, the failure detection circuit is configured to detect whether the second clock source fails when the currently gated master clock source is the second clock source, and the clock gating circuit is configured to switch the currently gated master clock source from the second clock source to the first clock source when the second clock source fails. In the embodiment, the first clock source is usually stable and reliable, and only the second clock source is subjected to failure detection, so that the consumption of the system is reduced.
In one embodiment, as shown in fig. 2, the failure detection circuit 110 includes a detection module 111 and a failure comparison module 112, wherein: the detection module 111 is configured to detect a clock frequency of a currently gated master clock source and generate a reset pulse, where the currently gated master clock source is a first clock source or a second clock source; the failure comparison module 112 is configured to compare a time interval from a time when the last reset pulse is generated to a current time with a preset time threshold, and output a clock switching signal when a comparison result meets a preset condition; then, the clock gating circuit 120 switches the master clock source of the chip according to the clock switching signal.
In one embodiment, the detection module 111 may include a frequency detection circuit 1111, a reset pulse generation circuit 1112, and a timer 1113, wherein the frequency detection circuit 1111 is mainly configured to detect a clock frequency of a currently gated master clock source according to a preset detection time interval; the reset pulse generating circuit 1112 is mainly configured to generate a corresponding reset pulse according to a clock frequency; the timer 1113 is mainly configured to start timing from zero after receiving the reset pulse, that is, the timing duration of the timer 1113 is a time interval between the last time when the reset pulse is received and the current time. Correspondingly, the failure comparing module 112 is mainly configured to compare a time interval from a time when the last reset pulse is generated to a current time with a preset time threshold, and output a clock switching signal when a comparison result meets a preset condition, and output the clock switching signal when a timing duration is greater than the preset time threshold. Specifically, when the time interval from the time of the last reset pulse generation to the current time is greater than the preset time threshold, it indicates that the timer 1113 has not received the reset pulse within the time duration corresponding to the preset time threshold, that is, the currently gated master clock source may have failed to cause the reset pulse generating circuit 1112 to not normally generate the reset pulse, and at this time, the output clock switching signal may replace the master clock source of the chip in time, so as to ensure the clock supply of the chip. In this embodiment, the frequency detection circuit 1111, the reset pulse generation circuit 1112 and the timer 1113 may accurately determine the state of the master clock source, so as to switch the master clock source in time, effectively ensure the clock supply of the chip, provide sufficient security measures for the chip system, and effectively ensure the clock security of the chip.
In one embodiment, the preset time threshold and the preset time interval may be stored in a register. Specifically, the clock control circuit may further include a fail time register 130 and a detection time register 140. The failure time register 130 is connected to the failure comparison module 112 and configured to store a preset time threshold, so that the failure comparison module 112 can compare the preset time threshold with a time interval from a time when the last reset pulse is generated to a current time; the detection time register 140 is connected to the frequency detection circuit 1111 and is configured to store a detection time interval, so that the frequency detection circuit 1111 can detect the clock frequency of the currently gated master clock source according to the preset detection time interval. Optionally, the expiration time register 130 and the detection time register 140 may multiplex registers within the chip. In order to avoid misjudgment, the preset time threshold value should be greater than or equal to the preset detection time interval. In this embodiment, the stored preset time threshold and the detection time interval can be accurately and timely fed back through the failure time register 130 and the detection time register 140, so that the failure comparison module 112 can perform comparison conveniently.
In one embodiment, as shown in fig. 3, the chip may set a clock selection register according to the requirement, and the clock selection register is used to select the master clock source required by the system on chip according to the requirement of the system on chip. For example, the clock select register inputs the master clock select signal CLK _ SEL _ REG [1:0] to the clock gating circuitry.
When CLK _ SEL _ REG [1:0] ═ 0, it indicates that the first clock source is to be selected as the master clock source of the chip, at which time the internal clock signal IRC _ CLK is supplied by the first clock source.
When CLK _ SEL _ REG [1:0 ]! And when the clock signal is equal to 0, the second clock source is selected as the main clock source of the chip, and the failure detection circuit is turned on to perform failure detection on the second clock source. Optionally, the second clock source may be one or more clock sources capable of providing at least one of an external low-speed clock signal LSE _ CLK, an external high-speed clock signal HSE _ CLK, and a phase-locked loop clock signal PLL _ CLK.
When the second clock source is gated as the main clock source of the chip, the frequency detection circuit 1111 in the failure detection circuit 110 performs clock frequency detection on the second clock source selected as the main clock according to a preset detection TIME interval DET _ TIME _ REG, and outputs a reset pulse signal to the timer through the reset pulse generation circuit, so that the timing duration of the timer does not exceed the set failure TIME threshold (i.e., the preset TIME threshold).
When the second clock source fails, the frequency detection circuit cannot detect the frequency of the second clock source, so that a corresponding reset pulse cannot be generated, and the timer cannot be reset. The failure comparison module compares the timing duration of the timer with a failure TIME threshold DIS _ TIME _ REG, when the timing duration of the timer reaches the failure TIME threshold DIS _ TIME _ REG, the failure comparison module outputs a main clock switching signal to the clock gating circuit, the clock gating circuit switches a main clock source of the chip from a second clock source to a first clock source according to the main clock switching signal, and an internal clock signal IRC _ CLK provided by the first clock source is used as the main clock signal of the chip. When the master clock switching signal is output, the failure comparison module can also generate an interrupt signal INT and report the interrupt signal INT to the upper management center of the chip.
In normal use, the value of the detection TIME interval DET _ TIME _ REG should be less than the failure TIME threshold DIS _ TIME _ REG. The bit width of the failure time register and the bit width of the detection time register are selected according to the requirements of the chip system, and the threshold value with sufficient space and corresponding size is ensured to be stored.
In one embodiment, the internal clock source may also be coupled to a timer to provide a stimulus for the clock. The internal clock source of the chip is generally the clock source generated by the RC oscillator, once the chip is manufactured and molded, the frequency of the internal clock source is determined and is easy to know, the internal clock source of the chip is accessed into the timer to be used as clock excitation, the existing resources of the chip can be utilized to the maximum extent, the structure is simplified, and the chip is more stable and reliable.
An embodiment of the present invention further provides a clock control method, which is applied to a chip, where a first clock source is disposed in the chip, and as shown in fig. 4, the clock control method specifically includes the following steps:
s101, detecting whether a main clock source of the chip is invalid or not, and generating a detection signal. Specifically, whether a master clock source currently gated by the chip fails is detected, wherein the master clock source is a first clock source or a preset second clock source.
And S102, switching the main clock source of the chip when the main clock source of the chip fails according to the detection signal. Specifically, when the currently gated chip master clock source is a first clock source and the first clock source fails, switching the currently gated chip master clock source to a second clock source; and when the currently-gated chip master clock source is a second clock source and the second clock source fails, switching the currently-gated chip master clock source to the first clock source.
Therefore, the state of the chip main clock source can be timely and accurately obtained through detecting the first clock source and the second clock source, the clock source switching can be timely carried out when the main clock is invalid, an external clock source or an internal clock source is correspondingly selected as the clock, the clock supply of the chip is guaranteed, the clock source switching can also be timely carried out, sufficient safety guarantee measures are provided for the chip system, and the chip system is prevented from being directly hung due to the fault of the external clock.
In one embodiment, detecting whether a master clock source currently gated by the chip fails includes the following steps:
detecting the clock frequency of a currently gated main clock source and generating a reset pulse;
and comparing the time interval from the moment of the generation of the last reset pulse to the current moment with a preset time threshold, and determining that the currently gated master clock source is invalid when the comparison result meets the preset condition.
In an embodiment, as shown in fig. 5, the step of detecting whether the master clock source currently gated by the chip fails specifically includes:
and S1011, detecting the clock frequency of the currently gated master clock source according to a preset detection time interval.
S1012, generating a corresponding reset pulse according to the clock frequency.
And S1013, timing is started from zero according to the reset pulse, and when the timing duration is greater than a preset time threshold, the failure of the currently gated main clock source is determined.
Specifically, the clock frequency of the currently gated master clock source may be detected by a frequency detection circuit, and a corresponding reset pulse may be generated by a reset pulse generation circuit. The timer is timed by a timer which resets upon receipt of a reset pulse and starts timing from zero. And outputting the timing duration of the timer to a failure comparison module, and judging whether the timing duration of the timer is greater than a preset threshold value through the failure comparison module. When the timing duration of the timer is greater than the preset time threshold, that is, the time interval from the moment of the generation of the last reset pulse to the current moment is greater than the preset time threshold.
In summary, when the chip selects an external clock as a master clock according to task requirements, in order to ensure that the master clock of the chip is effective, the failure detection circuit is adopted to detect the external clock at regular time, once the external clock fails, the failure detection circuit will react immediately, the master clock of the chip is switched into an internal clock source by controlling the clock gating circuit, and an interrupt signal is sent to report to the upper management center of the chip, so that quick and timely reaction is realized, and the safety of the chip is ensured.
Therefore, the embodiment of the invention can improve the security level of the chip system and ensure the security of the chip system by monitoring the state of the currently accessed master clock of the chip in real time and gating another clock as the master clock source of the chip system when the chip fails, and can be effectively applied to vehicle control systems, medical equipment and fire detection systems.
The present invention is not limited to the above preferred embodiments, and any modifications, equivalent substitutions and improvements made within the spirit and principle of the present invention should be included in the protection scope of the present invention.
Claims (10)
1. A clock control circuit is applied to a chip, and a first clock source is arranged in the chip;
the failure detection circuit is respectively connected with the first clock source and a preset second clock source, and is used for detecting whether a main clock source of the chip fails, wherein the main clock source of the chip is the first clock source or the second clock source;
the clock gating circuit is respectively connected with the failure detection circuit, the first clock source and the second clock source, and the clock gating circuit is used for switching the main clock source of the chip when the main clock source of the chip fails according to the output signal of the failure detection circuit.
2. The clock control circuit of claim 1, wherein the clock gating circuit is to:
when the currently gated main clock source of the chip is the first clock source and the first clock source fails, switching the main clock source of the chip to the second clock source;
and when the currently gated main clock source of the chip is the second clock source and the second clock source fails, switching the main clock source of the chip to the first clock source.
3. The clock control circuit of claim 1, wherein the failure detection circuit comprises:
the detection module is used for detecting the clock frequency of a currently gated master clock source and generating a reset pulse, wherein the currently gated master clock source is the first clock source or the second clock source;
the failure comparison module is used for comparing a time interval from the moment generated by the latest reset pulse to the current moment with a preset time threshold and outputting a clock switching signal when the comparison result meets a preset condition;
the clock gating circuit is used for switching the main clock source of the chip according to the clock switching signal.
4. The clock control circuit of claim 3, wherein the detection module comprises:
the frequency detection circuit is used for detecting the clock frequency of the currently gated main clock source according to a preset detection time interval;
the reset pulse generating circuit is used for generating a corresponding reset pulse according to the clock frequency;
a timer for starting timing from zero after receiving the reset pulse;
the failure comparison module is used for comparing the timing duration of the timing module with the preset time threshold and outputting the clock switching signal when the timing duration is greater than the preset time threshold.
5. The clock control circuit of claim 4, wherein the clock control circuit further comprises:
the failure time register is connected with the failure comparison module and used for storing the preset time threshold;
and the detection time register is connected with the frequency detection circuit and used for storing the detection time interval.
6. A chip provided with a first clock source, characterized in that the chip is provided with a clock control circuit according to any of claims 1-5.
7. A clock control method is applied to a chip, wherein a first clock source is arranged in the chip, and the method is characterized by comprising the following steps:
detecting whether a main clock source of the chip is invalid or not, and generating a detection signal, wherein the main clock source of the chip is the first clock source or a preset second clock source;
and switching the main clock source of the chip when the main clock source of the chip fails according to the detection signal.
8. The method of claim 7, wherein said detecting whether the first clock source and a predetermined second clock source fail comprises:
detecting whether a main clock source currently gated by the chip is invalid, wherein the main clock source is the first clock source or the second clock source;
the switching of the master clock source of the chip includes:
when the currently gated main clock source of the chip is the first clock source and the first clock source fails, switching the main clock source of the chip to the second clock source;
and when the currently gated main clock source of the chip is the second clock source and the second clock source fails, switching the main clock source of the chip to the first clock source.
9. The method of claim 8,
the detecting whether the main clock source currently gated by the chip is invalid includes:
detecting the clock frequency of a currently gated main clock source and generating a reset pulse;
and comparing the time interval from the moment of the generation of the last reset pulse to the current moment with a preset time threshold, and determining that the currently gated master clock source is invalid when the comparison result meets the preset condition.
10. The method of claim 9, wherein detecting the clock frequency of the currently strobed master clock source and generating a reset pulse comprises:
detecting the clock frequency of the currently gated master clock source according to a preset detection time interval;
generating a corresponding reset pulse according to the clock frequency;
comparing the time interval from the moment of the last reset pulse to the current moment with a preset time threshold, and determining that the currently gated master clock source is invalid when the comparison result meets a preset condition, the method includes:
and timing from zero according to the reset pulse, and determining that the currently gated master clock source is invalid when the timing duration is greater than the preset time threshold.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
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| CN202010797109.8A CN112083755A (en) | 2020-08-10 | 2020-08-10 | Clock control circuit, chip and clock control method |
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| CN112685242A (en) * | 2021-01-08 | 2021-04-20 | 合肥六角形半导体有限公司 | Chip system clock safety guarantee circuit and chip |
| CN113282133A (en) * | 2021-06-15 | 2021-08-20 | 西安微电子技术研究所 | Internal and external clock switching circuit and method for time correction of satellite-borne system |
| CN115268572A (en) * | 2022-07-30 | 2022-11-01 | 上海锐星微电子科技有限公司 | Real-time clock circuit |
| WO2023010250A1 (en) * | 2021-08-02 | 2023-02-09 | 华为技术有限公司 | Control apparatus, electronic control system, and vehicle |
| CN116643156A (en) * | 2023-07-21 | 2023-08-25 | 北京城建智控科技股份有限公司 | On-chip self-checking device, method, electronic equipment and storage medium |
| CN116722868A (en) * | 2023-08-08 | 2023-09-08 | 苏州浪潮智能科技有限公司 | Clock holding system, method and storage device |
| CN118062033A (en) * | 2024-04-18 | 2024-05-24 | 南京仁芯科技有限公司 | Vehicle-mounted SerDes chip, video transmission system comprising same and vehicle |
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| CN112685242A (en) * | 2021-01-08 | 2021-04-20 | 合肥六角形半导体有限公司 | Chip system clock safety guarantee circuit and chip |
| CN113282133A (en) * | 2021-06-15 | 2021-08-20 | 西安微电子技术研究所 | Internal and external clock switching circuit and method for time correction of satellite-borne system |
| WO2023010250A1 (en) * | 2021-08-02 | 2023-02-09 | 华为技术有限公司 | Control apparatus, electronic control system, and vehicle |
| CN115268572A (en) * | 2022-07-30 | 2022-11-01 | 上海锐星微电子科技有限公司 | Real-time clock circuit |
| CN115268572B (en) * | 2022-07-30 | 2023-06-16 | 上海锐星微电子科技有限公司 | Real-time clock circuit |
| CN116643156A (en) * | 2023-07-21 | 2023-08-25 | 北京城建智控科技股份有限公司 | On-chip self-checking device, method, electronic equipment and storage medium |
| CN116643156B (en) * | 2023-07-21 | 2023-11-07 | 北京城建智控科技股份有限公司 | On-chip self-checking device, method, electronic equipment and storage medium |
| CN116722868A (en) * | 2023-08-08 | 2023-09-08 | 苏州浪潮智能科技有限公司 | Clock holding system, method and storage device |
| CN116722868B (en) * | 2023-08-08 | 2023-11-03 | 苏州浪潮智能科技有限公司 | Clock holding system, method and storage device |
| CN118062033A (en) * | 2024-04-18 | 2024-05-24 | 南京仁芯科技有限公司 | Vehicle-mounted SerDes chip, video transmission system comprising same and vehicle |
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Application publication date: 20201215 |