CN111510138A - Crystal clock failure detection system and detection method thereof - Google Patents
Crystal clock failure detection system and detection method thereof Download PDFInfo
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- CN111510138A CN111510138A CN202010331960.1A CN202010331960A CN111510138A CN 111510138 A CN111510138 A CN 111510138A CN 202010331960 A CN202010331960 A CN 202010331960A CN 111510138 A CN111510138 A CN 111510138A
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- H—ELECTRICITY
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- H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
- H03L7/00—Automatic control of frequency or phase; Synchronisation
- H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
- H03L7/16—Indirect frequency synthesis, i.e. generating a desired one of a number of predetermined frequencies using a frequency- or phase-locked loop
- H03L7/18—Indirect frequency synthesis, i.e. generating a desired one of a number of predetermined frequencies using a frequency- or phase-locked loop using a frequency divider or counter in the loop
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Abstract
The invention discloses a crystal clock failure detection system and a detection method thereof, wherein the crystal clock failure detection method comprises the following steps of S1, starting a detected crystal clock to enable a detected crystal clock counter and an RC L clock counter to count simultaneously, S2, judging that the detected crystal clock reaches a working state if the RC L clock counter does not reach a set overflow value and the detected crystal clock reaches a stable state, executing the step S3, and S3, after the detected crystal clock reaches the working state, enabling the detected crystal clock counter and the RC L clock counter to count simultaneously.
Description
Technical Field
The invention belongs to the technical field of crystal clocks, and particularly relates to a crystal clock failure detection system and a crystal clock failure detection method.
Background
Crystal clocks have a large number of and wide applications as clock generators for electronic devices in systems. It is often referred to as the "heart" of an electronic device because it can generate a clock signal throughout the electronic device.
If the crystal clock is out of order or even stops, it must have a significant impact on the operation of the electronic device and can even cause system failure. The traditional method for detecting the failure of the failed crystal clock is generally used for detecting by using experience, and a set of determined detection flow and a set of detection method are not available for detecting the failed crystal clock at present.
The publication number is: CN108169651A, entitled an invention patent of a clock crystal oscillator detection method, the technical proposal thereof discloses an integral detection process, which comprises the following steps: using a microscope to check the appearance of the device, including a shell, a bonding pad and a lead, whether pollution, separation, defect and corrosion exist or not; x-ray is used for detecting whether open circuit and short circuit exist at the connecting parts of the bonding wire, the conductive adhesive and other metals; unsealing detection process, comprising the following steps: detecting whether the wafer, the electrode, the base, the bracket and the dispensing point are damaged, polluted, cracked and broken by using a microscope or a metallographic microscope; the unsealing detection process is carried out after the integral detection process; and any step obtains a positive result, the failure reason of the clock crystal oscillator is confirmed, and other steps are not carried out.
Taking the above patent as an example, it is a detection of a clock crystal oscillator, which is different from the technical scheme and technical problem of the present invention. Therefore, the above problems are further improved.
Disclosure of Invention
The invention mainly aims to provide a crystal clock failure detection system and a detection method thereof, which can multiplex three circuits of clock stabilization, clock failure detection and clock starting detection to realize the functions of the crystal clock failure detection system, effectively save the chip area, reduce the system power consumption and improve the system stability.
Another objective of the present invention is to provide a crystal clock failure detection system and a detection method thereof, which share a clock counter, thereby simplifying circuit design, saving area, and reducing power consumption.
To achieve the above object, the present invention provides a method for detecting crystal clock failure, which is used to detect crystal clock failure, and comprises the following steps:
step S1, starting the detected crystal clock to make the detected crystal clock counter and RC L clock counter count at the same time, and detecting the detected crystal clock according to the overflow state of the RC L clock counter and the stable state of the detected crystal clock;
step S2, if the RC L clock counter does not reach the set overflow value and the detected crystal clock reaches the stable state, the detected crystal clock is judged to reach the working state, step S3 is executed, otherwise, the detected crystal clock is judged to be failed (fail) and step S1 is executed;
in step S3, the detected crystal clock counter and the RC L clock counter count simultaneously after the detected crystal clock reaches the working state, and the detected crystal clock is detected according to the overflow state of the RC L clock counter and the threshold state of the detected crystal clock counter.
As a further preferable embodiment of the above technical means, step S1 is specifically implemented as the following steps:
step S1.1, after the detected crystal clock is started, an RC L clock counter is used for timing, and the detected crystal clock is detected according to the overflow state of an RC L clock counter;
step S1.2: and after the detected crystal clock is started, the detected crystal clock counter counts time and detects the detected crystal clock according to the stable state of the detected crystal clock counter.
As a further preferable embodiment of the above technical means, step S1 is specifically implemented as the following steps:
step S1.1.1, if the RC L clock counter does not reach the set overflow value, the RC L clock counter continues counting;
in step S1.1.2, if the clock counter of RC L does not reach the set overflow value and the detected crystal clock reaches a steady state, the detected crystal clock is determined to reach the working state.
As a further preferred embodiment of the above technical solution, step S1.2 is specifically implemented as the following steps:
step S1.2.1: if the detected crystal clock does not reach the stable state, the detected crystal clock counter continues counting;
at S1.2.2, if the detected crystal clock does not reach a steady state and the RC L clock counter reaches a predetermined overflow value, then the detected crystal clock is determined to be failed (fail).
As a further preferable embodiment of the above technical means, step S3 is specifically implemented as the following steps:
step S3.1: if the detected crystal clock counter does not count to the threshold value, the detected crystal clock counter continues counting;
s3.2, if the detected crystal clock counter counts to a threshold value, resetting the RC L clock counter;
step S3.3, if the RC L clock counter does not reach the preset overflow value, the RC L clock counter continues to count;
step S3.4, if the RC L clock counter reaches a predetermined overflow value, the detected crystal clock is determined to be invalid (fault).
To achieve the above object, the present invention provides a crystal clock failure detection system for detecting crystal clock failure, comprising a detected crystal clock, an RC L clock, a detected crystal clock counter and an RC L clock counter, wherein:
starting the detected crystal clock to enable the detected crystal clock counter and the RC L clock counter to count simultaneously, and detecting the detected crystal clock according to the overflow state of the RC L clock counter and the stable state of the detected crystal clock;
if the RC L clock counter does not reach the set overflow value and the detected crystal clock reaches the stable state, judging that the detected crystal clock reaches the working state, otherwise, judging that the detected crystal clock fails (fail);
and after the detected crystal clock reaches the working state, the detected crystal clock counter and the RC L clock counter count simultaneously, and the detected crystal clock is detected according to the overflow state of the RC L clock counter and the threshold state of the detected crystal clock counter.
Drawings
Fig. 1 is a circuit block diagram of a crystal clock failure detection system and a detection method thereof according to the present invention.
Fig. 2 is a schematic diagram of a clock start-up process of the crystal clock failure detection system and the detection method thereof according to the present invention.
FIG. 3 is a clock fail detection flow chart of the crystal clock fail detection system and the detection method thereof according to the present invention.
FIG. 4 is a timing diagram of clock fail detection in the crystal clock failure detection system and the detection method thereof according to the present invention.
FIG. 5 is a clock fault detection flow chart of the crystal clock failure detection system and the detection method thereof according to the present invention.
FIG. 6 is a timing diagram of clock fault detection in the crystal clock failure detection system and the detection method thereof according to the present invention.
The reference numerals include:
Detailed Description
The following description is presented to disclose the invention so as to enable any person skilled in the art to practice the invention. The preferred embodiments in the following description are given by way of example only, and other obvious variations will occur to those skilled in the art. The basic principles of the invention, as defined in the following description, may be applied to other embodiments, variations, modifications, equivalents, and other technical solutions without departing from the spirit and scope of the invention.
Referring to fig. 1 of the drawings, fig. 1 is a circuit block diagram of a crystal clock failure detection system and a detection method thereof according to the present invention, fig. 2 is a clock start-up process schematic diagram of the crystal clock failure detection system and the detection method thereof according to the present invention, fig. 3 is a clock fail detection flow chart of the crystal clock failure detection system and the detection method thereof according to the present invention, fig. 4 is a clock fail detection timing schematic diagram of the crystal clock failure detection system and the detection method thereof according to the present invention, fig. 5 is a clock fail detection flow chart of the crystal clock failure detection system and the detection method thereof according to the present invention, and fig. 6 is a clock fail detection timing schematic diagram of the crystal clock failure detection system and the detection method thereof according to the present invention.
In the preferred embodiment of the present invention, those skilled in the art should note that the RC L clock, RC L clock counter, etc. referred to in the present invention can be regarded as the prior art.
Preferred embodiments.
The invention discloses a crystal clock failure detection method, which is used for detecting crystal clock failure and comprises the following steps:
step S1, starting the detected crystal clock to make the detected crystal clock counter and RC L clock counter count at the same time, and detecting the detected crystal clock according to the overflow state of the RC L clock counter and the stable state of the detected crystal clock;
step S2, if the RC L clock counter does not reach the set overflow value and the detected crystal clock reaches the stable state, the detected crystal clock is judged to reach the working state, step S3 is executed, otherwise, the detected crystal clock is judged to be failed (fail) and step S1 is executed;
in step S3, the detected crystal clock counter and the RC L clock counter count simultaneously after the detected crystal clock reaches the working state, and the detected crystal clock is detected according to the overflow state of the RC L clock counter and the threshold state of the detected crystal clock counter.
Preferably, the method is divided into three stages after the detected crystal clock is enabled (XT L _ EN), namely a starting stage (starting stage), a stable stage (stable stage) and a working stage (work stage), wherein the amplitude of the clock output in the starting stage is relatively low, the digital circuit cannot be normally identified, and the stable stage is that the clock output reaches a certain amplitude and the digital circuit can identify but the clock is not stable.
Preferably, as shown in fig. 1, the circuit mainly includes 2 counters and associated logic, XT L is the detected clock, RC L is the reference clock, and two counters are included inside, one counter (RC L CNT) counts with RC L as the clock, and the other counter (XT L CNT) counts with XT L crystal as the counting clock.
Preferably, as can be seen from fig. 2, when the clock is stable during the startup phase, the RC L clock counter (RC L CNT) does not exceed the upper limit of the count, and does not enter into fail state and enters into working state.
Preferably, according to fig. 3, when the RC L counter reaches the set overflow value, the detected crystal clock counter (XT L CNT) does not reach the steady state, and a fail flag is generated to enter a fail state, thereby notifying the system of abnormal crystal start.
According to fig. 5 and 6, the detected crystal clock has reached a stable state and enters a working state, the XT L counter (XT L CNT) resets the RC L counter (RC L CNT) at a fixed count interval, if the RC L counter does not overflow, it indicates that the XT L working state is normal, if the XT L crystal is not working normally, the count interval is lengthened, the RC L counter will overflow, a fault flag is generated, and the fault state is entered to notify the system XT L that the crystal is abnormal in working state.
Specifically, step S1 is implemented as the following steps:
step S1.1, after the detected crystal clock is started, an RC L clock counter is used for timing, and the detected crystal clock is detected according to the overflow state of an RC L clock counter;
step S1.2: and after the detected crystal clock is started, the detected crystal clock counter counts time and detects the detected crystal clock according to the stable state of the detected crystal clock counter.
More specifically, step S1 is specifically implemented as the following steps:
step S1.1.1, if the RC L clock counter does not reach the set overflow value, the RC L clock counter continues counting;
in step S1.1.2, if the clock counter of RC L does not reach the set overflow value and the detected crystal clock reaches a steady state, the detected crystal clock is determined to reach the working state.
Further, step S1.2 is embodied as the following steps:
step S1.2.1: if the detected crystal clock does not reach the stable state, the detected crystal clock counter continues counting;
at S1.2.2, if the detected crystal clock does not reach a steady state and the RC L clock counter reaches a predetermined overflow value, then the detected crystal clock is determined to be failed (fail).
Further, step S3 is implemented as the following steps:
step S3.1: if the detected crystal clock counter does not count to the threshold value, the detected crystal clock counter continues counting;
s3.2, if the detected crystal clock counter counts to a threshold value, resetting the RC L clock counter;
step S3.3, if the RC L clock counter does not reach the preset overflow value, the RC L clock counter continues to count;
step S3.4, if the RC L clock counter reaches a predetermined overflow value, the detected crystal clock is determined to be invalid (fault).
The invention also discloses a crystal clock failure detection system, which is used for detecting the crystal clock failure and comprises a detected crystal clock, an RC L clock, a detected crystal clock counter and an RC L clock counter, wherein:
starting the detected crystal clock to enable the detected crystal clock counter and the RC L clock counter to count simultaneously, and detecting the detected crystal clock according to the overflow state of the RC L clock counter and the stable state of the detected crystal clock;
if the RC L clock counter does not reach the set overflow value and the detected crystal clock reaches the stable state, judging that the detected crystal clock reaches the working state, otherwise, judging that the detected crystal clock fails (fail);
and after the detected crystal clock reaches the working state, the detected crystal clock counter and the RC L clock counter count simultaneously, and the detected crystal clock is detected according to the overflow state of the RC L clock counter and the threshold state of the detected crystal clock counter.
It should be noted that the technical features of the RC L clock, the RC L clock counter, etc. related to the present patent application should be regarded as the prior art, and the specific structure, the operation principle, the control mode and the spatial arrangement mode of the technical features may be selected conventionally in the field, and should not be regarded as the invention point of the present patent, and the present patent is not further specifically described in detail.
It will be apparent to those skilled in the art that modifications and equivalents may be made in the embodiments and/or portions thereof without departing from the spirit and scope of the present invention.
Claims (6)
1. A method for detecting crystal clock failure is used for detecting crystal clock failure, and is characterized by comprising the following steps:
step S1, starting the detected crystal clock to make the detected crystal clock counter and RC L clock counter count at the same time, and detecting the detected crystal clock according to the overflow state of the RC L clock counter and the stable state of the detected crystal clock;
step S2, if the RC L clock counter does not reach the set overflow value and the detected crystal clock reaches the stable state, the detected crystal clock is judged to reach the working state, step S3 is executed, otherwise, the detected crystal clock is judged to be invalid and step S1 is executed;
in step S3, the detected crystal clock counter and the RC L clock counter count simultaneously after the detected crystal clock reaches the working state, and the detected crystal clock is detected according to the overflow state of the RC L clock counter and the threshold state of the detected crystal clock counter.
2. The method as claimed in claim 1, wherein the step S1 is implemented as the following steps:
step S1.1, after the detected crystal clock is started, an RC L clock counter is used for timing, and the detected crystal clock is detected according to the overflow state of an RC L clock counter;
step S1.2: and after the detected crystal clock is started, the detected crystal clock counter counts time and detects the detected crystal clock according to the stable state of the detected crystal clock counter.
3. The method as claimed in claim 2, wherein the step S1 is implemented as the following steps:
step S1.1.1, if the RC L clock counter does not reach the set overflow value, the RC L clock counter continues counting;
in step S1.1.2, if the clock counter of RC L does not reach the set overflow value and the detected crystal clock reaches a steady state, the detected crystal clock is determined to reach the working state.
4. The method as claimed in claim 3, wherein the step S1.2 is implemented as the following steps:
step S1.2.1: if the detected crystal clock does not reach the stable state, the detected crystal clock counter continues counting;
at S1.2.2, if the detected crystal clock does not reach a steady state and the RC L clock counter reaches a predetermined overflow value, it is determined that the detected crystal clock is invalid.
5. The method as claimed in any one of claims 1 or 4, wherein the step S3 is implemented as the following steps:
step S3.1: if the detected crystal clock counter does not count to the threshold value, the detected crystal clock counter continues counting;
s3.2, if the detected crystal clock counter counts to a threshold value, resetting the RC L clock counter;
step S3.3, if the RC L clock counter does not reach the preset overflow value, the RC L clock counter continues to count;
step S3.4, if the RC L clock counter reaches a predetermined overflow value, the detected crystal clock is determined to be invalid.
6. A crystal clock failure detection system for detecting crystal clock failure, comprising a detected crystal clock, an RC L clock, a detected crystal clock counter, and an RC L clock counter, wherein:
starting the detected crystal clock to enable the detected crystal clock counter and the RC L clock counter to count simultaneously, and detecting the detected crystal clock according to the overflow state of the RC L clock counter and the stable state of the detected crystal clock;
if the RC L clock counter does not reach the set overflow value and the detected crystal clock reaches the stable state, judging that the detected crystal clock reaches the working state, otherwise, judging that the detected crystal clock fails;
and after the detected crystal clock reaches the working state, the detected crystal clock counter and the RC L clock counter count simultaneously, and the detected crystal clock is detected according to the overflow state of the RC L clock counter and the threshold state of the detected crystal clock counter.
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| CN202010331960.1A CN111510138A (en) | 2020-04-24 | 2020-04-24 | Crystal clock failure detection system and detection method thereof |
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| CN202010331960.1A CN111510138A (en) | 2020-04-24 | 2020-04-24 | Crystal clock failure detection system and detection method thereof |
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Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN112083755A (en) * | 2020-08-10 | 2020-12-15 | 合肥市芯海电子科技有限公司 | Clock control circuit, chip and clock control method |
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- 2020-04-24 CN CN202010331960.1A patent/CN111510138A/en not_active Withdrawn
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN112083755A (en) * | 2020-08-10 | 2020-12-15 | 合肥市芯海电子科技有限公司 | Clock control circuit, chip and clock control method |
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Application publication date: 20200807 |