CN205750769U - Clock monitoring circuit - Google Patents
Clock monitoring circuit Download PDFInfo
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- CN205750769U CN205750769U CN201620512523.9U CN201620512523U CN205750769U CN 205750769 U CN205750769 U CN 205750769U CN 201620512523 U CN201620512523 U CN 201620512523U CN 205750769 U CN205750769 U CN 205750769U
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Abstract
The open a kind of clock monitoring circuit of this utility model, by arranging two low-frequency clock source modules, (one is the low-frequency clock module of chip internal, another one is plug-in low-frequency clock source module), doubleclocking source module is utilized to provide the reliability of clock of system, simultaneity factor itself possesses by the high frequency clock module of low-frequency clock source raising frequency, the input clock source of high frequency clock module can be external low frequency clock or internal low-frequency clock, this high-frequency model can also maintain the clock frequency of more than twice higher than low frequency after the low-frequency clock source of input quits work by the self-oscillation of module itself.When clock monitoring module monitor external clock module occur that exception or internal clocking low frequency module occur abnormal time; clock supervision module will export corresponding flag bit with interrupt to clock abnormality processing module, clock abnormality processing module will switch to another one low-frequency clock module the clock source of high frequency input module accordingly.
Description
Technical field
This utility model relates to electronic circuit technology field, is specifically related to a kind of clock monitoring circuit.
Background technology
Current electronic product often works in various rugged environment, and such as electromagnetic interference, power supply disturbance, electrostatic are done
Disturbing, this just requires that we are when designing electronic product, it is necessary to take into full account with the board design stage in chip design stage
The reliability of clock system.Wherein, the board design stage can pass through PCB layout, use strong interference immunity element and
Reasonably circuit design improves reliability, but when chip design, it is necessary to just advise from the system design stage started most
Pull reliable clock system, in order to improve reliability, but even if so, the clock source of chip still exists appearance exception
Risk.Thus, it is necessary to consider the exception handling of a set of clock source, clock source is avoided to occur abnormal and cause whole electricity
Sub-product crashes.
Utility model content
This utility model aims to provide a kind of clock monitoring circuit, abnormal to be guaranteed in the clock source appearance of clock system
Time, the clock source of switching clock so that chip can quickly be resumed work after being always maintained at normally working or breaking down.
This utility model is achieved through the following technical solutions:
A kind of clock monitoring circuit, including external low frequency clock module, internal low-frequency clock module, high frequency clock module,
Clock supervision module, clock abnormality processing module, electronic working system and clock source selection module；External low frequency clock module and
The output of internal low-frequency clock module connects two inputs of clock source selection module, the output of clock abnormality processing module respectively
The selection connecting clock source selection module controls end, when controlling clock source selection module selection external low frequency clock or internal low-frequency
Clock；The output of external low frequency clock module and internal low-frequency clock module is also respectively connected to clock supervision module, clock supervision mould
Low-frequency clock selected by clock source selection module is monitored and for abnormal low-frequency clock to clock abnormality processing mould by block
Block output clock abnormal indication signal and clock aborted signal；The output of clock source selection module connects high frequency clock mould
Block, high frequency clock module is clock supervision module, clock abnormality processing module and electronic working system provide more than current low frequency
High frequency clock signal more than clock source frequency twice.
As concrete technical scheme, described high frequency clock module include phase frequency detector, electric charge pump, voltage controlled oscillator and
Frequency divider；The first input end incoming clock source of phase frequency detector selects the low-frequency clock signal that module selects, phase frequency detector
Output connect electric charge pump input, electric charge pump output connect voltage controlled oscillator input, the output conduct of voltage controlled oscillator
The output of high frequency clock module, the output of voltage controlled oscillator accesses the second input of phase frequency detector simultaneously by frequency divider.
As concrete technical scheme, described clock supervision module includes that alternative selector, low-frequency clock signal detect
Unit and clock anomaly analysis unit；Two inputs of the alternative selector of clock supervision module, the choosing of alternative selector
Selecting the selection control end controlling end connection clock source selection module, the output of alternative selector connects low-frequency clock signal detection
Unit, the output of low-frequency clock signal detector unit connects the input of clock anomaly analysis unit, clock anomaly analysis unit
Output connects the signal receiving end of clock abnormality processing module.
As further technical scheme, described clock monitoring circuit also includes that clock supervision enables module, and this clock is supervised
Control enables the signal output part that enables of module and connects the enable control end of clock supervision module.
By arranging two low-frequency clock source modules, (one is the low-frequency clock module of chip internal to this utility model, separately
Outer one is plug-in low-frequency clock source module), utilize doubleclocking source module to provide the reliability of clock of system, simultaneity factor is originally
Body possesses by the high frequency clock module of low-frequency clock source raising frequency, when the input clock source of high frequency clock module can be external low frequency
Clock or internal low-frequency clock, this high-frequency model can also pass through module itself after the low-frequency clock source of input quits work
Self-oscillation maintain clock frequency more than twice higher than low frequency.Occur when clock monitoring module monitors external clock module
When exception or internal clocking low frequency module occur abnormal, clock supervision module will export corresponding flag bit with interrupt to
Clock abnormality processing module, clock abnormality processing module will switch to another one the clock source of high frequency input module accordingly
Low-frequency clock module.
Accompanying drawing explanation
The pie graph of the clock monitoring circuit that Fig. 1 provides for this utility model embodiment.
The pie graph of the clock monitoring circuit medium-high frequency clock module that Fig. 2 provides for this utility model embodiment.
Detailed description of the invention
During as it is shown in figure 1, the clock monitoring circuit that the present embodiment provides includes external low frequency clock module 1, internal low-frequency
Clock module 2, high frequency clock module 3, clock supervision module 4, clock abnormality processing module 5, electronic working system 6, clock supervision
Enable module 7 and clock source selection module 8.Wherein, clock supervision module 4 includes that alternative selector, low-frequency clock signal are examined
Survey unit 9 and clock anomaly analysis unit 10.
The output of external low frequency clock module 1 and internal low-frequency clock module 2 meets two of clock source selection module 8 respectively
Input, the control end that selects of clock source selection module 8 connects the output of clock abnormality processing module 5.External low frequency clock mould
The output of block 1 and internal low-frequency clock module 2 connects two inputs of the alternative selector of clock supervision module 4 the most respectively, and two
The selection selecting to control end connection clock source selection module 8 selecting a selector controls end, and the output of alternative selector connects
Low-frequency clock signal detector unit 9, the output of low-frequency clock signal detector unit 9 connects the defeated of clock anomaly analysis unit 10
Entering, the output of clock anomaly analysis unit 10 connects the signal receiving end of clock abnormality processing module 5.Clock source selection module 8
Output connect high frequency clock module 3, the output of high frequency clock module 3 connects clock abnormality processing module 5 and electronics work respectively
Make system 6.The enable of the output connection clock supervision module 4 that clock supervision enables module 7 controls end.
When the high frequency clock module 3 that external low frequency clock module 1 and internal low-frequency clock module 2 are system provides used
Zhong Yuan, arranges synchronization by clock source selection module 8 and one of both can only be selected as the clock of high frequency clock module 3
Source.The clock source selected produces more than input clock source as the input clock source of high frequency clock module 3, high frequency clock module 3
Clock frequency more than frequency twice, defeated as whole electronic working system 6, clock supervision module 4 and abnormality processing module 5
Enter clock.Clock supervision module 4 uses the clock supervision external low frequency clock module 1 or inside that high frequency clock module 3 provides
The low-frequency clock that low-frequency clock module 2 produces.Low-frequency clock signal detector unit 9 within clock supervision module 4 is responsible for monitoring
The rising edge of input clock is tied according to the monitoring of low-frequency clock signal detector unit 9 with trailing edge, clock anomaly analysis unit 10
Fruit analyzes whether the low-frequency clock signal of input clock monitoring module 4 exists exception, and low-frequency clock signal detector unit 9 monitors
Start timing during rising edge, monitor trailing edge and stop timing, exceed defeated when monitoring the rising edge time interval to trailing edge
The normal clock periodic regime or the low-frequency clock signal detection 9 that enter low-frequency clock detect that the clock of input stops always always
Exceed normal clock periodic regime at fixing level, then represent low-frequency clock abnormal (during low-frequency clock exception, high frequency clock mould
Block 3 still can maintain the low-frequency clock signal higher than 2 times, in order to ensures that clock supervision module 4 is working properly), then abnormal point
Analysis the module 10 just abnormal instruction of output clock and clock aborted.
If the low-frequency clock that clock source selection module 8 selects external low frequency clock module 1 is supervised as system clock, clock
Control enables module 7 and enables clock supervision module 4, and clock supervision module 4 begins to monitor the clock signal of external clock module 1,
If be detected that within the cycle of the low-frequency clock of external low frequency clock module 1 is always held at normal clock periodic regime, then
Clock supervision module 4 does not the most send clock and extremely indicates and clock aborted, but if be detected that external low frequency clock module 1
Cycle of low-frequency clock exceed normal clock periodic regime or clock frequency rests on some fixing electricity always always
Putting down and exceed a period of time, clock supervision module 4 will send the abnormal instruction of clock and clock aborted to clock abnormality processing
Module 5, clock abnormality processing module 5 by the abnormal instruction of inquiry clock or detects outside by interrupt processing service routine
Low-frequency clock module 1 is abnormal, then clock abnormality processing module 5 just can start internal clocking module 2 immediately, waits internal low
Frequently notify after clock module 2 is working properly that the clock source of high frequency clock module 4 is switched to inside by clock source selection module 8 immediately
Low-frequency clock module 2.If the clock source that originally contrary system is selected is internal low-frequency clock module 2, enable clock supervision mould
Block 4 just can monitor internal low-frequency clock module 2, if there is exception in internal low-frequency clock module 2, and correspondingly clock exception
Reason module 5 just can notify that the clock source of high frequency clock module 3 is switched to external low frequency clock by clock source selection module 8 immediately
Module 1.
As in figure 2 it is shown, high frequency clock module 3 includes phase frequency detector 12, electric charge pump 13, voltage controlled oscillator 14, frequency divider
15.The first input end incoming clock source of phase frequency detector 12 selects the low-frequency clock signal that module 8 selects, phase frequency detector 12
Output connect electric charge pump 13 input, electric charge pump 13 output connect voltage controlled oscillator 14 input, voltage controlled oscillator 14
Exporting the output as high frequency clock module 3, the output of voltage controlled oscillator 14 accesses phase frequency detector by frequency divider 15 simultaneously
Second input of 12.
In this utility model, no matter whether low-frequency clock module occurs extremely to ensure that high frequency clock module 3 exports
Clock be more than the twice of low-frequency clock.Wherein, the voltage that the frequency of oscillation of voltage controlled oscillator 14 is exported by electric charge pump 13
Control, and linear between frequency of oscillation and control voltage.The effect of phase frequency detector 12 is the low frequency letter of detection input
Number with the frequency of output signal that fed back by frequency divider 15 is with phase contrast, and by the phase signal that detects by electricity
Lotus pump 13 is converted into voltage signal output, thus the output frequency controlling voltage controlled oscillator 14 stablizes the frequency wanting setting user
Rate value.In this utility model, if the low-frequency clock signal of input is fixed on a fixing electricity after there is exception or failure of oscillation
Flat, voltage controlled oscillator 14 also can keep exporting 2 times of normal low frequency signals.
Having the beneficial effects that of the present embodiment:
1, two low-frequency clock sources are used, an inside, an outside, it is ensured that the reliability of clock source.
2, inside and outside low-frequency clock source can be monitored simultaneously, go wrong when monitoring currently used clock source,
Clock abnormality processing module is just switched to another one clock source clock source.
3, high frequency clock signal is from low-frequency clock source module raising frequency, it is not necessary to chip internal or outside regenerate
One high frequency clock.
4, high frequency clock module is after low-frequency clock source occurs extremely, can maintain self-oscillation, remains abnormal to clock
Processing module provides clock with clock supervision module.
Above-described embodiment only have expressed a kind of exemplary embodiment of the present utility model, and it describes more concrete and detailed,
But therefore can not be interpreted as the restriction to this utility model the scope of the claims.It will be apparent to those skilled in the art that do not taking off
Under concept thereof of the present utility model, the some deformation made or improvement, broadly fall into exposure scope of the present utility model.
Claims (4)
1. a clock monitoring circuit, it is characterised in that: include external low frequency clock module, internal low-frequency clock module, high frequency
Clock module, clock supervision module, clock abnormality processing module, electronic working system and clock source selection module；External low frequency
The output of clock module and internal low-frequency clock module connects two inputs of clock source selection module, clock abnormality processing respectively
Module output connect clock source selection module selection control end, control clock source selection module select external low frequency clock or
Internal low-frequency clock；The output of external low frequency clock module and internal low-frequency clock module is also respectively connected to clock supervision module,
Low-frequency clock selected by clock source selection module is monitored and for abnormal low-frequency clock to clock by clock supervision module
Abnormality processing module output clock abnormal indication signal and clock aborted signal；The output of clock source selection module connects height
Frequently clock module, high frequency clock module is clock supervision module, clock abnormality processing module and electronic working system provide and be more than
High frequency clock signal more than current low-frequency clock source frequency twice.
Clock monitoring circuit the most according to claim 1, it is characterised in that: described high frequency clock module includes frequency and phase discrimination
Device, electric charge pump, voltage controlled oscillator and frequency divider；The first input end incoming clock source of phase frequency detector selects the low of module selection
Frequently clock signal, the output of phase frequency detector connects the input of electric charge pump, and the output of electric charge pump connects the input of voltage controlled oscillator,
The output of voltage controlled oscillator is as the output of high frequency clock module, and the output of voltage controlled oscillator accesses frequency discrimination by frequency divider simultaneously
Second input of phase discriminator.
Clock monitoring circuit the most according to claim 1, it is characterised in that: described clock supervision module includes that alternative selects
Select device, low-frequency clock signal detector unit and clock anomaly analysis unit；Two of the alternative selector of clock supervision module
Input, the selecting of alternative selector controls end and connects the selection of clock source selection module and control end, alternative selector defeated
Going out to connect low-frequency clock signal detector unit, the output of low-frequency clock signal detector unit connects the defeated of clock anomaly analysis unit
Entering, the output of clock anomaly analysis unit connects the signal receiving end of clock abnormality processing module.
4. according to the clock monitoring circuit described in claim 1,2 or 3, it is characterised in that: described clock monitoring circuit also includes
Clock supervision enables module, and this clock supervision enables the signal output part that enables of module and connects the enable control of clock supervision module
End.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201620512523.9U CN205750769U (en) | 2016-05-30 | 2016-05-30 | Clock monitoring circuit |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201620512523.9U CN205750769U (en) | 2016-05-30 | 2016-05-30 | Clock monitoring circuit |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN205750769U true CN205750769U (en) | 2016-11-30 |
Family
ID=57362475
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201620512523.9U Withdrawn - After Issue CN205750769U (en) | 2016-05-30 | 2016-05-30 | Clock monitoring circuit |
Country Status (1)
| Country | Link |
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| CN (1) | CN205750769U (en) |
Cited By (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN106066817A (en) * | 2016-05-30 | 2016-11-02 | 珠海市微半导体有限公司 | clock monitoring circuit and method thereof |
| CN109839838A (en) * | 2017-11-29 | 2019-06-04 | 中国科学院沈阳自动化研究所 | It is synchronized and integrating device of meeting an urgent need from principal mode submersible high-accuracy self-adaptation |
| CN110690894A (en) * | 2019-09-20 | 2020-01-14 | 上海励驰半导体有限公司 | Clock failure safety protection method and circuit |
| CN111726190A (en) * | 2020-06-18 | 2020-09-29 | 四川艾贝斯科技发展有限公司 | System time calibration method for street lamp control system |
| CN112114616A (en) * | 2020-08-04 | 2020-12-22 | 深圳市宏电技术股份有限公司 | Switching method of real-time clock, electronic equipment and computer storage medium |
-
2016
- 2016-05-30 CN CN201620512523.9U patent/CN205750769U/en not_active Withdrawn - After Issue
Cited By (7)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN106066817A (en) * | 2016-05-30 | 2016-11-02 | 珠海市微半导体有限公司 | clock monitoring circuit and method thereof |
| CN106066817B (en) * | 2016-05-30 | 2023-04-07 | 珠海市一微半导体有限公司 | Clock monitoring circuit and method thereof |
| CN109839838A (en) * | 2017-11-29 | 2019-06-04 | 中国科学院沈阳自动化研究所 | It is synchronized and integrating device of meeting an urgent need from principal mode submersible high-accuracy self-adaptation |
| CN110690894A (en) * | 2019-09-20 | 2020-01-14 | 上海励驰半导体有限公司 | Clock failure safety protection method and circuit |
| CN110690894B (en) * | 2019-09-20 | 2023-05-12 | 上海励驰半导体有限公司 | Clock failure safety protection method and circuit |
| CN111726190A (en) * | 2020-06-18 | 2020-09-29 | 四川艾贝斯科技发展有限公司 | System time calibration method for street lamp control system |
| CN112114616A (en) * | 2020-08-04 | 2020-12-22 | 深圳市宏电技术股份有限公司 | Switching method of real-time clock, electronic equipment and computer storage medium |
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Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| C14 | Grant of patent or utility model | ||
| GR01 | Patent grant | ||
| AV01 | Patent right actively abandoned |
Granted publication date: 20161130 Effective date of abandoning: 20230407 |
|
| AV01 | Patent right actively abandoned |
Granted publication date: 20161130 Effective date of abandoning: 20230407 |
|
| AV01 | Patent right actively abandoned | ||
| AV01 | Patent right actively abandoned |