CN110690894A - Clock failure safety protection method and circuit - Google Patents
Clock failure safety protection method and circuit Download PDFInfo
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- CN110690894A CN110690894A CN201910890101.3A CN201910890101A CN110690894A CN 110690894 A CN110690894 A CN 110690894A CN 201910890101 A CN201910890101 A CN 201910890101A CN 110690894 A CN110690894 A CN 110690894A
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION, OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
- H03L7/00—Automatic control of frequency or phase; Synchronisation
- H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
- H03L7/08—Details of the phase-locked loop
- H03L7/0807—Details of the phase-locked loop concerning mainly a recovery circuit for the reference signal
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F1/00—Details not covered by groups G06F3/00 - G06F13/00 and G06F21/00
- G06F1/04—Generating or distributing clock signals or signals derived directly therefrom
- G06F1/08—Clock generators with changeable or programmable clock frequency
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION, OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
- H03L7/00—Automatic control of frequency or phase; Synchronisation
- H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
- H03L7/08—Details of the phase-locked loop
- H03L7/085—Details of the phase-locked loop concerning mainly the frequency- or phase-detection arrangement including the filtering or amplification of its output signal
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- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
- Y02D—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN INFORMATION AND COMMUNICATION TECHNOLOGIES [ICT], I.E. INFORMATION AND COMMUNICATION TECHNOLOGIES AIMING AT THE REDUCTION OF THEIR OWN ENERGY USE
- Y02D10/00—Energy efficient computing, e.g. low power processors, power management or thermal management
Abstract
A clock failure safety protection method and circuit. The invention is provided with a plurality of clock source detection modules which respectively check different clock sources mutually and calculate the deviation between the clock frequency of the clock source and the clock frequencies of other clock sources; and finally, switching the clock source to stabilize the output of the clock signal when the abnormal indication signal meets the clock source switching condition. Therefore, when the external clock source is abnormal or fails in case of external attack, the system clock signal can be recovered through other clock sources, and the risk of system crash or safety information loss is avoided.
Description
Technical Field
The invention relates to the field of chip safety, in particular to a clock failure safety protection method and a clock failure safety protection circuit.
Background
Most complex SoC chips today have both an internal clock source and an external clock source. The two clock sources may use crystal oscillators or other signal output devices to provide clock signals. The starting time of the internal clock source is short, the precision is poor, the starting time of the external clock source is slow, and the precision is high.
Because the external clock source has very good frequency stability and external interference resistance, most SoC chips use the external clock source as the clock source for stable operation of the chip. However, in order to speed up the system start-up time, most SoC chips use an internal clock source as a clock source when the chip starts up. After the system is started, the running clock source is switched from the internal clock source to the external clock source in a hardware or software mode.
Since systems rely on a clock signal provided by a clock source as a reference, external clock sources are often the target of external attacks. When the system encounters external clock source abnormality or hacker attack in the running process, the external clock source fails, and when the external clock source fails, the system loses the clock source. At this time, if there is no effective way to recover the system clock source, there will be a risk of system crash or loss of security information.
Disclosure of Invention
The invention provides a clock failure safety protection method and a circuit aiming at the defects of the prior art, can find out clock abnormity in time through mutual detection between clock sources, and switches the clock sources when the clocks are abnormal, thereby ensuring the stability and reliability of a system clock. The invention specifically adopts the following technical scheme.
Firstly, in order to achieve the above object, a clock fail-safe protection method is provided, the method is used for a chip system connected with at least two clock sources, and the method comprises the following steps: the at least two clock sources respectively check the deviation between the clock frequency of the clock sources and the clock frequencies of other clock sources; generating an abnormal indication signal corresponding to the deviation when the deviation exceeds a preset range; and switching the clock source when the abnormal indication signal meets the clock source switching condition, and outputting the clock signal of the switched clock source.
Optionally, in the above method for protecting clock failure, the clock source includes at least 2 external clock sources.
Optionally, in the above method for protecting clock failure, the clock source includes an external clock source and an internal clock source.
Optionally, in the above method for protecting clock failure, the step of checking the deviation between the clock frequencies includes: for each external clock source, respectively checking the deviation between the external clock source and the clock frequency of another external clock source by taking the clock frequency of the external clock source as a reference; further comprising: and for the internal clock source, taking the internal clock source as a reference, and respectively checking the deviation between the clock frequencies of each external clock source.
Optionally, in the above method for protecting clock failure, a deviation between the clock frequencies of the two clock sources is obtained by checking according to the following steps: the two clock sources respectively count in each period corresponding to the clock frequency of the two clock sources according to the same rule by taking the clock frequency of the two clock sources as a reference, and the count value is updated; when one of the count values reaches a configuration value, calculating the difference value between the count values obtained by updating the two clock sources respectively; and outputting the difference value between the two counting values as the deviation between the clock frequencies of the two clock sources.
Optionally, in the method for clock failure safety protection, the clock source switching condition includes: an abnormal indication signal obtained by checking a deviation between a clock frequency of one external clock source and a clock frequency of another external clock source is correspondingly consistent with an abnormal indication signal obtained by checking a deviation between clock frequencies of the external clock source with the internal clock source as a reference.
The invention also provides a clock failure safety protection circuit, which comprises: the external clock source detection modules comprise at least 2, each external clock source detection module is correspondingly connected with an external clock source, the external clock source detection modules are mutually connected and check the deviation between the clock frequency of the external clock source connected with the external clock source detection modules and the clock frequencies of the external clock sources connected with other external clock source detection modules, and an abnormal indication signal corresponding to the deviation is generated when the deviation exceeds a preset range; the internal clock source detection modules comprise at least 1, are connected with an internal clock source and each external clock source detection module, and are used for respectively checking the deviation between clock frequencies of each external clock source detection module by taking the connected internal clock source as a reference, and generating an abnormal indication signal corresponding to the deviation when the deviation exceeds a preset range; and the clock source arbitration module is connected with the internal clock source detection module and used for switching the clock source and outputting the clock signal of the switched clock source when the abnormal indication signal meets the clock source switching condition.
Optionally, in the above clock fail-safe protection circuit, each of the external clock source detection module or the internal clock source detection module respectively includes: a counter which counts in each period of the clock source according to a set rule by taking the clock frequency of the clock source connected with the module as a reference; the interactive interface is connected with another external clock source detection module or an internal clock source detection module, outputs a trigger signal to the other external clock source detection module or the internal clock source detection module when the counter starts counting or finishes counting, and triggers the other external clock source detection module or the internal clock source detection module to count; a configuration value comparison module for comparing a difference between a count value of another external clock source detection module or an internal clock source detection module and a configuration value when the count value of the counter reaches the configuration value, the difference being a deviation between clock frequencies of different clock sources; and the interrupt output module generates an abnormal indication signal corresponding to the deviation when the difference value exceeds a preset range.
Optionally, in the above clock fail-safe protection circuit, the interrupt output module further triggers the counter or another external clock source detection module or another internal clock source detection module to restart counting.
Optionally, in the clock failure safety protection circuit, the clock source switching condition is: and the abnormal indication signals corresponding to the external clock source detection modules or the internal clock source detection modules are correspondingly consistent.
Optionally, the clock fail-safe protection circuit further includes a clock switching register, configured to switch an external clock source or an internal clock source according to the abnormal indication signal flag; and the clock source switching circuit is used for switching the signal output by the clock source arbitration module into a corresponding clock signal of an external clock source or an internal clock source according to the clock switching register.
On the basis, the invention also provides a chip system which comprises a chip, wherein the chip is connected with at least 2 clock sources, the clock failure safety protection circuit is connected between the chip and the 2 clock sources, or the clock failure safety protection circuit is integrated in the chip.
Advantageous effects
In the invention, various clock source detection modules respectively check different clock sources mutually and calculate the deviation between the clock frequency of the clock source and the clock frequencies of other clock sources; and finally, switching the clock source to stabilize the output of the clock signal when the abnormal indication signal meets the clock source switching condition. Therefore, when the external clock source is abnormal or fails in case of external attack, the system clock signal can be recovered through other clock sources, and the risk of system crash or safety information loss is avoided.
Particularly, the invention judges whether the clock sources are synchronous or not and whether the deviation between the clock sources is in an acceptable range or not in a mode of mutually counting and comparing the count values. The interface signal of the judging mode is simple, a clock signal or a counting value with a plurality of bits does not need to be transmitted to another detecting module, the operation cost of the judging mode of the clock abnormity is low, the asynchronization among the clocks can be timely known, and the clock source with abnormity is directly determined through calculation so as to be convenient for switching. Moreover, the judgment method has higher flexibility. When the bit width of the counter needs to be changed or the counting mode needs to be changed, the interface signal is not influenced.
The invention can further introduce the internal clock source to carry out further judgment on the basis of mutual check of the external clock source. Therefore, when two external clock sources are both damaged or illegally stopped by a hacker, the system adopting the invention for always-failing protection can still detect the abnormity of the clock according to the internal clock source, thereby solving the risk of stopping the operation of the system.
Additional features and advantages of the invention will be set forth in the description which follows, and in part will be obvious from the description, or may be learned by practice of the invention.
Drawings
The accompanying drawings are included to provide a further understanding of the invention and are incorporated in and constitute a part of this specification, illustrate embodiments of the invention and together with the description serve to explain the principles of the invention and not to limit the invention. In the drawings:
FIG. 1 is a schematic diagram of a clock fail safe protection circuit of the present invention;
FIG. 2 is a schematic diagram of the connection relationship between the clock fail-safe protection circuit and the system on a chip according to the present invention;
FIG. 3 is a schematic diagram of an external clock source detection module or an internal clock source detection module according to the present invention;
fig. 4 is a signal timing diagram of each clock source in the present invention.
Detailed Description
In order to make the purpose and technical solution of the embodiments of the present invention clearer, the technical solution of the embodiments of the present invention will be clearly and completely described below with reference to the drawings of the embodiments of the present invention. It is to be understood that the embodiments described are only a few embodiments of the present invention, and not all embodiments. All other embodiments, which can be derived by a person skilled in the art from the described embodiments of the invention without any inventive step, are within the scope of protection of the invention.
It will be understood by those skilled in the art that, unless otherwise defined, all terms (including technical and scientific terms) used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this invention belongs. It will be further understood that terms, such as those defined in commonly used dictionaries, should be interpreted as having a meaning that is consistent with their meaning in the context of the prior art and will not be interpreted in an idealized or overly formal sense unless expressly so defined herein.
Fig. 1 is a clock fail-safe protection circuit according to the present invention, which is used to detect 2 external clock sources and 1 internal clock source, alarm when any clock source is abnormal, and automatically switch to a normal clock source when the external clock source is abnormal, affects normal operation, or is lost. The realization of the technology can effectively improve the safety and the reliability of the system.
The circuit includes:
the external clock source detection modules comprise at least 2, each external clock source detection module is correspondingly connected with an external clock source, the external clock source detection modules are mutually connected and check the deviation between the clock frequency of the external clock source connected with the external clock source detection modules and the clock frequencies of the external clock sources connected with other external clock source detection modules, and an abnormal indication signal corresponding to the deviation is generated when the deviation exceeds a preset range;
the internal clock source detection modules comprise at least 1, are connected with an internal clock source and each external clock source detection module, and are used for respectively checking the deviation between clock frequencies of each external clock source detection module by taking the connected internal clock source as a reference, and generating an abnormal indication signal corresponding to the deviation when the deviation exceeds a preset range;
and the clock source arbitration module is connected with the internal clock source detection module and used for switching the clock source and outputting the clock signal of the switched clock source when the abnormal indication signal meets the clock source switching condition.
Wherein, the external clock source detection module and the internal clock source detection module respectively check the deviation between the clock frequencies in the following ways: firstly, the two clock sources respectively count in each period corresponding to the self clock frequency according to the same rule by taking the self clock frequency as a reference, and the count value is updated; then, when one of the count values reaches a configuration value, calculating the difference value between the count values obtained by updating the two clock sources respectively, and then restarting counting; and finally, outputting the difference value between the two counting values as the deviation between the clock frequencies of the different clock sources.
The above-described deviation between the clock frequencies can be realized in particular by the circuit shown in fig. 3. The circuit can be applied to any external clock source detection module or the internal clock source detection module, and comprises:
a counter which counts in each period of the clock source according to a set rule by taking the clock frequency of the clock source connected with the module as a reference;
the interactive interface is connected with another external clock source detection module or an internal clock source detection module, outputs a trigger signal to the other external clock source detection module or the internal clock source detection module when the counter starts counting or finishes counting, and triggers the other external clock source detection module or the internal clock source detection module to count;
a configuration value comparison module for comparing a difference between a count value of another external clock source detection module or an internal clock source detection module and a configuration value when the count value of the counter reaches the configuration value, the difference being a deviation between clock frequencies of different clock sources;
and the interrupt output module generates an abnormal indication signal corresponding to the deviation when the difference value exceeds a preset range.
In a more preferred manner, the circuit in fig. 3 may be further connected:
the clock switching register is used for marking that the external clock source or the internal clock source needs to be switched when the abnormal indication signals corresponding to the external clock source detection modules or the internal clock source detection modules are consistent;
and the clock source switching circuit is used for switching the signal output by the clock source arbitration module into a corresponding clock signal of an external clock source or an internal clock source according to the mark stored in the clock switching register.
And the interrupt output module triggers the connected counter or another external clock source detection module or another internal clock source detection module to restart counting while generating the corresponding abnormal indication signal.
The above clock source detection process is described by taking the example that the clock source2 detects the clock source 1. All the judgment criteria in the process are provided by the register which is configured in advance on the left side of the figure 3. Deviation detection process between clock frequencies:
1. after the clock source detection module 2 receives the software enable signal "clock detection enable", it generates a start counting indication signal and starts the internal counter.
2. The clock source detection module 1 takes the rising edge of the starting counting indication signal, starts the internal counter thereof by the rising edge, generates the counting reaching the appointed value when the counting value reaches the configured value and indicates to the clock source detection module 2, and restarts the internal counter thereof.
3. The clock source detection module 2 receives the indication that the count reaches the predetermined value and then takes the rising edge
4. The value of the internal counter is compared with the value appointed by the counter indication to judge the speed of the clock source 1 and the clock source2, and corresponding interrupt and opposite side clock loss indication signals are generated.
5. The internal counter is restarted.
Wherein, the unstable threshold is used to set how much the error of the clock source 1 and the clock source2 exceeds, and the error is abnormal. The comparison stable times configuration value is used for setting the number of times of reporting the abnormity of the clock source 1 and the clock source2 continuously, and the two values can be set according to the requirements of functional safety and flexibility.
The external clock source 1 detects the external clock source2, and the detection processes of the internal clock source to the external clock source 1 and the external clock source detection 2 are all realized by adopting the same mode.
In another mode, referring to fig. 2, in the above circuit, the output terminal of the clock source arbitration module is connected to a Phase Locked Loop (PLL) of the system on chip to provide a stable clock signal for the system on chip. The clock signal is obtained by at least two clock sources respectively and mutually checking the deviation between the clock frequency of the clock source and the clock frequencies of other clock sources, generating an abnormal indication signal corresponding to the deviation when the deviation exceeds a preset range, screening the corresponding clock source when the abnormal indication signal meets the clock source switching condition, and switching the clock sources.
Taking the secondary switching of two external clock sources and 1 internal clock source as an example, in the implementation of fig. 2, the arbitration and the switching of clock sources under any abnormal condition between two external clock sources and one internal clock source are realized by the external clock source detection module 1, the external clock source detection module 2 and the internal clock source detection module 3 in cooperation with the corresponding clock source arbitration module.
The External Clock Source detection module 1 uses the External Clock Source 1 as a reference to check the External Clock Source 2. The External Clock Source detection module 2 checks the External Clock Source 1 with the External Clock Source2 as a reference. The checking process comprises the following steps:
step S101: checking a clock source, namely counting the two external clock source detection modules mutually, comparing the count values, finishing the checking if the deviation of the count values is within a preset range preset by software, and starting the next checking after a period of time; if the deviation of the count value is outside the preset range, the step S102 is carried out;
step S102: and generating an abnormal indication signal, reporting the abnormal indication signal to a CPU of the chip system in an interruption mode, and outputting a clock source detection result to the internal clock source detection module 3.
The INTERNAL CLOCK SOURCE detection module 3 uses the INTERNAL CLOCK SOURCE 2Hz as a reference to simultaneously check the External CLOCK SOURCE 1 and the External CLOCK SOURCE 2. The step flow of the checking comprises the following steps:
step S201: the external Clock Source 1 and the external Clock Source2 are checked with the Internal Clock Source Internal _ Clock _ Source as a reference, counted with each other, and the count values are compared. If the deviation of the count value is within a preset range preset by software, finishing the inspection, and starting the next inspection after a period of time interval; if the deviation of the count value is outside the preset range, the step S202 is executed;
step S202: generating an abnormal indication signal, and simultaneously judging whether the abnormal state corresponding to the abnormal indication signal is consistent with the detection results sent by the external clock source detection module 1 and the external clock source detection module 2;
step S203: according to the judgment result of the step S202, a clock source switching indication signal is generated. For example, when the External Clock Source 1 is lost, the External Clock Source detection module 2 detects that the External Clock Source 1 is lost, and the internal Clock Source detection module 3 detects that the External Clock Source 1 is lost, and then generates the switch indication signal for the External Clock Source 1.
Therefore, the clock source arbitration module arbitrates the chip clock source according to the clock source switching indication signal output by the internal clock source detection module 3, and checks and acquires the current clock source used by the chip. The checking process comprises the following steps:
step S301: and checking the Clock Source, namely checking whether the current Clock Source is an External Clock Source 1, an External Clock Source2 or an Internal Clock Source Internal _ Clock _ Source. Judging whether the current selected clock source clock switching indication signal is in a state needing switching or not;
step S302: and when the switching indication signal indicates that switching is required, driving corresponding hardware to switch clocks.
The above process corresponds to fig. 4. The chip system uses an External Clock Source 1 with consistent or multiple frequency relation or fixed frequency difference or period difference, the External Clock Source2 and an Internal Clock Source Internal _ Clock _ Source to provide Clock signals. In the chip starting process, an Internal _ Clock _ Source is selected as a chip Clock Source at first, and after the chip is started stably, the system can select an external Clock Source 1 as the chip Clock Source.
When the External Clock Source 1 is lost, the External Clock Source detection circuit 2 and the internal Clock Source detection circuit 3 both detect that the External Clock Source 1 is lost, the Clock Source arbitration module judges that the current Clock Source is the External Clock Source 1, and simultaneously receives an External Clock Source 1 switching indication signal output by the internal Clock Source detection module 3 to arbitrate, so that the chip Clock Source is switched from the External Clock Source 1 to the External Clock Source 2. In the switching process, the Selected Functional Clock Source is always used as a Clock signal output port to provide a Clock for units such as a phase-locked loop of the chip and the like for time efficiency control.
It should be noted that, the present invention can also realize similar clock failure protection only according to two external clock sources through the checking and detecting manner between the clock sources. Similarly, an external clock source can be detected through an internal clock source, and similarly, through the synchronous detection process among the clock sources, when the external clock source is attacked and is abnormal, the external clock source is switched to a stable internal clock source, so that the system is prevented from being failed or stuck due to the abnormality of the clock source.
The protection against clock failure can be achieved only by checking the external clock sources with each other, but the reliability is not as high as that of the previous embodiment in which both the internal clock source and the external clock source are used. This is because, in the aforementioned scheme of the internal and external clock sources, there is a double insurance through the interactive detection of the internal clock source and the external clock source, and the automatic switching operation is performed only when the checking result of the external clock source is consistent with the result of the internal clock source.
If only the external clock sources are mutually checked, when the two external clock sources are both broken or illegally stopped by a hacker, the two clock signals cannot be detected because the external clock sources are both invalid, and the detection mechanism between the two clock signals still cannot detect the abnormality because the reference standard used for detection is invalid, so that the risk of stopping the operation of the system cannot be solved.
Meanwhile, it should be understood by those skilled in the art that the manner of detecting the deviation between the clock frequencies of the clock sources in the above embodiments is only a preferred manner selected in consideration of the flexibility of clock verification, the complexity of interface implementation, and other factors. In general, the above-mentioned detection of the deviation between the clock frequencies can also be realized by means of phase-locking techniques, time synchronization, frequency synchronization, phase monitoring, or by means of an additional time alignment signal. However, compared with other methods, the method of comparing clocks by counting each other and transmitting the indication signal of the count to the predetermined value (register configuration value) in the above embodiment still has the following advantages:
1. the interface signal is simple, and it is not necessary to transmit clock signal or many bits of counting value to another detection module (usually, as the chip scale is larger and larger, the positions of the clock detection module may be far apart, the transmission of clock or multi-bit counter is more complex, and the physical realization is relatively difficult)
2. The flexibility is higher, and if the bit width of the counter needs to be changed, or the counting mode is changed, the interface signals cannot be influenced.
The above are merely embodiments of the present invention, which are described in detail and with particularity, and therefore should not be construed as limiting the scope of the invention. It should be noted that, for those skilled in the art, various changes and modifications can be made without departing from the spirit of the present invention, and these changes and modifications are within the scope of the present invention.
Claims (12)
1. A clock fail safe protection method, which is used for a chip system connected with at least two clock sources, and comprises the following steps:
the at least two clock sources respectively check the deviation between the clock frequency of the clock sources and the clock frequencies of other clock sources;
generating an abnormal indication signal corresponding to the deviation when the deviation exceeds a preset range;
and switching the clock source when the abnormal indication signal meets the clock source switching condition, and outputting the clock signal of the switched clock source.
2. The clock fail-safe method of claim 1, wherein the clock source comprises at least 2 external clock sources.
3. The clock fail-safe method of claim 1, wherein the clock source comprises an external clock source and an internal clock source.
4. A method of clock failsafe protection as claimed in claims 2 to 3, wherein the step of checking for deviations between the clock frequencies comprises:
for each external clock source, respectively checking the deviation between the external clock source and the clock frequency of another external clock source by taking the clock frequency of the external clock source as a reference;
further comprising:
and for the internal clock source, taking the internal clock source as a reference, and respectively checking the deviation between the clock frequencies of each external clock source.
5. A method of clock failsafe protection as claimed in claims 1 to 4, characterized in that the deviation between the clock frequencies between two clock sources is obtained by checking in particular the following steps:
the two clock sources respectively count in each period corresponding to the clock frequency of the two clock sources according to the same rule by taking the clock frequency of the two clock sources as a reference, and the count value is updated;
when one of the count values reaches a configuration value, calculating the difference value between the count values obtained by updating the two clock sources respectively;
and outputting the difference value between the two counting values as the deviation between the clock frequencies of the two clock sources.
6. The clock fail safe method of claims 1-5, wherein the clock source switching condition comprises:
an abnormal indication signal obtained by checking a deviation between a clock frequency of one external clock source and a clock frequency of another external clock source is correspondingly consistent with an abnormal indication signal obtained by checking a deviation between clock frequencies of the external clock source with the internal clock source as a reference.
7. A clock fail safe protection circuit, comprising:
the external clock source detection modules comprise at least 2, each external clock source detection module is correspondingly connected with an external clock source, the external clock source detection modules are mutually connected and check the deviation between the clock frequency of the external clock source connected with the external clock source detection modules and the clock frequencies of the external clock sources connected with other external clock source detection modules, and an abnormal indication signal corresponding to the deviation is generated when the deviation exceeds a preset range;
the internal clock source detection modules comprise at least 1, are connected with an internal clock source and each external clock source detection module, and are used for respectively checking the deviation between clock frequencies of each external clock source detection module by taking the connected internal clock source as a reference, and generating an abnormal indication signal corresponding to the deviation when the deviation exceeds a preset range;
and the clock source arbitration module is connected with the internal clock source detection module and used for switching the clock source and outputting the clock signal of the switched clock source when the abnormal indication signal meets the clock source switching condition.
8. The clock fail-safe circuit of claim 7, wherein each of the external clock source detection modules or the internal clock source detection modules comprises:
a counter which counts in each period of the clock source according to a set rule by taking the clock frequency of the clock source connected with the module as a reference;
the interactive interface is connected with another external clock source detection module or an internal clock source detection module, outputs a trigger signal to the other external clock source detection module or the internal clock source detection module when the counter starts counting or finishes counting, and triggers the other external clock source detection module or the internal clock source detection module to count;
a configuration value comparison module for comparing a difference between a count value of another external clock source detection module or an internal clock source detection module and a configuration value when the count value of the counter reaches the configuration value, the difference being a deviation between clock frequencies of different clock sources;
and the interrupt output module generates an abnormal indication signal corresponding to the deviation when the difference value exceeds a preset range.
9. The clock fail safe circuit of claim 7, wherein the interrupt output module further triggers the counter or another external clock source detection module or another internal clock source detection module to restart counting.
10. The clock fail-safe circuit of claim 7, wherein the clock source switching condition is: and the abnormal indication signals corresponding to the external clock source detection modules or the internal clock source detection modules are correspondingly consistent.
11. The clock fail-safe protection circuit of claim 7, further comprising a clock switching register for switching an external clock source or an internal clock source according to the abnormal indication signal flag;
and the clock source switching circuit is used for switching the signal output by the clock source arbitration module into a corresponding clock signal of an external clock source or an internal clock source according to the clock switching register.
12. A chip system comprising a chip, wherein the chip is connected with at least 2 clock sources, and the clock fail-safe protection circuit according to claims 7-11 is connected between the chip and the 2 clock sources, or the clock fail-safe protection circuit according to claims 7-11 is integrated inside the chip.
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| CN112083755A (en) * | 2020-08-10 | 2020-12-15 | 合肥市芯海电子科技有限公司 | Clock control circuit, chip and clock control method |
| CN112114616A (en) * | 2020-08-04 | 2020-12-22 | 深圳市宏电技术股份有限公司 | Switching method of real-time clock, electronic equipment and computer storage medium |
| CN112181047A (en) * | 2020-09-03 | 2021-01-05 | 华帝股份有限公司 | Self-adaptive method based on power grid power frequency clock source |
| CN114637370A (en) * | 2022-03-25 | 2022-06-17 | 北京中科飞鸿科技股份有限公司 | Circuit, device and method for switching internal and external different frequency reference clock signals |
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| CN112114616A (en) * | 2020-08-04 | 2020-12-22 | 深圳市宏电技术股份有限公司 | Switching method of real-time clock, electronic equipment and computer storage medium |
| CN112114616B (en) * | 2020-08-04 | 2022-10-25 | 深圳市宏电技术股份有限公司 | Switching method of real-time clock, electronic equipment and computer storage medium |
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| CN112181047A (en) * | 2020-09-03 | 2021-01-05 | 华帝股份有限公司 | Self-adaptive method based on power grid power frequency clock source |
| CN112181047B (en) * | 2020-09-03 | 2023-08-11 | 华帝股份有限公司 | Self-adaptive method based on power frequency clock source of power grid |
| CN114637370A (en) * | 2022-03-25 | 2022-06-17 | 北京中科飞鸿科技股份有限公司 | Circuit, device and method for switching internal and external different frequency reference clock signals |
| CN114637370B (en) * | 2022-03-25 | 2024-02-20 | 北京中科飞鸿科技股份有限公司 | Internal and external different frequency reference clock signal switching circuit, device and method |
| CN115328267A (en) * | 2022-07-15 | 2022-11-11 | 无锡芯领域微电子有限公司 | Dynamic clock adjusting method and device based on-chip clock comparison |
| CN116722868A (en) * | 2023-08-08 | 2023-09-08 | 苏州浪潮智能科技有限公司 | Clock holding system, method and storage device |
| CN116722868B (en) * | 2023-08-08 | 2023-11-03 | 苏州浪潮智能科技有限公司 | Clock holding system, method and storage device |
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