CN116722868A - Clock holding system, method and storage device - Google Patents
Clock holding system, method and storage device Download PDFInfo
- Publication number
- CN116722868A CN116722868A CN202310993732.4A CN202310993732A CN116722868A CN 116722868 A CN116722868 A CN 116722868A CN 202310993732 A CN202310993732 A CN 202310993732A CN 116722868 A CN116722868 A CN 116722868A
- Authority
- CN
- China
- Prior art keywords
- clock
- clock signal
- power
- signal
- down protection
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
- 238000000034 method Methods 0.000 title claims abstract description 24
- 239000013078 crystal Substances 0.000 claims abstract description 51
- 238000001514 detection method Methods 0.000 claims abstract description 44
- 230000004044 response Effects 0.000 claims description 38
- 230000000630 rising effect Effects 0.000 claims description 31
- 230000002159 abnormal effect Effects 0.000 claims description 14
- 230000014759 maintenance of location Effects 0.000 claims description 8
- 239000003990 capacitor Substances 0.000 claims description 5
- 230000010355 oscillation Effects 0.000 claims description 4
- 239000007787 solid Substances 0.000 claims description 4
- 230000005856 abnormality Effects 0.000 claims description 3
- 238000005516 engineering process Methods 0.000 abstract description 2
- 238000012423 maintenance Methods 0.000 abstract 1
- 101100003180 Colletotrichum lindemuthianum ATG1 gene Proteins 0.000 description 10
- 101100113692 Caenorhabditis elegans clk-2 gene Proteins 0.000 description 8
- 238000010586 diagram Methods 0.000 description 5
- 238000013461 design Methods 0.000 description 4
- 230000008569 process Effects 0.000 description 4
- 230000000694 effects Effects 0.000 description 2
- 238000000605 extraction Methods 0.000 description 2
- 230000014509 gene expression Effects 0.000 description 2
- 230000006872 improvement Effects 0.000 description 2
- 238000013459 approach Methods 0.000 description 1
- 230000009286 beneficial effect Effects 0.000 description 1
- 230000008859 change Effects 0.000 description 1
- 238000004519 manufacturing process Methods 0.000 description 1
- 230000007246 mechanism Effects 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 238000012545 processing Methods 0.000 description 1
- 239000010453 quartz Substances 0.000 description 1
- 238000012827 research and development Methods 0.000 description 1
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N silicon dioxide Inorganic materials O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 1
- 230000001360 synchronised effect Effects 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
- H03L7/00—Automatic control of frequency or phase; Synchronisation
- H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
- H03L7/08—Details of the phase-locked loop
- H03L7/14—Details of the phase-locked loop for assuring constant frequency when supply or correction voltages fail or are interrupted
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F1/00—Details not covered by groups G06F3/00 - G06F13/00 and G06F21/00
- G06F1/04—Generating or distributing clock signals or signals derived directly therefrom
- G06F1/14—Time supervision arrangements, e.g. real time clock
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
- H03L2207/00—Indexing scheme relating to automatic control of frequency or phase and to synchronisation
- H03L2207/08—Modifications of the phase-locked loop for ensuring constant frequency when the power supply fails or is interrupted, e.g. for saving power
-
- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
- Y02D—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN INFORMATION AND COMMUNICATION TECHNOLOGIES [ICT], I.E. INFORMATION AND COMMUNICATION TECHNOLOGIES AIMING AT THE REDUCTION OF THEIR OWN ENERGY USE
- Y02D10/00—Energy efficient computing, e.g. low power processors, power management or thermal management
Landscapes
- Engineering & Computer Science (AREA)
- Theoretical Computer Science (AREA)
- Physics & Mathematics (AREA)
- General Engineering & Computer Science (AREA)
- General Physics & Mathematics (AREA)
- Stabilization Of Oscillater, Synchronisation, Frequency Synthesizers (AREA)
Abstract
The present application relates to the field of computer technologies, and in particular, to a clock holding system, a clock holding method, and a storage device. The system comprises: a first clock signal generated by the motherboard; a second clock signal generated by the crystal oscillator; a power-down protection chip; the two input ends of the clock control unit are respectively connected with the first clock signal and the second clock signal, the clock control unit is used for detecting the first clock signal to generate a detection result, selecting one of the first clock signal and the second clock signal as a target clock input according to the detection result, and providing a third clock signal for the power-down protection chip based on the target clock input. The scheme of the application does not depend on the detection of the power-down state of the power supply any more, remarkably improves the timeliness of clock maintenance, is suitable for various memory devices with power-down protection functions, and has better universality.
Description
Technical Field
The present application relates to the field of computer technologies, and in particular, to a clock holding system, a clock holding method, and a storage device.
Background
In the design of server products, power-down protection is an important characteristic, when power supply of storage equipment (such as a disk array Redundant Array of Independent Disks, abbreviated as RAID card) in a server is in surge or power failure under an emergency, the power-down protection function can ensure that data is not lost, and ensure the safety and reliability of the data. The data protection function of the RAID card is realized by ROC chip scheduling, and the data in the volatile cache is transported to a nonvolatile NAND medium after power failure occurs, so that the power failure protection function of the ROC chip must be ensured to work normally when power failure occurs, the phenomenon of hanging the chip is avoided, and the data is influenced to be brushed out of the NAND. Actually, when the RAID card is powered down, the PCIe clock provided by the server side is lost, if the reference clock at the PCIe EP (End Point) End of the ROC (RAID On Chip) Chip at the RAID card side cannot be provided in time, the EP internal phase locked loop is unlocked, the response is overtime, and then the internal interconnection bus of the Chip is locked, and finally the ROC is suspended.
Currently, clock signal retention of a conventional power-down protection chip is realized through a Multiplexer (MUX), however, the MUX switching scheme is suitable for PCIe EP IP (Intellectual Property core ) with low requirements on clock continuity and low real-time performance, and thus, improvement is needed.
Disclosure of Invention
In view of the foregoing, it is desirable to provide a clock holding system, a clock holding method, and a memory device.
According to a first aspect of the present application, there is provided a clock-keeping system, the system comprising,
a first clock signal generated by the motherboard;
a second clock signal generated by the crystal oscillator;
a power-down protection chip;
the two input ends of the clock control unit are respectively connected with the first clock signal and the second clock signal, the clock control unit is used for detecting the first clock signal to generate a detection result, selecting one of the first clock signal and the second clock signal as a target clock input according to the detection result, and providing a third clock signal for the power-down protection chip based on the target clock input.
In some embodiments, the crystal oscillator includes a voltage controlled crystal oscillator, and an output terminal of the voltage controlled crystal oscillator outputs the second clock signal.
In some embodiments, the clock control unit comprises an analog phase locked loop;
the two input ends of the analog phase-locked loop are respectively connected with the output end of the first clock signal and the output end of the second clock signal, the analog phase-locked loop comprises a first output end, a second output end, a third output end and a fourth output end, the first output end, the second output end and the third output end are all connected with PCIe endpoints of the power-down protection chip, and the fourth output end is connected with the voltage driving end of the voltage-controlled crystal oscillator;
the first output end is used for outputting the third clock signal, the second output end is used for outputting a locking state signal, the third output end is used for outputting the clock state signal, and the fourth output end is used for outputting a driving voltage generated by a phase discrimination filter in the analog phase-locked loop.
In some embodiments, the analog phase-locked loop is configured to:
outputting an unlocked signal to a PCIe endpoint of the power-down protection chip through the second output terminal in response to the locking of the first clock signal is not completed;
and in response to the locking of the first clock signal, outputting the third clock signal by taking the first clock signal as a current clock source, and outputting a locking signal to a PCIe endpoint of the power-down protection chip through the second output end.
In some embodiments, the analog phase-locked loop is further configured to:
in response to completion of a PCIe connection with a PCIe endpoint of the power down protection chip, continuously detecting the first clock signal to determine whether the first clock signal is abnormal;
and responding to the first clock signal abnormality, diagnosing unlocking and entering a free oscillation mode to take the second clock signal as a current clock source to output the third clock signal, and respectively outputting an unlocking signal and a clock losing signal to a PCIe endpoint of the power-down protection chip through the second output end and the third output end.
In some embodiments, the analog phase-locked loop is further configured to:
and responding to the second clock signal as a current clock source to output the third clock signal, performing secondary locking on the second clock signal, and outputting a locking signal to a PCIe endpoint of the power-down protection chip through the second output terminal again after the execution of the secondary locking is completed.
In some embodiments, the power down protection chip is configured to:
responding to the existence of unlocked signal input, and enabling a phase-locked loop in the PCIe endpoint not to respond to the third clock signal currently output by the first output end;
responding to the existence of locking signal input, and enabling a phase-locked loop in the PCIe endpoint to execute a phase-locked flow;
and in response to the phase-locked loop in the PCIe endpoint being currently locked and the clock losing signal input exists, the phase-locked loop in the PCIe endpoint is unlocked.
In some embodiments, the power down protection chip is further configured to:
in response to the presence of a clock loss signal input, a power-down protection procedure is performed.
In some embodiments, the analog phase-locked loop is further configured to:
in response to the first clock signal currently having a rising edge, continuously judging whether the time difference between the current rising edge and the previous rising edge exceeds a first time threshold;
determining that the first clock signal is normal in response to the time difference between the current rising edge and the previous rising edge not exceeding a first time threshold;
in response to the time difference between the current rising edge and the previous rising edge exceeding a first time threshold, a first clock signal anomaly is determined.
In some embodiments, the analog phase-locked loop is further configured to:
in response to the first clock signal not having a rising edge at present, determining whether a difference between a current time and a time generated by a last rising edge exceeds a second time threshold;
in response to the difference between the current time and the time of generation of the last rising edge exceeding a second time threshold, the first clock signal is confirmed as abnormal.
In some embodiments, the clock control unit includes a clock signal detection unit and a multiplexer;
the first clock signal and the second clock signal are respectively input to two input ends of the multiplexer, and the output end of the multiplexer is connected with the power-down protection chip;
the clock signal detection unit is used for detecting the first clock signal to determine whether the first clock signal is abnormal or not, and outputting a gating signal to the multiplexer according to a detection result of whether the first clock signal is normal or not.
In some embodiments, the clock signal detection unit is configured to;
outputting a gating control signal for gating the first clock signal in response to the first clock signal being normal;
outputting a gating control signal for gating the second clock signal in response to the first clock signal being abnormal.
In some embodiments, the power down protection chip is configured to:
and responding to the multiplexer to gate the second clock signal to be input to the power-down protection chip, and executing a power-down protection flow.
In some embodiments, the system further comprises a supercapacitor;
the super capacitor is used for supplying power to the power-down protection chip, the crystal oscillator and the clock control unit when the power-down protection chip executes a power-down protection flow.
In some embodiments, the system further comprises: a micro control unit;
the micro control unit is connected with the analog phase-locked loop and is used for writing the analog phase-locked loop register after the power-down protection chip is powered up to configure the working parameters of the analog phase-locked loop.
In some embodiments, the power-down protection chip is used for protecting data of a storage device, where the storage device is selected from any one of a disk array card, a solid state disk, and a mechanical hard disk.
In some embodiments, the crystal oscillator and the clock control unit are integrated on a board of the memory device.
In some embodiments, the plurality of storage devices are provided, and the crystal oscillator and the clock control unit are mounted to any one of the plurality of storage devices in a plug-in manner.
According to a second aspect of the present application, there is provided a clock holding method, the method comprising:
connecting a first clock signal generated by a main board to one input end of a clock control unit;
connecting a second clock signal generated by the crystal oscillator to the other input end of the clock control unit;
detecting the first clock signal by using the clock control unit to generate a detection result, and selecting one of the first clock signal and the second clock signal as a target clock input according to the detection result;
and providing a third clock signal for the power-down protection chip based on the target clock input.
According to a third aspect of the present application, there is provided a storage device comprising:
a power-down protection chip;
the clock control unit is used for detecting the first clock signal to generate a detection result, selecting one of the first clock signal and the second clock signal as a target clock input according to the detection result, and providing a third clock signal for the power-down protection chip based on the target clock input.
According to the clock holding system, the first clock signal and the second clock signal are respectively provided through the main board and the crystal oscillator, the first clock signal is detected by the clock control unit, one of the first clock signal and the second clock signal is selected as the target clock input according to the detection result so as to provide the third clock signal for the power-down protection chip.
In addition, the application also provides a clock holding method and a storage device, which can also achieve the technical effects, and are not repeated here.
Drawings
In order to more clearly illustrate the embodiments of the application or the technical solutions in the prior art, the drawings that are necessary for the description of the embodiments or the prior art will be briefly described, it being obvious that the drawings in the following description are only some embodiments of the application and that other embodiments may be obtained according to these drawings without inventive effort for a person skilled in the art.
FIG. 1 is a schematic diagram of a clock holding system according to an embodiment of the present application;
FIG. 2 is a schematic diagram of a conventional multiplexer switching clock source holding clock scheme;
FIG. 3 is a schematic diagram of a clock holding system based on an analog phase locked loop according to another embodiment of the present application;
FIG. 4 is a schematic diagram of a multiplexer-based clock holding system according to another embodiment of the present application;
fig. 5 is a schematic flow chart of implementing a clock hold function of an analog phase-locked loop according to an embodiment of the present application;
FIG. 6 is a flowchart of a clock holding method according to an embodiment of the present application;
fig. 7 is a schematic structural diagram of a memory device according to an embodiment of the present application.
Detailed Description
In order to make the objects, technical solutions and advantages of the present application more apparent, the following embodiments of the present application will be described in further detail with reference to the accompanying drawings.
It should be noted that, in the embodiments of the present application, all the expressions "first" and "second" are used to distinguish two entities with the same name but different entities or different parameters, and it is noted that the "first" and "second" are only used for convenience of expression, and should not be construed as limiting the embodiments of the present application, and the following embodiments are not described one by one.
In one embodiment, referring to FIG. 1, the present application provides a clock-keeping system 100, specifically, the system comprises:
a first clock signal clk1 generated by the main board 110;
in this embodiment, the motherboard, also called a motherboard (main board), a system board (system board), or a motherboard (atherboard), is one of the most basic and important components of the computer. The motherboard is generally a rectangular circuit board on which the main circuitry that makes up the computer is mounted, and typically has elements such as a BIOS chip, an I/O control chip, a keyboard and panel control switch interface, an indicator light connector, an expansion slot, a direct current power supply connector for the motherboard and the card. The main board 110 may be a main board of a personal notebook, a main board of a desktop, a main board of a terminal capable of recognizing and using a memory device, a main board of a server, etc., and a main board of a server is taken as an example for the convenience of understanding the present application.
A second clock signal clk2 generated by the crystal oscillator 120;
in this embodiment, the crystal oscillator 130 is simply referred to as a crystal oscillator, and refers to an oscillator using quartz crystal, and the crystal oscillator 130 may be selected from existing crystal oscillator products.
A power-down protection chip 130;
in this embodiment, the power-down protection is a special way of protecting data, which means that all data will be stored on the disk all the time when power is down and not deleted until the reconstruction is completed. The power-down protection chip 130 in this embodiment may be a power-down protection device on an existing RAID card, a solid state disk, or a mechanical hard disk.
The clock control unit 140, the first clock signal clk1 and the second clock signal clk2 are connected to the clock control unit 140, the clock control unit 140 is configured to detect the first clock signal clk1 to generate a detection result, select one of the first clock signal clk1 and the second clock signal clk2 as a target clock input according to the detection result, and provide the third clock signal clk3 to the power-down protection chip 130 based on the target clock input.
In this embodiment, detecting the first clock signal means detecting whether the first clock signal is normal, and the detection guarantee of the normal clock signal includes, but is not limited to, that the clock signal exists, that the signal frequency meets a preset requirement, and that the corresponding detection result includes normal signal and abnormal signal; specifically, the first clock signal clk1 is input as the target clock when the detection result indicates that the first clock signal is normal, and the second clock signal clk2 is input as the target clock when the detection result indicates that the first clock signal is abnormal.
In order to facilitate understanding of the improvement of the scheme of the present application with respect to the prior art, the implementation of the clock scheme when the conventional multiplexer switches clock sources for maintaining is described in detail below, and as shown in fig. 2, a RAID card may be taken as an example, and it is assumed that the RAID card is inserted on a server motherboard, in order to enable an EP end clock of a power-down protection chip on the RAID card to be timely supplied after power-down, a common practice is to simultaneously access a common clk clock of a server and a local 100M crystal oscillator, select one of the two clocks to supply EP by using a MUX, and when power-down is detected, the hardware automatically switches the MUX to the local 100M crystal oscillator. Although this approach can achieve that the 100M clock of the ROC EP has external input after power down; however, in the method, the switching of the MUX depends on the power-down state of the power supply, so that the requirement on the power-down detection threshold value of the power supply is higher, the real-time performance of the switching can be influenced by the excessively high or excessively low setting, in addition, in the power-down process, the external common clk clock can be lost earlier than the power supply, and the detection power supply is selected instead of the clock, so that the detection time delay can influence the detection time efficiency; the scheme of hardware MUX switching is selected, the external common clk is switched to the local clk to generate serious phase jump, the external common clk can be regarded as two different clock inputs, the reference clock is unstable for the phase-locked loop in the EP, and a larger bandwidth is required to track the drift of the reference clock, so that the requirement on the quick locking capability of the phase-locked loop in the EP is extremely high, and otherwise, the phase-locked loop in the EP has the risk of losing lock.
According to the clock holding system, the first clock signal and the second clock signal are respectively provided through the main board 110 and the crystal oscillator 120, the first clock signal is detected by the clock control unit 140, one of the first clock signal and the second clock signal is selected as a target clock input according to a detection result to provide the third clock signal clk3 for the power-down protection chip 130, compared with a clock scheme when a traditional multiplexer switches clock sources for holding, the scheme of the application does not depend on power-down state detection any more, the timeliness of clock holding is remarkably improved, the clock holding system is suitable for various storage devices with a power-down protection function, and the clock holding system has good universality.
In some embodiments, in order to facilitate understanding of the solution of the present application, a clock holding system is implemented based on an analog phase-locked loop, and referring to fig. 3, in this embodiment, a scenario in which a RAID card 220 is connected to a server 210 is taken as an example, the server 210 has a motherboard, a first clock signal generated by using the motherboard is denoted as common CLK, a power-down protection chip in this embodiment is denoted as an on-chip RAID chip 221 in the RAID card 220, a crystal oscillator specifically refers to a voltage-controlled crystal oscillator 230 in this embodiment, and an output terminal of the voltage-controlled crystal oscillator 230 outputs the second clock signal and is denoted as CLK OUT in this embodiment, where the voltage-controlled crystal oscillator is referred to as a voltage-controlled crystal oscillator, and is also referred to as a VCXO.
In some embodiments, as shown in fig. 3, the clock control unit 140 includes an analog phase-locked loop 240; the analog pll 240 mainly comprises a phase reference extraction circuit, a voltage-controlled oscillator, a phase comparator, a control circuit, and the like. The voltage-controlled oscillator outputs a constant-amplitude signal which is very close to the required frequency, the constant-amplitude signal and a reference signal extracted from the signal by the phase reference extraction circuit are simultaneously sent into the phase comparator, and the error formed by comparison is used for continuously changing the frequency of the voltage-controlled oscillator to the direction of reducing the absolute value of the error through the control circuit, so that phase locking is realized, and the synchronization is realized;
the two input ends of the analog phase-locked loop 240 are respectively connected with the output end of the first clock signal common CLK and the output end of the second clock signal CLK OUT, the analog phase-locked loop 240 comprises a first output end, a second output end, a third output end and a fourth output end, the first output end, the second output end and the third output end are all connected with PCIe endpoints of the power-down protection chip 221, and the fourth output end is connected with a voltage driving end of the voltage-controlled crystal oscillator 230;
the first output terminal is used for outputting the third clock signal (CLK in fig. 3), the second output terminal is used for outputting a lock state signal, the third output terminal is used for outputting a clock state signal, and the fourth output terminal is used for outputting a driving voltage generated by a phase discrimination filter inside the analog phase-locked loop.
In the implementation process, the first connector 270 may be configured to connect the analog pll 240 to the server 210, and the first connector 280 may be configured to connect the analog pll 240 to the power-down protection chip 221.
In some embodiments, the analog phase-locked loop 240 is configured to:
outputting an unlocked signal to a PCIe endpoint of the power-down protection chip through the second output terminal in response to the locking of the first clock signal is not completed;
and in response to the locking of the first clock signal, outputting the third clock signal by taking the first clock signal as a current clock source, and outputting a locking signal to a PCIe endpoint of the power-down protection chip through the second output end.
In some embodiments, the analog phase-locked loop 240 is further configured to:
in response to completion of a PCIe connection with a PCIe endpoint of the power down protection chip, continuously detecting the first clock signal to determine whether the first clock signal is abnormal;
and responding to the first clock signal abnormality, diagnosing unlocking and entering a free oscillation mode to take the second clock signal as a current clock source to output the third clock signal, and respectively outputting an unlocking signal and a clock losing signal to a PCIe endpoint of the power-down protection chip through the second output end and the third output end.
In some embodiments, the analog phase-locked loop 240 is further configured to:
and responding to the second clock signal as a current clock source to output the third clock signal, performing secondary locking on the second clock signal, and outputting a locking signal to a PCIe endpoint of the power-down protection chip through the second output terminal again after the execution of the secondary locking is completed.
In some embodiments, the power down protection chip 221 is configured to:
responding to the existence of unlocked signal input, and enabling a phase-locked loop in the PCIe endpoint not to respond to the third clock signal currently output by the first output end;
responding to the existence of locking signal input, and enabling a phase-locked loop in the PCIe endpoint to execute a phase-locked flow;
and in response to the phase-locked loop in the PCIe endpoint being currently locked and the clock losing signal input exists, the phase-locked loop in the PCIe endpoint is unlocked.
In some embodiments, the power down protection chip 221 is further configured to:
in response to the presence of a clock loss signal input, a power-down protection procedure is performed.
In some embodiments, the analog phase-locked loop 240 is further configured to:
in response to the first clock signal currently having a rising edge, continuously judging whether the time difference between the current rising edge and the previous rising edge exceeds a first time threshold;
determining that the first clock signal is normal in response to the time difference between the current rising edge and the previous rising edge not exceeding a first time threshold;
in response to the time difference between the current rising edge and the previous rising edge exceeding a first time threshold, a first clock signal anomaly is determined.
In some embodiments, the analog phase-locked loop 240 is further configured to:
in response to the first clock signal not having a rising edge at present, determining whether a difference between a current time and a time generated by a last rising edge exceeds a second time threshold;
in response to the difference between the current time and the time of generation of the last rising edge exceeding a second time threshold, the first clock signal is confirmed as abnormal.
In some embodiments, in order to facilitate understanding of the solution of the present application, a clock holding system is implemented based on a multiplexer, and referring to fig. 4, in this embodiment, a scenario in which a RAID card is connected to a server is also taken as an example, in this embodiment, the server is denoted as 310, the RAID card is denoted as 320, a motherboard of the server 310 can generate a first clock signal denoted as clk, in this embodiment, a power-down protection chip is denoted as an on-chip RAID chip denoted as 321 in the RAID card 220, a crystal oscillator uses a 100M local crystal oscillator denoted as 330 in this embodiment, and the 100M local crystal oscillator 330 outputs a clock signal denoted as clk2, which is different from the foregoing embodiment, in that the clock control unit 140 includes a clock signal detecting unit 341 and a multiplexer 342;
the first clock signal clk1 and the second clock signal clk2 are respectively input to two input ends of the multiplexer 342, and an output end of the multiplexer 342 is connected with the power-down protection chip 321;
the clock signal detecting unit 341 is configured to detect the first clock signal clk1 to determine whether the first clock signal is abnormal, and output a strobe signal to the multiplexer 342 according to a detection result of whether the first clock signal is normal.
In some embodiments, the clock signal detection unit 341 is configured to;
outputting a gate control signal for gating the first clock signal clk1 in response to the first clock signal clk1 being normal;
in response to the first clock signal clk1 being abnormal, a gate control signal that gates the second clock signal clk2 is output.
In some embodiments, the power-down protection chip 321 is configured to:
in response to the multiplexer 342 gating the second clock signal clk2 for input to the power down protection chip 321, a power down protection process is performed.
In some embodiments, referring again to fig. 3, the system further comprises a supercapacitor 250;
the super capacitor 250 is configured to supply power to the power-down protection chip 221, the crystal oscillator 230, and the clock control unit 240 when the power-down protection chip 221 performs a power-down protection process.
In some embodiments, referring again to fig. 3, the system further comprises: a micro control unit 260; wherein, the micro control unit is Microcontroller Unit, called MCU for short, also called single chip microcomputer (Single Chip Microcomputer) or single chip microcomputer
The micro-control unit 260 is connected to the analog pll 240, and is configured to write an analog pll register to configure the operating parameters of the analog pll after the power-down protection chip 221 is powered up.
In some embodiments, the power-down protection chip is used for protecting data of a storage device, where the storage device is selected from any one of a disk array card, a solid state disk, and a mechanical hard disk.
In some embodiments, the crystal oscillator and the clock control unit are integrated on a board of the memory device.
In the embodiment, the design that the crystal oscillator and the clock control unit are integrated on the storage device is more suitable for the scene of mass production of storage products, so that the crystal oscillator and the clock control unit can be shared by a plurality of storage devices, and the crystal oscillator and clock control unit has better universality.
In some embodiments, the plurality of storage devices are provided, and the crystal oscillator and the clock control unit are mounted to any one of the plurality of storage devices in a plug-in manner.
In the embodiment, the design of the crystal oscillator and the clock control unit which are hung on the storage device is more suitable for the scene of debugging of storage products, and the design of different types of storage device designers does not need to be independently developed, so that the crystal oscillator and clock control unit has better universality and reduces the research and development cost.
In still another embodiment, in order to provide a clock holding system with a clock holding function after accidental power failure of a RAID card, referring to fig. 3, the system mainly includes: the PICE EP of the on-chip RAID (ROC) 221 in the RAID card 220 is provided through the second connector 280 after the PICE EP is sent to the analog phase-locked loop 240 for processing. The analog phase-locked loop 240 and the voltage-controlled crystal oscillator 230 form a clock phase-locked loop to realize a clock holding function, the micro control unit 260 issues configuration information to the analog phase-locked loop through an SPI or I2C interface, the analog phase-locked loop 240 generates an interrupt signal after clock loss through the second connector 28, the super capacitor 250 is used as a standby power supply for the operation of the analog phase-locked loop 240, and the micro control unit 260 is used as a controller of the analog phase-locked loop 240 to realize the configuration of the working mode.
The operation of the system is described in detail below with reference to fig. 5:
step one, after the RAID card 220 is powered on, the micro control unit 260 completes the actions of starting and writing the analog pll 240 register within 5ms, and the configuration interface can select SPI or I2C;
step two, before the analog pll 240 does not enter the locked state, an unlock signal is output to the ROC221, and the EP of the ROC221 will not respond to the input clock in this period;
step three, after the analog pll 240 completes locking the common clk input to the server 210, the output clock will keep synchronous with the common clk, and meanwhile, the analog pll outputs a lock signal to the ROC221, the pll in the ROC EP completes locking, and then enters the normal PCIe link phase;
step four, when unexpected power failure occurs, the analog phase-locked loop 240 detects the rising edge change condition of the input reference clock common clk, and after the LOSS of lock is determined, the analog phase-locked loop 240 enters a free oscillation mode, and the voltage-controlled crystal oscillator 230 is used as a clock source to provide the clock source to the analog phase-locked loop 240, and the analog phase-locked loop 240 synchronously generates a clock LOSS signal to the ROC EP to trigger the ROC EP internal protection mechanism.
Step five, the ROC EP receives the phase continuity clock output by the analog pll 240, and completes the locking and subsequent protection actions of the internal pll, and the ROC core is not affected to complete the normal data protection flow.
The clock holding system of the embodiment has the following beneficial technical effects: (1) The clock loss is directly detected, and the method has the characteristics of instantaneity and small delay time; (2) The real clock holding function is realized, the consistency of the frequency and the phase of the clock before and after the power failure occurs is maintained, and the requirement on the quick locking capability of the EP internal analog phase-locked loop is low; (3) The method is not only suitable for RAID cards, but also suitable for SSD and other hot plug components needing power-down protection, and has good universality; (4) The micro control unit is responsible for the configuration of the analog phase-locked loop, so that the configuration of the analog phase-locked loop is decoupled from the ROC, the configuration information is rapidly issued after the power-on, and the complexity of ROC firmware is reduced;
in some embodiments, referring to fig. 6, the present application further provides a clock holding method 400, which includes:
step 401, connecting a first clock signal generated by a motherboard to an input terminal of a clock control unit;
step 402, connecting a second clock signal generated by the crystal oscillator to the other input end of the clock control unit;
step 403, detecting the first clock signal by using the clock control unit to generate a detection result, and selecting one of the first clock signal and the second clock signal as a target clock input according to the detection result;
step 404 provides a third clock signal for the power down protection chip based on the target clock input.
According to the clock holding method, the first clock signal and the second clock signal are respectively provided through the main board and the crystal oscillator, the first clock signal is detected by the clock control unit, one of the first clock signal and the second clock signal is selected as the target clock input according to the detection result so as to provide the third clock signal for the power-down protection chip.
It should be noted that, the specific limitation of the clock holding method may be referred to the limitation of the clock holding system hereinabove, and will not be described herein.
In accordance with yet another aspect of the present application, referring to fig. 7, the present application further provides a storage device 500, including:
a power-down protection chip;
the clock control unit is used for detecting the first clock signal to generate a detection result, selecting one of the first clock signal and the second clock signal as a target clock input according to the detection result, and providing a third clock signal for the power-down protection chip based on the target clock input.
According to the storage device, the first clock signal and the second clock signal are respectively provided through the main board and the crystal oscillator, the first clock signal is detected by the clock control unit, one of the first clock signal and the second clock signal is selected as the target clock input according to the detection result so as to provide the third clock signal for the power-down protection chip.
It should be noted that, the specific limitation of the storage device may be referred to as the limitation of the clock holding system hereinabove, and will not be described herein.
The technical features of the above embodiments may be arbitrarily combined, and all possible combinations of the technical features in the above embodiments are not described for brevity of description, however, as long as there is no contradiction between the combinations of the technical features, they should be considered as the scope of the description.
The above examples illustrate only a few embodiments of the application, which are described in detail and are not to be construed as limiting the scope of the application. It should be noted that it will be apparent to those skilled in the art that several variations and modifications can be made without departing from the spirit of the application, which are all within the scope of the application. Accordingly, the scope of protection of the present application is to be determined by the appended claims.
Claims (20)
1. A clock retention system, the system comprising:
a first clock signal generated by the motherboard;
a second clock signal generated by the crystal oscillator;
a power-down protection chip;
the two input ends of the clock control unit are respectively connected with the first clock signal and the second clock signal, the clock control unit is used for detecting the first clock signal to generate a detection result, selecting one of the first clock signal and the second clock signal as a target clock input according to the detection result, and providing a third clock signal for the power-down protection chip based on the target clock input.
2. The clock holding system of claim 1, wherein the crystal oscillator comprises a voltage controlled crystal oscillator, an output of the voltage controlled crystal oscillator outputting the second clock signal.
3. The clock retention system of claim 2, wherein the clock control unit comprises an analog phase locked loop;
the two input ends of the analog phase-locked loop are respectively connected with the output end of the first clock signal and the output end of the second clock signal, the analog phase-locked loop comprises a first output end, a second output end, a third output end and a fourth output end, the first output end, the second output end and the third output end are all connected with PCIe endpoints of the power-down protection chip, and the fourth output end is connected with the voltage driving end of the voltage-controlled crystal oscillator;
the first output end is used for outputting the third clock signal, the second output end is used for outputting a locking state signal, the third output end is used for outputting the clock state signal, and the fourth output end is used for outputting a driving voltage generated by a phase discrimination filter in the analog phase-locked loop.
4. A clock-keeping system according to claim 3, wherein the analog phase-locked loop is configured to:
outputting an unlocked signal to a PCIe endpoint of the power-down protection chip through the second output terminal in response to the locking of the first clock signal is not completed;
and in response to the locking of the first clock signal, outputting the third clock signal by taking the first clock signal as a current clock source, and outputting a locking signal to a PCIe endpoint of the power-down protection chip through the second output end.
5. The clock-holding system of claim 4, wherein the analog phase-locked loop is further configured to:
in response to completion of a PCIe connection with a PCIe endpoint of the power down protection chip, continuously detecting the first clock signal to determine whether the first clock signal is abnormal;
and responding to the first clock signal abnormality, diagnosing unlocking and entering a free oscillation mode to take the second clock signal as a current clock source to output the third clock signal, and respectively outputting an unlocking signal and a clock losing signal to a PCIe endpoint of the power-down protection chip through the second output end and the third output end.
6. The clock-holding system of claim 5, wherein the analog phase-locked loop is further configured to:
and responding to the second clock signal as a current clock source to output the third clock signal, performing secondary locking on the second clock signal, and outputting a locking signal to a PCIe endpoint of the power-down protection chip through the second output terminal again after the execution of the secondary locking is completed.
7. The clock retention system of claim 6, wherein the power-down protection chip is configured to:
responding to the existence of unlocked signal input, and enabling a phase-locked loop in the PCIe endpoint not to respond to the third clock signal currently output by the first output end;
responding to the existence of locking signal input, and enabling a phase-locked loop in the PCIe endpoint to execute a phase-locked flow;
and in response to the phase-locked loop in the PCIe endpoint being currently locked and the clock losing signal input exists, the phase-locked loop in the PCIe endpoint is unlocked.
8. The clock retention system of claim 6, wherein the power-down protection chip is further configured to:
in response to the presence of a clock loss signal input, a power-down protection procedure is performed.
9. The clock-holding system of claim 5, wherein the analog phase-locked loop is further configured to:
in response to the first clock signal currently having a rising edge, continuously judging whether the time difference between the current rising edge and the previous rising edge exceeds a first time threshold;
determining that the first clock signal is normal in response to the time difference between the current rising edge and the previous rising edge not exceeding a first time threshold;
in response to the time difference between the current rising edge and the previous rising edge exceeding a first time threshold, a first clock signal anomaly is determined.
10. The clock-holding system of claim 9, wherein the analog phase-locked loop is further configured to:
in response to the first clock signal not having a rising edge at present, determining whether a difference between a current time and a time generated by a last rising edge exceeds a second time threshold;
in response to the difference between the current time and the time of generation of the last rising edge exceeding a second time threshold, the first clock signal is confirmed as abnormal.
11. The clock holding system according to claim 1, wherein the clock control unit includes a clock signal detection unit and a multiplexer;
the first clock signal and the second clock signal are respectively input to two input ends of the multiplexer, and the output end of the multiplexer is connected with the power-down protection chip;
the clock signal detection unit is used for detecting the first clock signal to determine whether the first clock signal is abnormal or not, and outputting a gating signal to the multiplexer according to a detection result of whether the first clock signal is normal or not.
12. The clock holding system of claim 11, wherein the clock signal detection unit is configured to;
outputting a gating control signal for gating the first clock signal in response to the first clock signal being normal;
outputting a gating control signal for gating the second clock signal in response to the first clock signal being abnormal.
13. The clock retention system of claim 12, wherein the power-down protection chip is configured to:
and responding to the multiplexer to gate the second clock signal to be input to the power-down protection chip, and executing a power-down protection flow.
14. The clock retention system of claim 8 or 13, wherein the system further comprises a super capacitor;
the super capacitor is used for supplying power to the power-down protection chip, the crystal oscillator and the clock control unit when the power-down protection chip executes a power-down protection flow.
15. A clock-keeping system as claimed in claim 3, further comprising: a micro control unit;
the micro control unit is connected with the analog phase-locked loop and is used for writing the analog phase-locked loop register after the power-down protection chip is powered up so as to configure the working parameters of the analog phase-locked loop.
16. The clock holding system according to claim 1, wherein the power-down protection chip is used for data protection of a storage device, and the storage device is selected from any one of a disk array card, a solid state disk, and a mechanical hard disk.
17. The clock retention system of claim 16, wherein the crystal oscillator and the clock control unit are integrated on a board of the memory device.
18. The clock holding system of claim 16, wherein the plurality of memory devices is provided, and the crystal oscillator and the clock control unit are mounted to any one of the plurality of memory devices by means of a plug-in.
19. A clock-keeping method, the method comprising:
connecting a first clock signal generated by a main board to one input end of a clock control unit;
connecting a second clock signal generated by the crystal oscillator to the other input end of the clock control unit;
detecting the first clock signal by using the clock control unit to generate a detection result, and selecting one of the first clock signal and the second clock signal as a target clock input according to the detection result;
and providing a third clock signal for the power-down protection chip based on the target clock input.
20. A memory device, comprising:
a power-down protection chip;
the clock control unit is used for detecting the first clock signal to generate a detection result, selecting one of the first clock signal and the second clock signal as a target clock input according to the detection result, and providing a third clock signal for the power-down protection chip based on the target clock input.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202310993732.4A CN116722868B (en) | 2023-08-08 | 2023-08-08 | Clock holding system, method and storage device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202310993732.4A CN116722868B (en) | 2023-08-08 | 2023-08-08 | Clock holding system, method and storage device |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN116722868A true CN116722868A (en) | 2023-09-08 |
| CN116722868B CN116722868B (en) | 2023-11-03 |
Family
ID=87866419
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN202310993732.4A Active CN116722868B (en) | 2023-08-08 | 2023-08-08 | Clock holding system, method and storage device |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN116722868B (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN118393968A (en) * | 2024-06-24 | 2024-07-26 | 杭州胜金微电子有限公司 | Clock detection and control circuit |
Citations (7)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1592134A (en) * | 2003-08-27 | 2005-03-09 | 华为技术有限公司 | Phase alignment method for master and stand-by clocks |
| CN106293004A (en) * | 2016-08-08 | 2017-01-04 | 杭州晟元数据安全技术股份有限公司 | The chip system of a kind of novel raising system stability and method |
| CN110690894A (en) * | 2019-09-20 | 2020-01-14 | 上海励驰半导体有限公司 | Clock failure safety protection method and circuit |
| CN112083755A (en) * | 2020-08-10 | 2020-12-15 | 合肥市芯海电子科技有限公司 | Clock control circuit, chip and clock control method |
| CN114237948A (en) * | 2021-11-17 | 2022-03-25 | 佛山巨晟微电子有限公司 | Crystal oscillator clock failure detection method |
| CN115023681A (en) * | 2019-12-20 | 2022-09-06 | 北欧半导体公司 | Clock selector circuit |
| CN116048192A (en) * | 2022-11-18 | 2023-05-02 | 苏州浪潮智能科技有限公司 | Clock backup circuit, control method, system, device, medium and server |
-
2023
- 2023-08-08 CN CN202310993732.4A patent/CN116722868B/en active Active
Patent Citations (7)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1592134A (en) * | 2003-08-27 | 2005-03-09 | 华为技术有限公司 | Phase alignment method for master and stand-by clocks |
| CN106293004A (en) * | 2016-08-08 | 2017-01-04 | 杭州晟元数据安全技术股份有限公司 | The chip system of a kind of novel raising system stability and method |
| CN110690894A (en) * | 2019-09-20 | 2020-01-14 | 上海励驰半导体有限公司 | Clock failure safety protection method and circuit |
| CN115023681A (en) * | 2019-12-20 | 2022-09-06 | 北欧半导体公司 | Clock selector circuit |
| CN112083755A (en) * | 2020-08-10 | 2020-12-15 | 合肥市芯海电子科技有限公司 | Clock control circuit, chip and clock control method |
| CN114237948A (en) * | 2021-11-17 | 2022-03-25 | 佛山巨晟微电子有限公司 | Crystal oscillator clock failure detection method |
| CN116048192A (en) * | 2022-11-18 | 2023-05-02 | 苏州浪潮智能科技有限公司 | Clock backup circuit, control method, system, device, medium and server |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN118393968A (en) * | 2024-06-24 | 2024-07-26 | 杭州胜金微电子有限公司 | Clock detection and control circuit |
| CN118393968B (en) * | 2024-06-24 | 2024-09-13 | 杭州胜金微电子有限公司 | Clock detection and control circuit |
Also Published As
| Publication number | Publication date |
|---|---|
| CN116722868B (en) | 2023-11-03 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| US8555124B2 (en) | Apparatus and method for detecting an approaching error condition | |
| US7401273B2 (en) | Recovery from errors in a data processing apparatus | |
| CN116722868B (en) | Clock holding system, method and storage device | |
| US5790609A (en) | Apparatus for cleanly switching between various clock sources in a data processing system | |
| US8384435B2 (en) | Clock switching circuit with priority multiplexer | |
| Kim et al. | Razor-lite: A side-channel error-detection register for timing-margin recovery in 45nm SOI CMOS | |
| CN112667450B (en) | Dynamically configurable fault-tolerant system with multi-core processor | |
| US5758136A (en) | Method for dynamically switching between a plurality of clock sources upon detection of phase alignment therefor and disabling all other clock sources | |
| US8407540B2 (en) | Low overhead circuit and method for predicting timing errors | |
| US5020024A (en) | Method and apparatus for detecting selected absence of digital logic synchronism | |
| JPH10161767A (en) | Device and method for automatically sequencing clock within data processing system in starting and finishing power saving state | |
| CN101592975B (en) | Clock switching circuit | |
| CN101901176B (en) | Redundant clock system | |
| US7568138B2 (en) | Method to prevent firmware defects from disturbing logic clocks to improve system reliability | |
| CN111949283B (en) | BMC Flash mirror image self-recovery system and method | |
| CN212112481U (en) | Circuit structure of prototype verification platform | |
| US9438256B2 (en) | Slow to fast clock synchronization | |
| CN113672414A (en) | MCU chip fault safety protection circuit, method and starting method | |
| CN208569614U (en) | A kind of double controller storage system | |
| US20110074386A1 (en) | Voltage indicator signal generation system and method | |
| JP3063334B2 (en) | Highly reliable information processing equipment | |
| US6801973B2 (en) | Hot swap circuit module | |
| CN110175091B (en) | Method, device and circuit for synchronizing signals between nodes under Lockstep architecture | |
| CN113568790B (en) | Chip detection method, detection device and electronic equipment | |
| US10459501B2 (en) | System and method for augmentation of reset recovery operation timing |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| PB01 | Publication | ||
| PB01 | Publication | ||
| SE01 | Entry into force of request for substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| GR01 | Patent grant | ||
| GR01 | Patent grant |