CN111949283A - BMC Flash mirror image self-recovery system and method - Google Patents
BMC Flash mirror image self-recovery system and method Download PDFInfo
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- CN111949283A CN111949283A CN202010915866.0A CN202010915866A CN111949283A CN 111949283 A CN111949283 A CN 111949283A CN 202010915866 A CN202010915866 A CN 202010915866A CN 111949283 A CN111949283 A CN 111949283A
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Abstract
The invention provides a BMC Flash mirror image self-recovery system and a method, wherein one of double BMC Flash chips is mounted on a CPLD, and completely same mirror image files are burnt as backups, when the CPLD detects that the BMC chip is not started within a specified time, the data in the backup Flash chip is synchronously updated to a main Flash chip, so that the Flash mirror image file self-recovery is realized by mounting the Flash chip on the CPLD and through a logic circuit.
Description
Technical Field
The invention relates to the technical field of server design, in particular to a BMC Flash mirror image self-recovery system and a method.
Background
The BMC chip and related components thereof are a relatively independent out-of-band monitoring system on the server, can independently run without depending on other hardware units, BIOS, operating systems and the like, mainly monitors the temperature, voltage, running state and the like of the server, and can complete the control of the on and off of the whole server and the update of firmware such as the BIOS, a control chip and the like. A special Flash memory is hung below the BMC chip, and data interaction is usually carried out between the BMC chip and the Flash based on an SPI bus protocol. In the power-on starting process of the BMC, the configuration of the internal register of the chip and the initialization of each functional unit are carried out by reading binary data which are pre-burned in Flash, and the BMC chip represents the current working state of the BMC chip by outputting watchdog signals with different frequencies outwards. Data in Flash are generally updated in an off-line burning or BMC on-line upgrading mode, and the correctness and stability of the data in Flash are guaranteed to be important for the normal work of the BMC monitoring system. In the current general server system design, in order to improve the safety and reliability of image files in Flash, algorithms such as MD5 are usually used for data encryption and verification in the encoding process, and SPI routing and the like on the motherboard also have strict requirements.
At present, a plurality of servers adopt a design of dual-BMC Flash, namely two identical flashes are mounted on a group of SPI buses output by BMC, data in the two flashes are mutually backed up, and when data in one Flash is abnormal, the Flash can be timely switched to a standby Flash to ensure that the BMC works normally. However, the dual BMC Flash design cannot completely guarantee the security of the mirror image data in practical engineering applications for the following reasons. Firstly, two flashes have the same SPI routing path and similar mainboard environment on a mainboard, the double flashes have poor anti-interference performance of circuit design similar to each other, when data in one Flash has problems, the other Flash is easy to repeat the condition of the former, and more importantly, when the data in one Flash is abnormally distorted, due to the synchronous design of the double-Flash data, for many servers, the Flash serving as a backup can automatically synchronize wrong mirror image versions, so that the double-redundant Flash redundancy does not play a real role. When the BMC Flash image file is damaged, the image cannot be refreshed remotely, and the image can only be updated one by one or returned to a factory for maintenance through a BMC serial port, so that the self-recovery of the BMC Flash image file is particularly important.
Disclosure of Invention
The invention aims to provide a BMC Flash mirror image self-recovery system and a method, and aims to solve the problem of poor anti-interference performance of a dual-BMC Flash design in the prior art, avoid abnormal tampering of data, enhance the capability of a server system against malicious intrusion and improve the running stability of a BMC system.
In order to achieve the technical purpose, the invention provides a BMC Flash mirror image self-recovery system, which comprises:
the device comprises a BMC, a bus switching chip, a control chip, a first Flash chip and a second Flash chip;
the BMC is respectively connected with the bus switching chip and the control chip;
the bus switching chip is respectively connected with the first Flash chip and the control chip;
the control chip is also connected with a second Flash chip;
the first Flash chip and the second Flash chip store the same BMC mirror image file;
when the mirror image in the first Flash chip loaded by the BMC fails, the control chip controls the bus switching chip to gate a line between the control chip and the first Flash chip, and a path between the first Flash chip and the second Flash chip is conducted to complete self-recovery of the mirror image; and after the mirror image is updated, the control chip controls the bus switching chip to gate the line between the BMC and the first Flash chip.
Preferably, the BMC outputs a watchdog signal, and after loading the Flash mirror image, the watchdog signal is changed into a periodic square wave signal with fixed frequency after finishing initialization and normal work.
Preferably, the bus switching chip gates a line between the BMC and the first Flash chip by default.
Preferably, the data communication between the BMC and the bus switching chip and between the bus switching chip and the first Flash chip is SPI bus communication; and the data communication between the control chip and the second Flash chip is SPI bus communication.
Preferably, the system further comprises an external computer, and the external computer is connected with the BMC through a network.
The invention also provides a BMC Flash mirror image self-recovery method, which comprises the following operations:
monitoring a watchdog signal output by the BMC through a control chip, and starting the control chip to actively update the BMC Flash mirror image when the watchdog signal exceeds a periodic signal with a preset frequency within a set time;
the control chip sets a reset signal of the BMC chip to be a low level, forces the BMC to enter a reset state, controls the bus switching chip to gate a line between the control chip and the first Flash chip, conducts the first Flash chip and the second Flash chip, and updates a mirror image file of the second Flash chip to the first Flash chip;
the control chip controls the bus switching chip to gate a circuit between the BMC and the first Flash chip, releases the reset signal of the BMC chip, and normally loads the mirror image file of the first Flash chip.
Preferably, the method further comprises upgrading the Flash chip image file, specifically:
the image file in the PC is transmitted to the BMC through a network signal, the BMC transmits the image file to the control chip, and the image file is transmitted into the second Flash chip through the control chip, so that the upgrading operation of the image file of the second Flash chip is completed;
and the BMC completes the upgrading operation of the image file in the first Flash chip through a default-gated channel between the BMC and the first Flash chip.
Preferably, the BMC transmits the image file to the control chip through an I2C bus.
The effect provided in the summary of the invention is only the effect of the embodiment, not all the effects of the invention, and one of the above technical solutions has the following advantages or beneficial effects:
compared with the prior art, one of the double-BMC Flash chips is mounted on the control chip, the completely same image file is burnt to be used as a backup, and when the control chip detects that the BMC chip is not started within a specified time, the data in the backup Flash chip is synchronously updated to the main Flash chip, so that the Flash image file is self-recovered by mounting the Flash chip on the control chip and through the logic circuit.
Drawings
FIG. 1 is a block diagram of a BMC Flash mirror image self-recovery system provided in an embodiment of the present invention;
FIG. 2 is a flow chart of a BMC Flash mirror image self-recovery method provided in the embodiment of the present invention;
in the figure, 101-server mainboard, 102-BMC, 103-first Flash chip, 104-control chip, 105-second Flash chip, 106-PC, 107-bus switching chip.
Detailed Description
In order to clearly explain the technical features of the present invention, the following detailed description of the present invention is provided with reference to the accompanying drawings. The following disclosure provides many different embodiments, or examples, for implementing different features of the invention. To simplify the disclosure of the present invention, the components and arrangements of specific examples are described below. Furthermore, the present invention may repeat reference numerals and/or letters in the various examples. This repetition is for the purpose of simplicity and clarity and does not in itself dictate a relationship between the various embodiments and/or configurations discussed. It should be noted that the components illustrated in the figures are not necessarily drawn to scale. Descriptions of well-known components and processing techniques and procedures are omitted so as to not unnecessarily limit the invention.
The following describes a BMC Flash image self-recovery system and method provided by an embodiment of the present invention in detail with reference to the accompanying drawings.
As shown in fig. 1, an embodiment of the present invention discloses a BMC Flash mirror image self-recovery system, which includes:
the device comprises a BMC, a bus switching chip, a control chip, a first Flash chip and a second Flash chip;
the BMC is respectively connected with the bus switching chip and the control chip;
the bus switching chip is respectively connected with the first Flash chip and the control chip;
the control chip is also connected with a second Flash chip;
the first Flash chip and the second Flash chip store the same BMC mirror image file;
when the mirror image in the first Flash chip loaded by the BMC fails, the control chip controls the bus switching chip to gate a line between the control chip and the first Flash chip, and a path between the first Flash chip and the second Flash chip is conducted to complete self-recovery of the mirror image; and after the mirror image is updated, the control chip controls the bus switching chip to gate the line between the BMC and the first Flash chip.
The control chip is a CPLD.
In the figure, a BMC chip realizes out-of-band monitoring functions of the temperature, the voltage, the running state and the like of the whole server, ASPEED AST2500 chips are selected, a configuration file required in a BMC initialization process is stored in a first Flash chip mounted on the BMC chip, the BMC chip performs configuration of an internal register of the chip and initialization of each functional unit by reading binary data which is pre-burned in Flash in the power-on starting process, data communication between the BMC and the first Flash chip is realized through buses S1-S2, and the bus type includes but is not limited to an SPI type.
The control chip is used for controlling the power-on/power-off time sequence and state monitoring of the whole server, monitoring a watchdog signal output by the BMC, selecting an Intel MAX10 series, loading Flash data by the BMC within a specified time t, finishing initialization and normal work after the BMC loads the Flash data, changing the watchdog signal into a periodic square wave signal with the frequency of xHz, and if the control chip detects a xHz signal sent by the BMC within the specified time period, starting the default BMC normally and enabling the data in the Flash to be normal; if the time exceeds t, the control chip circuit logic still does not monitor a periodic signal with the frequency of xHz, the control chip will default that the data in the BMC Flash is tampered, the BMC fails to load the data, and the control chip will be started to actively update the flow of the BMC Flash mirror image.
The second Flash chip is mounted under the control chip, the BMC image file which is the same as the first Flash chip is stored in the second Flash chip, and the second Flash chip and the control chip are in data communication through a bus S7, wherein the bus type includes but is not limited to an SPI type. Under the normal working condition of BMC, the data in the second Flash chip can not be read and written so as to keep the stability of the data.
The first Flash chip and the second Flash chip select MXIC MX25L51245GMI-08G chips.
The bus switching chip selects two bus paths S2-S1 and S6-S1 alternatively, the gating switch is controlled by the control chip and gates S2-S1 lines by default, and the type of the gating switch is NEXPERIA 74CBTLV 3257D. After the process of actively updating the BMC Flash by the control chip is started, the control chip sets a chip reset signal S4 of the BMC to be a low level at first to force the BMC to enter a reset state, the control chip controls a bus switching chip to gate an S6-S1 access through an S5 signal, the control chip controls S7 bus communication at the same time, and data in the second Flash chip is updated to the first Flash chip through an S7-S6-S1 access. After the data updating is finished, the control chip controls the bus switching chip to gate an S2-S1 circuit through the S5, and then the BMC releases a reset signal of the BMC through the control S4 signal, so that the BMC loads the data in the first Flash chip normally.
In conclusion, the self-recovery process of the BMC Flash image file can be completed once.
And for the upgrading of the Flash chip image file, upgrading is carried out in a BMC remote network mode. The image file in the PC is transmitted to the BMC through a network signal S8, the BMC transmits the image file to the control chip through S9, wherein S9 is not limited to bus types such as I2C, and the upgrading operation of the image file in the second Flash chip is completed through an S7 bus between the control chip and the Flash chip; in addition, the BMC completes the upgrading operation of the image file in the first Flash chip through an S2-S1 path which is gated by default.
In the embodiment of the invention, one of the double-BMC Flash chips is mounted on the control chip, the completely same image file is burnt to be used as a backup, and when the control chip detects that the BMC chip is not started within a specified time, the data in the backup Flash chip is synchronously updated to the main Flash chip, so that the Flash image file is self-restored by mounting the Flash chip on the control chip and through the logic circuit.
As shown in fig. 2, an embodiment of the present invention further discloses a BMC Flash mirror image self-recovery method implemented by using the system, which specifically includes the following operations:
monitoring a watchdog signal output by the BMC through a control chip, and starting the control chip to actively update the BMC Flash mirror image when the watchdog signal exceeds a periodic signal with a preset frequency within a set time;
the control chip sets a reset signal of the BMC chip to be a low level, forces the BMC to enter a reset state, controls the bus switching chip to gate a line between the control chip and the first Flash chip, conducts the first Flash chip and the second Flash chip, and updates a mirror image file of the second Flash chip to the first Flash chip;
the control chip controls the bus switching chip to gate a circuit between the BMC and the first Flash chip, releases the reset signal of the BMC chip, and normally loads the mirror image file of the first Flash chip.
The control chip is responsible for monitoring a watchdog signal output by the BMC, the watchdog signal is changed into a periodic square wave signal with the frequency of xHz after the BMC loads Flash data to complete initialization and normal work within a specified time t, if the control chip detects a xHz signal sent by the BMC within the specified time, the default BMC is started to be normal, and the data in the Flash is normal; if the time exceeds t, the control chip circuit logic still does not monitor a periodic signal with the frequency of xHz, the control chip will default that the data in the BMC Flash is tampered, the BMC fails to load the data, and the control chip will be started to actively update the flow of the BMC Flash mirror image.
After the process of actively updating the BMC Flash by the control chip is started, the control chip sets a chip reset signal S4 of the BMC to be a low level at first to force the BMC to enter a reset state, the control chip controls a bus switching chip to gate an S6-S1 access through an S5 signal, the control chip controls S7 bus communication at the same time, and data in the second Flash chip is updated to the first Flash chip through an S7-S6-S1 access. After the data updating is finished, the control chip controls the bus switching chip to gate an S2-S1 circuit through the S5, and then the BMC releases a reset signal of the BMC through the control S4 signal, so that the BMC loads the data in the first Flash chip normally.
And for the upgrading of the Flash chip image file, upgrading is carried out in a BMC remote network mode. The image file in the PC is transmitted to the BMC through a network signal S8, the BMC transmits the image file to the control chip through S9, wherein S9 is not limited to bus types such as I2C, and the upgrading operation of the image file in the second Flash chip is completed through an S7 bus between the control chip and the Flash chip; in addition, the BMC completes the upgrading operation of the image file in the first Flash chip through an S2-S1 path which is gated by default.
The above description is only for the purpose of illustrating the preferred embodiments of the present invention and is not to be construed as limiting the invention, and any modifications, equivalents and improvements made within the spirit and principle of the present invention are intended to be included within the scope of the present invention.
Claims (8)
1. A BMC Flash mirror image self-recovery system, the system comprising:
the device comprises a BMC, a bus switching chip, a control chip, a first Flash chip and a second Flash chip;
the BMC is respectively connected with the bus switching chip and the control chip;
the bus switching chip is respectively connected with the first Flash chip and the control chip;
the control chip is also connected with a second Flash chip;
the first Flash chip and the second Flash chip store the same BMC mirror image file;
when the mirror image in the first Flash chip loaded by the BMC fails, the control chip controls the bus switching chip to gate a line between the control chip and the first Flash chip, and a path between the first Flash chip and the second Flash chip is conducted to complete self-recovery of the mirror image; and after the mirror image is updated, the control chip controls the bus switching chip to gate the line between the BMC and the first Flash chip.
2. The BMC Flash image self-recovery system according to claim 1, wherein the BMC outputs a watchdog signal and changes to a periodic square wave signal with a fixed frequency after the Flash image is loaded, the initialization is completed and the normal operation is completed.
3. The BMC Flash mirror image self-recovery system of claim 1, wherein the bus switch chip gates the line between the BMC and the first Flash chip by default.
4. The BMC Flash mirror image self-recovery system according to claim 1, wherein the data communication between the BMC and the bus switch chip, the bus switch chip and the first Flash chip is SPI bus communication; and the data communication between the control chip and the second Flash chip is SPI bus communication.
5. The BMC Flash image self-recovery system according to claim 1, wherein the system further comprises an external computer, and the external computer is connected to the BMC through a network.
6. A BMC Flash image self-recovery method implemented by the system of any of claims 1-5, the method comprising:
monitoring a watchdog signal output by the BMC through a control chip, and starting the control chip to actively update the BMC Flash mirror image when the watchdog signal exceeds a periodic signal with a preset frequency within a set time;
the control chip sets a reset signal of the BMC chip to be a low level, forces the BMC to enter a reset state, controls the bus switching chip to gate a line between the control chip and the first Flash chip, conducts the first Flash chip and the second Flash chip, and updates a mirror image file of the second Flash chip to the first Flash chip;
the control chip controls the bus switching chip to gate a circuit between the BMC and the first Flash chip, releases the reset signal of the BMC chip, and normally loads the mirror image file of the first Flash chip.
7. The BMC Flash image self-recovery method of claim 6, further comprising upgrading a Flash chip image file, specifically:
the image file in the external computer is transmitted to the BMC through a network signal, the BMC transmits the image file to the control chip, and the image file is transmitted into the second Flash chip through the control chip, so that the upgrading operation of the image file of the second Flash chip is completed;
and the BMC completes the upgrading operation of the image file in the first Flash chip through a default-gated channel between the BMC and the first Flash chip.
8. The BMC Flash image self-recovery method of claim 7, wherein the BMC transmits the image file to the control chip over an I2C bus.
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Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN112883384A (en) * | 2021-03-04 | 2021-06-01 | 中国航空工业集团公司西安航空计算技术研究所 | Protection method for embedded computer boot loader with strong robustness |
| CN114816571A (en) * | 2022-04-15 | 2022-07-29 | 西安广和通无线通信有限公司 | Method, device and equipment for hanging flash memory and storage medium |
| WO2024140223A1 (en) * | 2022-12-30 | 2024-07-04 | 华为技术有限公司 | Chip starting method, chip, electronic device, and readable storage medium |
Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20160099886A1 (en) * | 2014-10-07 | 2016-04-07 | Dell Products, L.P. | Master baseboard management controller election and replacement sub-system enabling decentralized resource management control |
| CN107844330A (en) * | 2017-10-25 | 2018-03-27 | 郑州云海信息技术有限公司 | A kind of method and system of enhancing ARM startup of server code reliabilities |
| CN108334367A (en) * | 2017-08-31 | 2018-07-27 | 郑州云海信息技术有限公司 | A kind of firmware remote update system and method towards BMC chip |
-
2020
- 2020-09-03 CN CN202010915866.0A patent/CN111949283B/en active Active
Patent Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20160099886A1 (en) * | 2014-10-07 | 2016-04-07 | Dell Products, L.P. | Master baseboard management controller election and replacement sub-system enabling decentralized resource management control |
| CN108334367A (en) * | 2017-08-31 | 2018-07-27 | 郑州云海信息技术有限公司 | A kind of firmware remote update system and method towards BMC chip |
| CN107844330A (en) * | 2017-10-25 | 2018-03-27 | 郑州云海信息技术有限公司 | A kind of method and system of enhancing ARM startup of server code reliabilities |
Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN112883384A (en) * | 2021-03-04 | 2021-06-01 | 中国航空工业集团公司西安航空计算技术研究所 | Protection method for embedded computer boot loader with strong robustness |
| CN114816571A (en) * | 2022-04-15 | 2022-07-29 | 西安广和通无线通信有限公司 | Method, device and equipment for hanging flash memory and storage medium |
| CN114816571B (en) * | 2022-04-15 | 2023-06-16 | 西安广和通无线通信有限公司 | Method, device, equipment and storage medium for plug-in flash memory |
| WO2024140223A1 (en) * | 2022-12-30 | 2024-07-04 | 华为技术有限公司 | Chip starting method, chip, electronic device, and readable storage medium |
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