CN110362152A - A kind of synchronization system and method for system hardware time and BMC hardware timeout - Google Patents
A kind of synchronization system and method for system hardware time and BMC hardware timeout Download PDFInfo
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- CN110362152A CN110362152A CN201910574800.7A CN201910574800A CN110362152A CN 110362152 A CN110362152 A CN 110362152A CN 201910574800 A CN201910574800 A CN 201910574800A CN 110362152 A CN110362152 A CN 110362152A
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Abstract
The invention discloses the synchronization systems of a kind of system hardware time and BMC hardware timeout, including CPU, BMC, switching control module, system clock and BMC clock；The CPU and BMC passes through switching control module connecting system clock, switching control module CPU switching or BMC connected system clock respectively, obtains the system hardware time；The BMC itself carry BMC clock realizes BMC hardware timeout and system hardware time synchronization for the system hardware time obtained to be written.The synchronous method of a kind of system hardware time and BMC hardware timeout are also disclosed, solves the problems, such as that BMC hardware timeout can not be synchronous with the system hardware time.Switched by the connection that switching control module realizes BMC and CPU and system clock, whom determines to read the hardware timeout of system；To prevent system boot state BMC from reading influence of the system hardware time to system, BMC detection system open state is set, guarantees that CPU normally obtains always the system hardware time in open state without being influenced by BMC.
Description
Technical field
The present invention relates to server design fields, and in particular to a kind of system hardware time is synchronous with BMC hardware timeout
System and method.
Background technique
CPU (Central Processing Unit, central processing unit) processor is widely used in storage, internet etc.
Various industries.For the CPU and server of ARM platform, CPU and BMC (Baseboard Management Controller, base
Board management controller) there is independent RTC (Real-Time Clock, real-time clock) respectively, it can not be carried out the time between them
Calibration and uniformly, can generation system hardware timeout and the problem of BMC time irreversibility.
If the time of CPU and BMC, there are error, the logging time inaccuracy that the system of will lead to is generated and stored uses
Family leads to error in judgement because of time inaccuracy when analyzing failure.
Summary of the invention
In order to solve the above-mentioned technical problems, the present invention provides a kind of system hardware time is synchronous with BMC hardware timeout
System and method solve the problems, such as that BMC hardware timeout can not be synchronous with the system hardware time.
To achieve the above object, the invention adopts the following technical scheme:
A kind of synchronization system of system hardware time and BMC hardware timeout, characterized in that including CPU, BMC, switching control
Module, system clock and BMC clock；
The CPU and BMC passes through switching control module connecting system clock, switching control module CPU switching or BMC respectively
Connected system clock obtains the system hardware time；
The BMC itself carry BMC clock realizes BMC hardware timeout and is for the system hardware time obtained to be written
Hardware timeout of uniting is synchronous.
Further, the BMC sends BMC_GPIO signal to switching control module, and BMC_GPIO passes through pull down resistor R1
Ground connection, for selecting CPU or BMC to be connected to system clock.
Further, the switching control module includes CPLD, and CPU passes through BMC_ by CPU_I2C0 connection CPLD, BMC
I2C12 connection CPLD, CPLD connect system clock by SYS_RTC_I2C；CPLD also issues SYS_PWROK signal to BMC, uses
In control BMC_GPIO level.
Further, different voltages are arranged in the interface of the CPLD connection CPU and system clock, when realizing CPU and system
The level conversion of clock.
Further, the switching control module realizes the switching of CPU and BMC by gating chip.
Further, the gating chip is PCA9541, and CPU is by the first PCA9617 connection PCA9541, first
PCA9617 realizes level conversion；BMC passes through the 2nd PCA9617 connection PCA9541；PCA9541 connection system clock SYS_RTC
DS3232；ADC voltage detection module is additionally provided in BMC, detection system open state controls BMC_GPIO level.
The present invention also provides the synchronous method of a kind of system hardware time and BMC hardware timeout, using above system,
It is characterized in,
Machine system is inserted into power supply and when power supply line, BMC detect SYS_PWROK be it is low, BMC is issued to the BMC_ of CPLD
GPIO is drawn high；
CPLD is received after BMC_GPIO gets higher, and SYS_RTC_I2C is switched to BMC_I2C12, when BMC obtains system hardware
Between；
BMC clock, BMC hardware timeout and system hardware time synchronization is written in the system hardware time that BMC will acquire；
After pressing power button system boot, the SYS_PWROK that BMC detects that CPLD is issued becomes high level, by BMC_
GPIO release, can not draw high again；
After CPLD detects that BMC_GPIO is lower, SYS_RTC_I2C is switched to CPU_I2C0, CPU reads system hardware
Time.
The present invention also provides the synchronous method of a kind of system hardware time and BMC hardware timeout, using above system,
It is characterized in,
When machine system is inserted into power supply and power supply line, the ADC voltage detection module of BMC detects that system voltage is 0, system
It is not keyed up, the BMC_GPIO signal that BMC is issued to the 2nd PCA9617 EN pin is drawn high, and BMC is hard by PCA9541 acquisition system
The part time；
BMC clock, BMC hardware timeout and system hardware time synchronization is written in the system hardware time that BMC will acquire；
After pressing power button system boot, the ADC voltage detection module of BMC detects that system voltage is 12V, by BMC_
GPIO release, can not draw high again；
CPU completes level conversion by the first PCA9617, obtains the system hardware time by PCA9541.
The beneficial effects of the present invention are:
The synchronization system of system hardware time and BMC hardware timeout of the invention realize BMC by switching control module
Connection with CPU and system clock switches, whom determines to read the hardware timeout of system；To prevent system boot state BMC from reading
It takes influence of the system hardware time to system, BMC detection system open state is set, guarantee CPU in open state always just
The system hardware time is often obtained without being influenced by BMC, while BMC can be adjusted with the system hardware time again and be calibrated；The system also has
There is the function of level conversion.
Detailed description of the invention
Fig. 1 is the structural schematic diagram of the synchronization system of present system hardware timeout and BMC hardware timeout；
Fig. 2 is the structural schematic diagram of the synchronization system embodiment one of present system hardware timeout and BMC hardware timeout；
Fig. 3 is the structural schematic diagram of the synchronization system embodiment two of present system hardware timeout and BMC hardware timeout.
Specific embodiment
In order to clarify the technical characteristics of the invention, below by specific embodiment, and its attached drawing is combined, to this hair
It is bright to be described in detail.Following disclosure provides many different embodiments or example is used to realize different knots of the invention
Structure.In order to simplify disclosure of the invention, hereinafter the component of specific examples and setting are described.In addition, the present invention can be with
Repeat reference numerals and/or letter in different examples.This repetition is that for purposes of simplicity and clarity, itself is not indicated
Relationship between various embodiments and/or setting is discussed.It should be noted that illustrated component is not necessarily to scale in the accompanying drawings
It draws.Present invention omits the descriptions to known assemblies and treatment technology and process to avoid the present invention is unnecessarily limiting.
As shown in Figure 1, the synchronization system of system hardware time and BMC hardware timeout of the invention include CPU, BMC, switching
Control module, system clock and BMC clock；
The CPU and BMC passes through switching control module connecting system clock, switching control module CPU switching or BMC respectively
Connected system clock obtains the system hardware time；
The BMC itself carry BMC clock realizes BMC hardware timeout and is for the system hardware time obtained to be written
Hardware timeout of uniting is synchronous.
The BMC sends BMC_GPIO signal to switching control module, and BMC_GPIO is grounded by pull down resistor R1, is used for
Selection CPU or BMC is connected to system clock.
In order to further illustrate the technical characterstic of this programme, it is described in detail by following two embodiment.
As shown in Fig. 2, the embodiment of the present invention one is by the BMC_I2C12 of the CPU_I2C0 for the 2000+CPU that soars and BMC points
The CPLD not being connected on mainboard, when being connected to external system by one group of SYS_RTC_I2C of control logic and then output of CPLD
On clock chip SYS_RTCDS3232, CPLD is equivalent to a switching effect.
CPU_I2C0 output level is 1.8V, and SYS_RTC DS3232 interface level is 3.3V, and therefore, CPLD is needed herein
Realize level conversion function.CPLD model used by the present embodiment is LCMXO2-2000HC-4FTG256I, it connects
Mouthful can be divided into 5 Bank, each Bank has a VCCIO input voltage pin, be arranged here Bank3 be 1.8V Bank (i.e.
The VCCIO of Bank3 is connected on 1.8V voltage), the CPU_I2C0 that CPU comes out is connected on 1.8V Bank；Other Bank are set as 3.3V
Bank (i.e. the VCCIO of other Bank is connected on 3.3V voltage), the I2C interface of SYS_RTC DS3232 is connected on 3.3V Bank,
The level conversion between 1.8V to 3.3V so may be implemented.
When BMC wants to obtain system time, SYS_RTC_I2C is switched to BMC_I2C12 by CPLD.
CPLD confirms the switching of CPU and BMC by the GPIO of BMC.Herein by a GPIO of BMC alternatively pin
It is connected to CPLD, and adds pull down resistor R1 a to GND, i.e., default BMC_GPIO is low, and CPLD cuts SYS_RTC_I2C at this time
Change to CPU_I2C0.
When BMC will read SYS_RTC, it is only necessary to draw high BMC_GPIO, at this moment CPLD detects BMC_GPIO for height
SYS_RTC_I2C will be switched on BMC_I2C12 by level, and BMC can obtain system hardware temporal information at this time.
BMC is self by one BMC_RTC DS3232 chip of I2C14 carry, to determine its own time, when BMC is obtained
After getting the hardware timeout of system, the hardware timeout of system can be written in the BMC_RTC DS3232 of itself, thus may be used
With with system hardware time synchronization.
It is influenced to not read SYS_RTC by BMC_I2C12 when guaranteeing system boot operation, BMC also has detection function
Can, when BMC_GPIO can not be drawn high to the hardware of reading system after BMC detects the SYS_PWROK signal that CPLD is issued
Between.
This scheme can guarantee that the 2000+CPU that soars normally obtains always the system hardware time in open state without by BMC
It influences, while BMC can be adjusted with the system hardware time again and be calibrated.
The synchronous method of above system are as follows:
Machine system is inserted into power supply and when power supply line, BMC detect SYS_PWROK be it is low, BMC is issued to the BMC_ of CPLD
GPIO is drawn high；
CPLD is received after BMC_GPIO gets higher, and SYS_RTC_I2C is switched to BMC_I2C12, when BMC obtains system hardware
Between；
In system hardware time that BMC will acquire write-in BMC clock BMC_RTC DS3232, BMC hardware timeout and it is
Hardware timeout of uniting is synchronous；
After pressing power button system boot, the SYS_PWROK that BMC detects that CPLD is issued becomes high level, by BMC_
GPIO release, can not draw high again；
After CPLD detects that BMC_GPIO is lower, SYS_RTC_I2C is switched to CPU_I2C0, later by the 2000+ that soars
The system hardware time of CPU reading SYS_RTC DS3232.
In this way, the present embodiment can be achieved based on the time synchronization for 2000+CPU server of soaring.
The embodiment of the present invention two is as shown in Figure 3.
The I2C12 of the I2C0 for the 2000+CPU that soars and BMC is passed through a PCA9617 respectively to be connected on PCA9541,
In, the soar PCA9617 of 2000+CPU of connection is also used as level switch module, and PCA9541 is 2 to select 1 I2C mixer module, passes through
Then the gating for crossing PCA9541 exports one group of SYS_RTC_I2C and is connected on external system time chip SYS_RTC DS3232.
Under normal boot-strap state, the time for reading SYS_RTC DS3232 is gone by the 2000+CPU that soars, is needed at this time by BMC
BMC_I2C12 and the PCA9541 gate of output disconnect, and have EN signal pin, EN signal pin on the PCA9617 connecting with BMC
BMC_GPIO signal is connected, when dragging down BMC_GPIO signal, EN signal drags down certifiable PCA9617 and do not work, BMC_
I2C12 can not be communicated on PCA9541.
When BMC wants to obtain system time, it is only necessary to draw high BMC_GPIO, the PCA9617 connected at this time is in
Working condition, BMC_I2C12 signal, to be communicated to SYS_RTC DS3232, finally can be for delivery on PCA9541
System hardware timeout information.
BMC is self by one BMC_RTC DS3232 chip of I2C14 carry, to determine its own time, when BMC is obtained
After getting the hardware timeout of system, the hardware timeout of system can be written in the BMC_RTC DS3232 of itself, thus may be used
With with system hardware time synchronization.
It being influenced to not read SYS_RTC by BMC_I2C12 when guaranteeing system boot operation, BMC has detection function,
ADC voltage detection module inside BMC can detecte system voltage, can not when BMC detects that 12V main power has electricity
BMC_GPIO is drawn high to the hardware timeout of reading system.
This scheme can guarantee that the 2000+CPU that soars normally obtains always the system hardware time in open state without by BMC
It influences, while BMC can be adjusted with the system hardware time again and be calibrated.
The synchronous method of above system are as follows:
When machine system is inserted into power supply and power supply line, the ADC voltage detection module of BMC detects that system voltage is 0, system
It is not keyed up, the BMC_GPIO signal that BMC is issued to the PCA9617 EN pin of connection is drawn high, and BMC obtains system by PCA9541
Hardware timeout；Since CPU does not work under not open state, so CPU also can not read system hardware by CPU_I2C0
Time；
The system hardware time that BMC will acquire passes BMC_I2C14 write-in BMC clock BMC_RTC DS3232, BMC hardware
Time and system hardware time synchronization；
After pressing power button system boot, the ADC voltage detection module of BMC detects that system voltage is 12V, by BMC_
GPIO release, can not draw high again, so that SYS_RTC DS3232 temporal information cannot be read by PCA9541；
CPU completes level conversion by the PCA9617 of connection when booting, and by PCA9541, this I2C access is connected to
SYS_RTC DS3232, to obtain the system hardware time by the 2000+CPU that soars.
Above-mentioned, although the foregoing specific embodiments of the present invention is described with reference to the accompanying drawings, not protects model to the present invention
The limitation enclosed.To those of ordinary skill in the art, other different forms can also be made on the basis of the above description
Modification or deformation.There is no necessity and possibility to exhaust all the enbodiments.On the basis of technical solution of the present invention
On, the various modifications or variations that can be made by those skilled in the art with little creative work still in protection of the invention
Within range.
Claims (8)
1. a kind of synchronization system of system hardware time and BMC hardware timeout, characterized in that including CPU, BMC, switching control mould
Block, system clock and BMC clock；
The CPU and BMC passes through switching control module connecting system clock, switching control module CPU switching or BMC connection respectively
System clock obtains the system hardware time；
The BMC itself carry BMC clock realizes that BMC hardware timeout and system are hard for the system hardware time obtained to be written
Part time synchronization.
2. the synchronization system of system according to claim 1 hardware timeout and BMC hardware timeout, characterized in that the BMC
Send BMC_GPIO signal to switching control module, BMC_GPIO is grounded by pull down resistor R1, for select CPU or BMC and
System clock connection.
3. the synchronization system of system hardware time and BMC hardware timeout according to claim 2, characterized in that described to cut
Changing control module includes CPLD, and CPU is passed through by CPU_I2C0 connection CPLD, BMC by BMC_I2C12 connection CPLD, CPLD
SYS_RTC_I2C connection system clock；CPLD also issues SYS_PWROK signal to BMC, for controlling BMC_GPIO level.
4. the synchronization system of system hardware time and BMC hardware timeout according to claim 3, characterized in that described
Different voltages are arranged in the interface of CPLD connection CPU and system clock, realize the level conversion of CPU and system clock.
5. the synchronization system of system hardware time and BMC hardware timeout according to claim 2, characterized in that described to cut
Change the switching that control module realizes CPU and BMC by gating chip.
6. the synchronization system of system hardware time and BMC hardware timeout according to claim 5, characterized in that the choosing
Obturator piece is PCA9541, and CPU realizes level conversion by the first PCA9617 connection PCA9541, the first PCA9617；BMC passes through
2nd PCA9617 connection PCA9541；PCA9541 connection system clock SYS_RTC DS3232；The inspection of ADC voltage is additionally provided in BMC
Module is surveyed, detection system open state controls BMC_GPIO level.
7. a kind of synchronous method of system hardware time and BMC hardware timeout, utilizes system as claimed in claim 4, feature
It is,
Machine system is inserted into power supply and when power supply line, BMC detect SYS_PWROK be it is low, BMC is issued to the BMC_GPIO of CPLD
It draws high；
CPLD is received after BMC_GPIO gets higher, and SYS_RTC_I2C is switched to BMC_I2C12, BMC obtains the system hardware time；
BMC clock, BMC hardware timeout and system hardware time synchronization is written in the system hardware time that BMC will acquire；
After pressing power button system boot, the SYS_PWROK that BMC detects that CPLD is issued becomes high level, by BMC_GPIO
Release, can not draw high again；
After CPLD detects that BMC_GPIO is lower, SYS_RTC_I2C is switched to CPU_I2C0, CPU reads the system hardware time.
8. a kind of synchronous method of system hardware time and BMC hardware timeout, utilizes system as claimed in claim 6, feature
It is,
When machine system is inserted into power supply and power supply line, the ADC voltage detection module of BMC detects that system voltage is 0, and system is not opened
Machine, the BMC_GPIO signal that BMC is issued to the 2nd PCA9617 EN pin are drawn high, when BMC obtains system hardware by PCA9541
Between；
BMC clock, BMC hardware timeout and system hardware time synchronization is written in the system hardware time that BMC will acquire；
After pressing power button system boot, the ADC voltage detection module of BMC detects that system voltage is 12V, by BMC_GPIO
Release, can not draw high again；
CPU completes level conversion by the first PCA9617, obtains the system hardware time by PCA9541.
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| CN110908953A (en) * | 2019-11-25 | 2020-03-24 | 山东超越数控电子股份有限公司 | Processor interconnection system and method |
| CN113157046A (en) * | 2021-03-25 | 2021-07-23 | 山东英信计算机技术有限公司 | Method, device and system for managing server BMC time |
| CN114063704A (en) * | 2021-08-30 | 2022-02-18 | 浪潮电子信息产业股份有限公司 | RTC clock circuit |
| CN114115446A (en) * | 2021-11-30 | 2022-03-01 | 杭州迪普信息技术有限公司 | Method for sharing real-time clock and data processing equipment |
| CN114779883A (en) * | 2022-05-17 | 2022-07-22 | 西安易朴通讯技术有限公司 | System clock synchronization method, device, system and storage medium |
| CN114895746A (en) * | 2022-06-14 | 2022-08-12 | 北京东土军悦科技有限公司 | System time synchronization method and device, computing equipment and storage medium |
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| CN114895746B (en) * | 2022-06-14 | 2023-11-07 | 北京东土军悦科技有限公司 | System time synchronization method and device, computing equipment and storage medium |
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Application publication date: 20191022 |