CN115630011A - Method and device for realizing I2C bus communication of master and slave equipment by using CPLD - Google Patents
Method and device for realizing I2C bus communication of master and slave equipment by using CPLD Download PDFInfo
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- CN115630011A CN115630011A CN202211328150.6A CN202211328150A CN115630011A CN 115630011 A CN115630011 A CN 115630011A CN 202211328150 A CN202211328150 A CN 202211328150A CN 115630011 A CN115630011 A CN 115630011A
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- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
- G06F13/38—Information transfer, e.g. on bus
- G06F13/42—Bus transfer protocol, e.g. handshake; Synchronisation
- G06F13/4282—Bus transfer protocol, e.g. handshake; Synchronisation on a serial bus, e.g. I2C bus, SPI bus
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- G06F2213/0016—Inter-integrated circuit (I2C)
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Abstract
The embodiment of the invention discloses a method and a device for realizing I2C bus communication of master and slave equipment by using a CPLD, wherein the method comprises the following steps: configuring an I2C clock; selecting an I2C communication channel of the master device and the slave device by using the CPLD; assigning the I2C clock line of the main equipment to the slave equipment of the corresponding channel; acquiring the falling edge of an I2C clock line of the master device; simultaneously pulling down the I2C clock lines of the master device and the slave device until the configured clock period low level time is met; releasing the I2C clock line of the slave device; judging whether the I2C clock line of the released slave equipment is at a low level or not; if the level is high level, releasing the I2C clock line of the master device; if the level is low, the I2C clock line of the master device is continuously pulled down. The invention realizes the function of simulating the I2C Switch by the CPLD and saves the expenditure of hardware cost.
Description
Technical Field
The invention relates to the technical field of servers, in particular to a method and a device for realizing I2C bus communication of master and slave equipment by using a CPLD (complex programmable logic device).
Background
As shown in fig. 1, if the existing server motherboard BMC needs to access the NVMe hard disk through I2C (the hard disk is inserted into the 8639 connector slot), a special I2C Switch chip is needed, and the CPLD communicates with the BMC on the backplane to manage and control the backplane and the NVMe hard disk. The I2C Switch chip is hardware and expensive, so the use cost is high.
Therefore, it is necessary to design a software way to simulate the function of the I2C Switch chip to reduce the use cost.
Disclosure of Invention
The invention aims to overcome the defects of the prior art, provides a method and a device for realizing I2C bus communication of master and slave equipment by using a CPLD, and aims to simulate the function of an I2C Switch chip by adopting a software mode so as to reduce the use cost.
In order to achieve the purpose, the invention adopts the following technical scheme:
in a first aspect, a method for implementing I2C bus communication of a master device and a slave device by using a CPLD includes:
configuring an I2C clock;
selecting an I2C communication channel of the master device and the slave device by using the CPLD;
assigning the I2C clock line of the main equipment to the slave equipment of the corresponding channel;
acquiring the falling edge of an I2C clock line of the master device;
simultaneously pulling down the I2C clock lines of the master device and the slave device until the configured clock period low level time is met;
releasing the I2C clock line of the slave device;
judging whether the I2C clock line of the released slave equipment is at a low level or not;
if the voltage level is high level, releasing the I2C clock line of the master device;
if the level is low, the I2C clock line of the master device is continuously pulled down.
The further technical scheme is as follows: after the selecting the I2C communication channel between the master device and the slave device by using the CPLD, the method further includes:
analyzing the direction of the I2C data;
and switching the I2C data lines according to the analyzed data direction.
The further technical scheme is as follows: the analyzing the I2C data direction comprises the following steps:
acquiring and analyzing an I2C protocol;
and identifying the control relation of the master equipment and the slave equipment to the I2C data line from the analysis result.
The further technical scheme is as follows: the identifying of the control relationship of the master device and the slave device to the I2C data line from the analysis result includes:
if the direction of the data line is sent to the slave equipment by the master equipment, assigning the data line of the master equipment to the slave equipment of the corresponding channel by adopting a Verilog language in the CPLD;
if the direction of the data line is sent to the master device by the slave device, the data line of the slave device is assigned to the master device of the corresponding channel in the CPLD by adopting Verilog language.
In a second aspect, a device for realizing I2C bus communication of master and slave devices by using a CPLD comprises a configuration unit, a selection unit, an assignment unit, an acquisition unit, a first clock line pull-down unit, a first release unit, a judgment unit, a second release unit and a second clock line pull-down unit;
the configuration unit is used for configuring an I2C clock;
the selection unit is used for selecting an I2C communication channel of the master device and the slave device by utilizing a CPLD;
the assignment unit assigns the I2C clock line of the main equipment to the slave equipment of the corresponding channel;
the acquisition unit is used for acquiring the falling edge of an I2C clock line of the master equipment;
the first clock line pull-down unit is used for pulling down the I2C clock lines of the master device and the slave device at the same time until the configured clock cycle low level time is met;
the first release unit is used for releasing an I2C clock line of the slave device;
the judging unit is used for judging whether the released I2C clock line of the slave equipment is at a low level or not;
the second release unit is used for releasing the I2C clock line of the master device if the level is high;
and the second clock line pull-down unit is used for continuously pulling down the I2C clock line of the master device if the level is low.
The further technical scheme is as follows: the system also comprises an analysis unit and a switching unit;
the analysis unit analyzes the I2C data direction;
and the switching unit is used for switching the I2C data line according to the analyzed data direction.
The further technical scheme is as follows: the analysis unit comprises an acquisition module and an identification module;
the analysis module is used for acquiring and analyzing an I2C protocol;
and the identification module is used for identifying the control relation of the master equipment and the slave equipment to the I2C data line from the analysis result.
The further technical scheme is as follows: the identification module comprises a first assignment module and a second assignment module;
the first assignment module is used for assigning the data line of the master device to the slave device of the corresponding channel by adopting a Verilog language in the CPLD if the direction of the data line is sent to the slave device by the master device;
and the second assignment module is used for assigning the data line of the slave device to the master device of the corresponding channel by adopting a Verilog language in the CPLD if the direction of the data line is sent to the master device by the slave device.
In a third aspect, a computer device includes a memory, a processor, and a computer program stored in the memory and executable on the processor, and the processor executes the computer program to implement the method for implementing I2C bus communication of a master device and a slave device by using CPLD as described above.
In a fourth aspect, a computer-readable storage medium stores a computer program, the computer program comprising program instructions that, when executed by a processor, cause the processor to perform the method for implementing master-slave device I2C bus communication using a CPLD as described above.
Compared with the prior art, the invention has the beneficial effects that: the invention configures the I2C clock; selecting an I2C communication channel of the master device and the slave device by using the CPLD; assigning the I2C clock line of the main equipment to the slave equipment of the corresponding channel; acquiring the falling edge of an I2C clock line of the master device; simultaneously pulling down the I2C clock lines of the master device and the slave device until the configured clock period low level time is met; releasing the I2C clock line of the slave device; judging whether the I2C clock line of the released slave equipment is at a low level or not; if the level is high level, releasing the I2C clock line of the master device; if the level is low, the I2C clock line of the master device is continuously pulled down. Therefore, the function that the CPLD simulates the I2C Switch is realized, and the expenditure of hardware cost is saved.
The foregoing description is only an overview of the technical solutions of the present invention, and in order to make the technical means of the present invention more clearly understood, the present invention may be implemented according to the content of the description, and in order to make the above and other objects, features, and advantages of the present invention more apparent, the following detailed description will be given of preferred embodiments.
Drawings
In order to more clearly illustrate the technical solutions of the embodiments of the present invention, the drawings required to be used in the description of the embodiments are briefly introduced below, and it is obvious that the drawings in the description below are some embodiments of the present invention, and it is obvious for those skilled in the art to obtain other drawings based on the drawings without creative efforts.
FIG. 1 is a prior art frame diagram;
FIG. 2 is a frame diagram of the present invention;
fig. 3 is a flowchart of a method for implementing I2C bus communication between a master device and a slave device by using a CPLD according to an embodiment of the present invention;
fig. 4 is a schematic block diagram of an apparatus for implementing I2C bus communication between a master device and a slave device by using a CPLD according to an embodiment of the present invention;
FIG. 5 is a schematic block diagram of a computer device according to an embodiment of the present invention.
Detailed Description
The technical solutions in the embodiments of the present invention will be clearly and completely described below with reference to the drawings in the embodiments of the present invention, and it is obvious that the described embodiments are some, not all, embodiments of the present invention. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present invention.
It will be understood that the terms "comprises" and/or "comprising," when used in this specification and the appended claims, specify the presence of stated features, integers, steps, operations, elements, and/or components, but do not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and/or groups thereof.
It is also to be understood that the terminology used in the description of the invention herein is for the purpose of describing particular embodiments only and is not intended to be limiting of the invention. As used in the specification of the present invention and the appended claims, the singular forms "a," "an," and "the" are intended to include the plural forms as well, unless the context clearly indicates otherwise.
It should be further understood that the term "and/or" as used in this specification and the appended claims refers to and includes any and all possible combinations of one or more of the associated listed items.
The embodiment of the invention provides a method for realizing I2C bus communication of master and slave equipment by using a CPLD, which is applied to a server.
As shown in fig. 1, if an existing server motherboard BMC (master device) needs to access an NVMe hard disk (slave device) through I2C, and the hard disk is inserted into the 8639 connector slot, a special I2C Switch chip is needed, and a CPLD communicates with the BMC on the backplane to manage and control the backplane and the NVMe hard disk. Therefore, in the existing scheme, the I2C Switch chip is a bridge for control and management, but the I2C Switch chip belongs to hardware, which inevitably causes a problem of high use cost.
As shown in fig. 2, in the present invention, the BMC does not need a special I2C Switch chip if it wants to access the NVME disk, and at the same time, does not prevent the BMC from accessing the CPLD, and thus manages and controls the backplane. Different I2C slave devices are instantiated by logic inside the CPLD, and the slave devices are distinguished by addresses. Since the I2C Switch chip is not required to be used, the use cost can be reduced.
The invention is described below by means of specific embodiments.
A method for implementing I2C bus communication between a master device and a slave device by using a CPLD, as shown in fig. 3, the method comprising the following steps: S10-S90.
S10, configuring an I2C clock.
The system clock and the I2C clock may be identified and configured by the CPLD.
And S20, selecting an I2C communication channel of the master device and the slave device by utilizing the CPLD.
In particular, there are often more than one slave device, and therefore, it is necessary to select with which slave device the master device establishes a communication channel.
In addition, the master device and the slave device include a clock line control and a data line control, and the clock line control and the data line control respectively have different processing modes (the following contents of the specific processing method are specifically described).
And S30, assigning the I2C clock line of the master device to the slave device of the corresponding channel.
And S40, acquiring the falling edge of the I2C clock line of the master device.
And S50, simultaneously pulling down the I2C clock lines of the master device and the slave device until the configured clock period low level time is met.
And S60, releasing the I2C clock line of the slave device.
And S70, judging whether the released I2C clock line of the slave equipment is in a low level or not.
And S80, if the voltage level is high, releasing the I2C clock line of the master device.
And S90, if the level is low, continuously pulling down the I2C clock line of the master device.
For S30-S90, the processing and control of the Clock line are implemented, specifically, if neither the master nor the slave device supports the characteristics of Clock Stretch, the Clock line is unidirectional, and the Clock line of the master device is directly assigned to the slave device. If the Clock Stretch characteristic needs to be supported, detecting the low level of the Clock, comparing the low level with the configured low level of the Clock cycle, if the low level of the Clock is detected, pulling down the Clock lines of the master device and the gated slave device by the CPLD until the configured low level time of the Clock cycle is met, releasing the Clock line of the gated slave device after the time is reached, judging whether the released Clock line is low, if so, pulling down the Clock line of the master device continuously, and if so, releasing the Clock of the master device. The switch with the Clock Stretch characteristic can be realized.
In an embodiment, after step S20, the method further includes the following steps:
and S25, analyzing the I2C data direction.
And S26, switching the I2C data lines according to the analyzed data direction.
Steps S25 and S26 implement the processing and control of the data lines, and since both the master device and the slave device have the possibility of controlling the data lines, it is necessary to determine the control direction of the data lines.
In an embodiment, step S25 specifically includes the following steps:
and S251, acquiring and analyzing the I2C protocol.
And S252, identifying the control relationship of the master equipment and the slave equipment to the I2C data line from the analysis result.
Specifically, it is necessary to first analyze the I2C protocol, and then recognize when the master device performs control of the data line and when the slave device performs control of the data line, thereby determining the control and processing direction of the data line.
In an embodiment, the step S252 specifically includes the following steps:
and S2521, if the direction of the data line is sent to the slave device by the master device, assigning the data line of the master device to the slave device of the corresponding channel by adopting a Verilog language in the CPLD.
And S2523, if the direction of the data line is sent to the master device by the slave device, assigning the data line of the slave device to the master device of the corresponding channel by adopting a Verilog language in the CPLD.
The invention realizes that the CPLD simulates the I2C Switch, supports the Clock Stretch function and saves the expenditure of hardware cost.
Fig. 4 is a schematic block diagram of an apparatus for implementing I2C bus communication between a master device and a slave device by using a CPLD according to an embodiment of the present invention; corresponding to the above method for implementing I2C bus communication between master and slave devices by using CPLDs, the embodiment of the present invention further provides a device 100 for implementing I2C bus communication between master and slave devices by using CPLDs.
As shown in fig. 4, the apparatus 100 for implementing I2C bus communication of a master device and a slave device by using a CPLD includes a configuration unit 110, a selection unit 120, an assignment unit 130, an acquisition unit 140, a first clock line pull-down unit 150, a first release unit 160, a judgment unit 170, a second release unit 180, and a second clock line pull-down unit 190.
A configuration unit 110, configured to configure the I2C clock.
The system clock and the I2C clock may be identified and configured by the CPLD.
And a selecting unit 120, configured to select an I2C communication channel between the master device and the slave device by using the CPLD.
In particular, there are often more than one slave device, and therefore, it is necessary to select with which slave device the master device establishes a communication channel.
In addition, the master device and the slave device include a clock line control and a data line control, which have different processing modes respectively (the following contents of the specific processing method are specifically described)
The assigning unit 130 assigns the I2C clock line of the master device to the slave device of the corresponding channel.
An obtaining unit 140, configured to obtain a falling edge of an I2C clock line of the master device.
The first clock line pull-down unit 150 is configured to pull down the I2C clock lines of the master device and the slave device simultaneously until the configured clock cycle low time is satisfied.
A first release unit 160 for releasing the I2C clock line of the slave device.
And a judging unit 170 for judging whether the I2C clock line of the released slave device is at a low level.
And a second release unit 180 for releasing the I2C clock line of the master device if the level is high.
The second clock line pull-down unit 190 is configured to continue to pull down the I2C clock line of the master device if the level is low.
Specifically, the clock lines are processed and controlled as follows: if the master device and the slave device do not support the characteristic of Clock Stretch, the Clock line is in a one-way state, and the Clock line of the master device is directly assigned to the slave device. If the Clock Stretch characteristic needs to be supported, the low level of the Clock needs to be detected, the low level of the Clock is compared with the configured low level of the Clock period, if the low level of the Clock is detected, the CPLD pulls the Clock lines of the master device and the gated slave device low until the configured low level time of the Clock period is met, after the time is reached, the Clock line of the gated slave device is released firstly, whether the released Clock line is low or not is judged, if the released Clock line is low, the Clock line of the master device continues to be pulled down, and if the released Clock line is high, the Clock of the master device is released. The switch with the Clock Stretch characteristic can be realized.
In an embodiment, the apparatus 100 for implementing I2C bus communication between a master device and a slave device by using a CPLD further includes a parsing unit and a switching unit.
The analysis unit analyzes the I2C data direction.
And the switching unit is used for switching the I2C data line according to the analyzed data direction.
Specifically, the data lines are processed and controlled in the following manner: since both the master device and the slave device have the possibility of controlling the data lines, it is necessary to determine the control direction of the data lines.
In one embodiment, the parsing unit includes an obtaining module and an identifying module.
And the analysis module is used for acquiring and analyzing the I2C protocol.
And the identification module is used for identifying the control relation of the master equipment and the slave equipment to the I2C data line from the analysis result.
Specifically, it is necessary to first analyze the I2C protocol, and then recognize when the master device performs control of the data line and when the slave device performs control of the data line, thereby determining the control and processing direction of the data line.
In one embodiment, the identification module includes a first assignment module and a second assignment module.
And the first assignment module is used for assigning the data line of the master device to the slave device of the corresponding channel by adopting a Verilog language in the CPLD if the direction of the data line is sent to the slave device by the master device.
And the second assignment module is used for assigning the data line of the slave device to the master device of the corresponding channel by adopting a Verilog language in the CPLD if the direction of the data line is sent to the master device by the slave device.
As shown in fig. 5, the computer device includes a memory, a processor, and a computer program stored in the memory and executable on the processor, and when the processor executes the computer program, the method steps for implementing the I2C bus communication of the master-slave device by using the CPLD as described above are implemented.
The computer device 700 may be a terminal or a server. The computer device 700 includes a processor 720, memory, and a network interface 750, which are connected by a system bus 710, where the memory may include non-volatile storage media 730 and internal memory 740.
The non-volatile storage medium 730 may store an operating system 731 and computer programs 732. The computer programs 732, when executed, cause the processor 720 to perform any of the methods for implementing master-slave I2C bus communication using a CPLD.
The processor 720 is used to provide computing and control capabilities, supporting the operation of the overall computer device 700.
The internal memory 740 provides an environment for the operation of a computer program 732 in the non-volatile storage medium 730, and when the computer program 732 is executed by the processor 720, the computer program may cause the processor 720 to perform any method for implementing the I2C bus communication between the master and the slave devices by using the CPLD.
The network interface 750 is used for network communication such as sending assigned tasks and the like. Those skilled in the art will appreciate that the configuration shown in fig. 5 is a block diagram of only a portion of the configuration relevant to the present teachings and is not intended to limit the computing device 700 to which the present teachings may be applied, and that a particular computing device 700 may include more or less components than those shown, or may combine certain components, or have a different arrangement of components. Wherein the processor 720 is configured to execute the program code stored in the memory to perform the following steps:
a method for realizing I2C bus communication of master and slave devices by using a CPLD comprises the following steps:
configuring an I2C clock;
selecting an I2C communication channel of the master device and the slave device by using the CPLD;
assigning the I2C clock line of the main equipment to the slave equipment of the corresponding channel;
acquiring the falling edge of an I2C clock line of the master device;
simultaneously pulling down the I2C clock lines of the master device and the slave device until the configured clock period low level time is met;
releasing the I2C clock line of the slave device;
judging whether the I2C clock line of the released slave equipment is at a low level or not;
if the level is high level, releasing the I2C clock line of the master device;
if the level is low, the I2C clock line of the master device is continuously pulled down.
In one embodiment: after the selecting the I2C communication channel between the master device and the slave device by using the CPLD, the method further includes:
analyzing the direction of the I2C data;
and switching the I2C data lines according to the analyzed data direction.
In one embodiment: the analyzing the I2C data direction comprises the following steps:
acquiring and analyzing an I2C protocol;
and identifying the control relation of the master equipment and the slave equipment to the I2C data line from the analysis result.
In one embodiment: the identifying of the control relationship of the master device and the slave device to the I2C data line from the analysis result includes:
if the direction of the data line is sent to the slave equipment by the master equipment, assigning the data line of the master equipment to the slave equipment of the corresponding channel by adopting a Verilog language in the CPLD;
and if the direction of the data line is sent to the master device from the slave device, assigning the data line of the slave device to the master device of the corresponding channel by adopting a Verilog language in the CPLD.
It should be understood that, in the embodiment of the present Application, the Processor 720 may be a Central Processing Unit (CPU), and the Processor 720 may also be other general-purpose processors, digital Signal Processors (DSPs), application Specific Integrated Circuits (ASICs), field Programmable Gate Arrays (FPGAs) or other Programmable logic devices, discrete gate or transistor logic devices, discrete hardware components, and the like. Wherein a general purpose processor may be a microprocessor or the processor may be any conventional processor or the like.
Those skilled in the art will appreciate that the configuration of computer device 700 depicted in FIG. 5 is not intended to be limiting of computer device 700 and may include more or fewer components than those shown, or some components may be combined, or a different arrangement of components.
In another embodiment of the present invention, a computer-readable storage medium is provided. The computer readable storage medium may be a non-volatile computer readable storage medium. The computer readable storage medium stores a computer program, wherein when the computer program is executed by a processor, the computer program implements the method for implementing I2C bus communication of a master device and a slave device by using a CPLD, which is disclosed by the embodiment of the present invention.
It is clear to those skilled in the art that, for convenience and brevity of description, the specific working processes of the above-described apparatuses, devices and units may refer to the corresponding processes in the foregoing method embodiments, and are not described herein again. Those of ordinary skill in the art will appreciate that the elements and algorithm steps of the examples described in connection with the embodiments disclosed herein may be embodied in electronic hardware, computer software, or combinations of both, and that the components and steps of the examples have been described in a functional general in the foregoing description for the purpose of illustrating clearly the interchangeability of hardware and software. Whether such functionality is implemented as hardware or software depends upon the particular application and design constraints imposed on the implementation. Skilled artisans may implement the described functionality in varying ways for each particular application, but such implementation decisions should not be interpreted as causing a departure from the scope of the present invention.
In the embodiments provided by the present invention, it should be understood that the disclosed apparatus, device and method can be implemented in other ways. For example, the above-described embodiments of the apparatus are merely illustrative, and for example, the division of the units is only a logical division, and there may be other divisions when the actual implementation is performed, or units having the same function may be grouped into one unit, for example, a plurality of units or components may be combined or may be integrated into another system, or some features may be omitted, or not executed. In addition, the shown or discussed mutual coupling or direct coupling or communication connection may be an indirect coupling or communication connection through some interfaces, devices or units, and may also be an electric, mechanical or other form of connection.
The units described as separate parts may or may not be physically separate, and parts displayed as units may or may not be physical units, may be located in one place, or may be distributed on a plurality of network units. Some or all of the units can be selected according to actual needs to achieve the purpose of the solution of the embodiment of the present invention.
In addition, functional units in the embodiments of the present invention may be integrated into one processing unit, or each unit may exist alone physically, or two or more units are integrated into one unit. The integrated unit can be realized in a form of hardware, and can also be realized in a form of a software functional unit.
The integrated unit, if implemented in the form of a software functional unit and sold or used as a stand-alone product, may be stored in a storage medium. Based on such understanding, the technical solution of the present invention essentially or partly contributes to the prior art, or all or part of the technical solution can be embodied in the form of a software product, which is stored in a storage medium and includes several instructions for causing a computer device (which may be a personal computer, a server, or a network device) to execute all or part of the steps of the method according to the embodiments of the present invention. And the aforementioned storage medium includes: various media capable of storing program codes, such as a usb disk, a removable hard disk, a Read-Only Memory (ROM), a magnetic disk, or an optical disk.
While the invention has been described with reference to specific embodiments, it will be understood by those skilled in the art that various changes in form and details may be made therein without departing from the spirit and scope of the invention. Therefore, the protection scope of the present invention shall be subject to the protection scope of the claims.
Claims (10)
1. A method for realizing I2C bus communication of master and slave devices by using a CPLD is characterized by comprising the following steps:
configuring an I2C clock;
selecting an I2C communication channel of the master device and the slave device by using the CPLD;
assigning the I2C clock line of the master device to the slave device of the corresponding channel;
acquiring the falling edge of an I2C clock line of the master device;
simultaneously pulling down the I2C clock lines of the master equipment and the slave equipment until the configured clock period low level time is met;
releasing the I2C clock line of the slave device;
judging whether the I2C clock line of the released slave equipment is at a low level or not;
if the voltage level is high level, releasing the I2C clock line of the master device;
if the level is low, the I2C clock line of the master device is continuously pulled down.
2. The method for implementing master-slave device I2C bus communication by using CPLD as claimed in claim 1, wherein after selecting the I2C communication channel between the master device and the slave device by using CPLD, further comprising:
analyzing the direction of the I2C data;
and switching the I2C data lines according to the analyzed data direction.
3. The method for implementing I2C bus communication between a master device and a slave device by using a CPLD according to claim 2, wherein the parsing the I2C data direction includes:
acquiring and analyzing an I2C protocol;
and identifying the control relation of the master equipment and the slave equipment to the I2C data line from the analysis result.
4. The method for implementing master-slave device I2C bus communication by using a CPLD according to claim 3, wherein the identifying the control relationship between the master device and the slave device on the I2C data line from the parsing result includes:
if the direction of the data line is sent to the slave equipment by the master equipment, assigning the data line of the master equipment to the slave equipment of the corresponding channel by adopting a Verilog language in the CPLD;
if the direction of the data line is sent to the master device by the slave device, the data line of the slave device is assigned to the master device of the corresponding channel in the CPLD by adopting Verilog language.
5. The device for realizing I2C bus communication of the master device and the slave device by using the CPLD is characterized by comprising a configuration unit, a selection unit, an assignment unit, an acquisition unit, a first clock line pull-down unit, a first release unit, a judgment unit, a second release unit and a second clock line pull-down unit;
the configuration unit is used for configuring an I2C clock;
the selection unit is used for selecting an I2C communication channel of the master device and the slave device by utilizing a CPLD;
the assignment unit assigns the I2C clock line of the main equipment to the slave equipment of the corresponding channel;
the acquisition unit is used for acquiring the falling edge of an I2C clock line of the master equipment;
the first clock line pull-down unit is used for pulling down the I2C clock lines of the master device and the slave device at the same time until the configured clock cycle low level time is met;
the first release unit is used for releasing an I2C clock line of the slave device;
the judging unit is used for judging whether the released I2C clock line of the slave equipment is at a low level or not;
the second release unit is used for releasing the I2C clock line of the master device if the level is high;
and the second clock line pull-down unit is used for continuously pulling down the I2C clock line of the master device if the level is low.
6. The device for realizing I2C bus communication between master and slave devices by using a CPLD according to claim 5, further comprising a parsing unit and a switching unit;
the analysis unit is used for analyzing the I2C data direction;
and the switching unit is used for switching the I2C data line according to the analyzed data direction.
7. The device for realizing I2C bus communication of a master device and a slave device by utilizing a CPLD according to claim 6, wherein the parsing unit comprises an acquisition module and an identification module;
the analysis module is used for acquiring and analyzing an I2C protocol;
and the identification module is used for identifying the control relation of the master equipment and the slave equipment to the I2C data line from the analysis result.
8. The apparatus of claim 7, wherein the identification module comprises a first assignment module and a second assignment module;
the first assignment module is used for assigning the data line of the master device to the slave device of the corresponding channel by adopting a Verilog language in the CPLD if the direction of the data line is sent to the slave device by the master device;
and the second assignment module is used for assigning the data line of the slave device to the master device of the corresponding channel by adopting a Verilog language in the CPLD if the direction of the data line is sent to the master device by the slave device.
9. A computer device comprising a memory, a processor and a computer program stored on the memory and executable on the processor, wherein the processor when executing the computer program implements the method for implementing I2C bus communication between master and slave devices using CPLDs according to any one of claims 1-4.
10. A computer-readable storage medium, characterized in that the storage medium stores a computer program comprising program instructions which, when executed by a processor, cause the processor to carry out the method of implementing master-slave I2C bus communication using a CPLD according to any one of claims 1 to 4.
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| Publication number | Priority date | Publication date | Assignee | Title |
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| CN115982087A (en) * | 2023-02-20 | 2023-04-18 | 中科可控信息产业有限公司 | Signal transmission method, computer device, and storage medium |
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| Publication number | Priority date | Publication date | Assignee | Title |
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| CN115982087A (en) * | 2023-02-20 | 2023-04-18 | 中科可控信息产业有限公司 | Signal transmission method, computer device, and storage medium |
| CN115982087B (en) * | 2023-02-20 | 2023-09-19 | 中科可控信息产业有限公司 | Signal transmission method, computer device and storage medium |
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