CN115982087A

CN115982087A - Signal transmission method, computer device, and storage medium

Info

Publication number: CN115982087A
Application number: CN202310136466.3A
Authority: CN
Inventors: 邹小兵; 费美婧; 朱淇; 聂华; 黄建新; 毛峰; 夏雨
Original assignee: Zhongke Controllable Information Industry Co Ltd
Current assignee: Zhongke Controllable Information Industry Co Ltd
Priority date: 2023-02-20
Filing date: 2023-02-20
Publication date: 2023-04-18
Anticipated expiration: 2043-02-20
Also published as: CN115982087B

Abstract

The application relates to a signal transmission method, a signal transmission device, computer equipment and a storage medium. The method comprises the steps of setting the state of a data signal line to be a clock starting state, and carrying out signal transmission with a back plate through the data signal line under the condition that the data signal line is in the clock starting state. The method indicates the synchronous signal transmission between the mainboard and the backboard by setting the clock starting state of the data signal line, thereby realizing that the synchronous clock is embedded into the data signal line for signal transmission, ensuring that the communication between the mainboard and the backboard does not need precise clock synchronization and reducing the error rate of signal transmission; in addition, the method does not need to additionally increase clock synchronization signal lines, reduces the number of signal line connections between the mainboard and the backboard, and further greatly reduces the cost of the server mainboard.

Description

Signal transmission method, computer device, and storage medium

Technical Field

The present application relates to the field of server technologies, and in particular, to a signal transmission method, a computer device, and a storage medium.

Background

Along with the more and more complicated constitution of server, the load quantity of server mainboard is also more and more, for example, a complicated server mainboard often can expand a plurality of backplates, and every backplate can install a plurality of hard disks again, and the cable interface quantity of mainboard to backplate also increases correspondingly, and the increase of cable interface can be very big influence the reliability of signal transmission between mainboard and the backplate.

At present, a synchronous serial and an asynchronous serial communication protocol is usually adopted between a mainboard and a backplane to realize the transmission and the reception of data packets. The mainboard and the backboard of asynchronous serial communication use respective clock signals as reference to appoint the same baud rate and analysis mode for communication. And synchronous serial communication is realized by sending a synchronous clock by the mainboard, and data transmission is faster and more stable than asynchronous serial communication.

However, the number of input/output ports between the motherboard and the backplane in the conventional synchronous serial mode is very large, which results in very high cost of the server motherboard.

Disclosure of Invention

In view of the above, it is necessary to provide a signal transmission method, a computer device, and a storage medium capable of reducing the cost of a server motherboard in response to the above technical problem.

In a first aspect, the present application provides a signal transmission method, where the signal transmission method is applied to a motherboard of a server, and the motherboard is connected to a backplane of the server through a data signal line; the method comprises the following steps:

setting the state of the data signal line to a clock start state;

and under the condition that the data signal line is in the clock initial state, carrying out signal transmission with the backboard through the data signal line.

In a second aspect, the present application provides a signal transmission method, where the signal transmission method is applied to a backplane of a server, and the backplane is connected to a motherboard of the server through a data signal line; the method comprises the following steps:

detecting the state of the data signal line;

and when the data signal line is detected to be in a clock initial state, carrying out signal transmission with the mainboard through the data signal line.

In a third aspect, the application also provides a computer device. The computer device comprises a memory storing a computer program and a processor implementing the method of the first aspect when executing the computer program.

In a fourth aspect, the application also provides a computer device. The computer device comprises a memory storing a computer program and a processor implementing the method of the second aspect when executing the computer program.

In a fifth aspect, the present application further provides a computer-readable storage medium. The computer-readable storage medium having stored thereon a computer program which, when executed by a processor, implements the method of the first aspect described above.

In a sixth aspect, the present application further provides a computer-readable storage medium. The computer-readable storage medium having stored thereon a computer program which, when executed by a processor, implements the method of the second aspect described above.

According to the signal transmission method, the computer device and the storage medium, the state of the data signal line is set to be the clock starting state, and signal transmission is carried out between the data signal line and the backboard under the condition that the data signal line is in the clock starting state. The method indicates the mainboard and the backboard to carry out synchronous signal transmission by setting the clock starting state of the data signal line, thereby realizing that the synchronous clock is embedded into the data signal line for signal transmission; compared with the traditional synchronous serial transmission mode, the method does not need to additionally increase clock synchronization signal lines, reduces the number of signal line connections between the mainboard and the backboard, and further greatly reduces the cost of the server mainboard.

Drawings

FIG. 1 is a schematic diagram of a signal transmission system according to an embodiment;

FIG. 2 is a flow chart illustrating a signal transmission method according to an embodiment;

FIG. 3 is a schematic flow chart illustrating a signal transmission method for sending data from a motherboard to a backplane according to an embodiment;

FIG. 4 is a timing diagram of the motherboard sending a data bit in one embodiment;

FIG. 5 is a timing diagram of the sending of a data bit by the motherboard in another embodiment;

FIG. 6 is a flowchart illustrating a signal transmission method according to another embodiment;

FIG. 7 is a flow chart illustrating a signal transmission method according to another embodiment;

FIG. 8 is a schematic flow chart illustrating a method for transmitting signals for receiving data by a backplane according to an embodiment;

FIG. 9 is a timing diagram illustrating the receipt of a data bit by the backplane in one embodiment;

FIG. 10 is a timing diagram illustrating the receipt of a data bit by the backplane according to another embodiment;

FIG. 11 is a flow chart illustrating a signal transmission method according to another embodiment;

FIG. 12 is a flow chart illustrating a method for signaling data returned by the backplane according to an embodiment;

FIG. 13 is a timing diagram illustrating the return of a data bit by the backplane according to one embodiment;

FIG. 14 is a timing diagram illustrating the return of a data bit by the backplane in another embodiment;

FIG. 15 is a flowchart illustrating a signal transmission method according to another embodiment;

FIG. 16 is a flowchart illustrating a signal transmission method for receiving data by a motherboard according to an embodiment;

fig. 17 is a schematic flowchart illustrating a signal transmission method for receiving data by a motherboard in another embodiment;

FIG. 18 is a timing diagram of signal transmission in another embodiment;

FIG. 19 is a diagram illustrating a state transition process for sending and receiving data by the motherboard in one embodiment;

FIG. 20 is a state transition flow diagram for the backplane sending and receiving data in one embodiment;

FIG. 21 is a schematic diagram of a circuit board in one embodiment;

FIG. 22 is a schematic diagram of the connection of a motherboard to a backplane in one embodiment;

FIG. 23 is a block diagram showing the construction of a signal transmission device according to an embodiment;

fig. 24 is a block diagram showing a configuration of a signal transmission device according to another embodiment.

Detailed Description

In order to make the objects, technical solutions and advantages of the present application more apparent, the present application is described in further detail below with reference to the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are merely illustrative of the present application and are not intended to limit the present application.

The signal transmission method provided by the embodiment of the application can be applied to a signal transmission system inside a server as shown in fig. 1. The signal transmission system comprises a mainboard and a backboard, wherein a Programmable Logic Device (CPLD) is arranged on the mainboard, and a CPLD is arranged on the backboard. A single data signal line connection is established between the main board and the back board, a 1k omega resistor is pulled up to a power supply (P3V 3_ STBY) at the main board end, and a 1k omega resistor is pulled up to the power supply (P3V 3_ STBY) at the back board end. And data is transmitted and received between the main board and the back board in a half-duplex mode. The following embodiment illustrates the signal transmission method before the motherboard and the backplane in fig. 1.

In one embodiment, as shown in fig. 2, a signal transmission method is provided, where the signal transmission method is applied to a motherboard of a server as in fig. 1, and relates to a process in which the motherboard sends data to the backplane and receives data, and the method includes the following steps:

s101, setting the state of the data signal line to a clock start state.

The clock starting state is used for informing the mainboard of starting to send data to the back board or indicating the back board to return data to the mainboard. When the main board sends data to the back board in advance or receives data returned by the back board in advance, the CPLD of the main board sets the state of the data signal line to be a clock starting state, and then the CPLD of the main board can start sending data to the back board or receiving returned data of the back board.

In this embodiment, the main board is provided with a CPLD for controlling the data signal line. When the main board sends data to the back board in advance, the state of the data signal line can be set to be a clock starting state in a mode of pulling down the data signal line so as to inform the back board of starting to receive the data. Correspondingly, when the mainboard receives the data returned by the backboard, the CPLD of the mainboard can set the state of the data signal line to the clock start state by pulling down the data signal line to inform the backboard to start sending data. Since the state of the data signal line is set to the clock start state by pulling down the data signal line, the clock start state here may also be a low level state of the data signal line.

And S102, carrying out signal transmission with the backboard through the data signal line under the condition that the data signal line is in a clock initial state.

The data signal line is in a clock starting state, and indicates that the main board sends data to the back board in advance or the main board receives data returned by the back board in advance. In this embodiment, when the motherboard sends data to the backplane in advance, the CPLD of the motherboard sets the state of the data signal line to the clock start state to inform the backplane that the motherboard starts sending data, so that the backplane is ready to start receiving data, and then the CPLD of the motherboard can start sending data by controlling the state of the data signal line, and the CPLD of the corresponding backplane reads data by detecting the state of the data signal line, thereby completing the process of sending data by the motherboard and receiving data by the backplane; when the mainboard receives the data returned by the backboard in advance, the CPLD of the mainboard sets the state of the data signal line to be a clock initial state to inform that the backboard can start returning the data, then the CPLD of the mainboard gives the control right of the data signal line to the CPLD of the backboard, the CPLD of the backboard can start returning the data by controlling the state of the data signal line, the corresponding CPLD of the mainboard reads the data by detecting the state of the data signal line, and the process that the backboard returns the data and the mainboard receives the data is completed.

The signal transmission method provided by the embodiment is applied to a mainboard of a server, and the mainboard sets the state of a data signal line to be a clock starting state and performs signal transmission with a backboard through the data signal line under the condition that the data signal line is in the clock starting state. The method indicates the mainboard and the backboard to carry out synchronous signal transmission by setting the clock starting state of the data signal line, thereby realizing that the synchronous clock is embedded into the data signal line for signal transmission; compared with the traditional synchronous serial transmission mode, the method does not need to additionally increase clock synchronization signal lines, reduces the number of signal line connections between the mainboard and the backboard, and further greatly reduces the cost of the server mainboard.

In one embodiment, a signal transmission method for transmitting data from a motherboard to a backplane is provided, as shown in fig. 3, the method includes:

s201, setting the state of the data signal line to a clock start state in a first clock cycle of each transmission cycle of the data transmission phase.

The transmission period is a clock period occupied by the main board sending a data bit, and may be determined according to an actual signal transmission condition, for example, four clock periods may be set as the transmission period of a data bit, or six clock periods may be set as the transmission period of a data bit.

In this embodiment, when the motherboard is in the data sending stage, a clock signal is generated inside the CPLD of the motherboard, and at the rising edge time of the first clock cycle of the transmission cycle of each data bit, the data signal line is pulled down as a hidden clock start bit, that is, the state of the data signal line is set to the clock start state, so as to synchronously inform the backplane that data reception can start, and when the backplane monitors that the data signal line is pulled down, synchronous reception of data sent by the motherboard can start.

S202, starting from the second clock cycle of the transmission cycle, setting the state of the data signal line according to the data bit of the first transmission data, so as to transmit the first transmission data to the backplane.

In this embodiment, after the CPLD of the motherboard pulls down the data signal line, data transmission can be started at the rising edge of the second clock cycle of the transmission cycle. Specifically, a data bit of first transmission data to be transmitted may be determined, and if the data bit of the first transmission data is a first value, the state of the data signal line is set to a high impedance state, where the first value may specifically be a value of "1"; if the data bit of the first transmission data is a second value, the state of the data signal line is set to a low state, wherein the second value may be a value of "0". After the CPLD of the motherboard completes the state of the data signal line in the second clock cycle, the CPLD may then maintain the state of the data signal line in the third, fourth, etc. clock cycles of the transmission cycle until the last clock cycle is excluded, so as to stably transmit the data of the data bit.

S203, the data signal line is released in the last clock cycle of the transmission cycle.

In this embodiment, after the CPLD of the motherboard sets the state of the data signal line in the second, third, N-th clock cycle, etc., the data signal line may be pulled up at the rising edge of the last clock cycle of the transmission cycle, that is, the state of the data signal line is set to the high impedance state, so as to release the data signal line, so as to notify the backplane that data transmission is finished, and instruct the backplane to stop receiving data.

In the method for exemplifying and explaining the embodiment of fig. 3, during a phase of transmitting data by a CPLD (represented by host _ CPLD) of a motherboard, a motherboard clock (represented by host _ clk) is generated inside the host _ CPLD, a signal transmission delay of 2m of a cable length in the motherboard is about 10ns in consideration of practical application, a parasitic capacitance of a signal cable is about 100 to 150pf, a rising edge delay of a signal from 20% to 90% under a pull-up resistance of a single-end 1Kohm is about 120ns, a signal transmission frequency of a lumped circuit is less than 1/(ns × 6) =1.38Mhz, the host _ clk is actually set to be 1.2Mhz, and a data transmission bit rate is about 300Kbps according to a transmission period of 4 host _ clk as one data bit.

When data of one data bit is transmitted specifically at the motherboard end, taking the data of which the transmission data bit is 0 as an example, as shown in fig. 4, a timing chart of which one data bit is 0 is transmitted, in fig. 4, at a rising edge time (position marked with 1 in the drawing) of a first motherboard clock host _ clk cycle, a host _ CPLD pulls down a data signal line as an implicit clock start bit, and at a rising edge time (position marked with 2 in the drawing) of a second host _ clk cycle, the host _ CPLD sets a state of the data signal line to a low state (1' b0) according to a state that the data bit of the first transmission data is 0; the low state (1 'b0) of the data signal line is held in the third host _ clk period, and the state of the data signal line is set to the high-impedance state (1' bz) in the host _ CPLD at the rising edge time (position indicated by symbol 4 in the figure) of the fourth host _ clk period. In actual operation, under the action of a pull-up resistor outside the mainboard, when the output of the host _ CPLD is high-impedance, the data signal line is pulled high, which is equivalent to that the host _ CPLD releases the data signal line at the moment and indicates that transmission of one data bit is finished.

For another example, taking the data with the transmission data bit 1 as an example, as shown in the timing chart of fig. 5 in which one data bit is transmitted as 1, in fig. 5, at the time of the rising edge of the first host _ clk period (position marked by 1 in the figure), the host _ CPLD pulls down the data signal line as an implicit clock start bit, and at the time of the rising edge of the second host _ clk period (position marked by 2 in the figure), the state of the data signal line is set to the high impedance state (1' bz) according to the state where the data bit of the first transmission data is 1; holding the high impedance state (1' bz) of the data signal line for a third host _ clk cycle; at the rising edge of the fourth host _ clk period (position marked 4 in the figure), the host _ CPLD sets the state of the data signal line to the high-impedance state (1' bz), i.e., the host _ CPLD releases the data signal line, indicating that one data bit transmission is finished.

Specifically, in operation, the host _ CPLD sets the state of the data signal line by providing a finite state machine, that is, specifically, the state of the data signal line can be represented by using host _ DAT _ Ctr, and if the state of the data signal line is in a high-impedance state, the host _ DAT _ Ctr can be set to "1'bz", and if the state of the data signal line is in a low-level state, the host _ DAT _ Ctr can be set to "1' b0". For example, when the data bit of the first transmission data is 1, host _ DAT _ Ctr =1' bz; when the data bit of the first transmission data is 0, host _ DAT _ Ctr =1' b0.

The method of the embodiment designs a synchronous serial communication mode, and embeds the synchronous clock into the data signal line, thereby reducing the connection quantity of the signal lines between the mainboard and the backboard. Moreover, the embedded synchronous clock avoids the problem of unstable communication caused by the error of setting a reference synchronous clock in the traditional mainboard and the traditional backboard.

In one embodiment, when the motherboard finishes sending one data bit, the motherboard needs to determine whether to continue sending data or stop sending data. Therefore, as shown in fig. 6, the method in the embodiment of fig. 3 further includes:

s204, starting the first counter to count each time the last clock cycle of the transmission cycle is reached, and determining whether the value of the first counter reaches the length of the first sending data, if so, executing step S205, otherwise, executing step S206.

Wherein, the CPLD of mainboard is inside to be provided with first counter. The first counter is used for recording the digit of the data sent by the mainboard, so that whether the mainboard sends all the first sending data completely is determined according to the recorded digit.

In this embodiment, a half-duplex transceiving mode is adopted between the motherboard and the backplane, and the byte length of the first transmission data to be transmitted can be defined as a fixed length according to design requirements. When the main board sends the first sending data to the backplane, and each time the last clock cycle of the transmission cycle is reached, that is, the rising edge time of the last clock cycle (for example, at the position marked by 4 in fig. 4 or fig. 5), the first counter is started to count, and it is determined whether the count value of the first counter reaches the length of the first sending data.

S205, entering a data receiving stage.

If the count value of the first counter reaches the length of the first sending data, it indicates that the mainboard has finished sending the first sending data, and correspondingly, the backplane has also finished receiving the data. At this time, the backplane is switched from the data receiving stage to the data sending stage, and the corresponding motherboard enters the data receiving stage.

S206, re-enter the first clock cycle of the next transmission cycle, and set the state of the data signal line to the clock start state.

If the count value of the first counter does not reach the length of the first sending data, it indicates that the main board has not sent the first sending data, and the first sending data needs to be sent continuously, at this time, the main board enters the data sending stage again, and returns to the step of S201 again, and enters the next transmission cycle to continue sending data.

The embodiments of fig. 3 to 6 provide a method for sending data from a motherboard to a backplane, and correspondingly, in a data sending stage of the motherboard, the backplane is in a data receiving stage, and the embodiments of fig. 7 to 11 provide a method for receiving data from the backplane.

As shown in fig. 7, the signal transmission method is applied to a backplane of the server in fig. 1, and relates to a process of receiving data by the backplane and transmitting data back to a motherboard, and the method includes the following steps:

s301, detecting the state of the data signal line.

In this embodiment, when the CPLD (denoted by slave _ CPLD) of the backplane receives data from the data signal line, a reference clock (denoted by slave _ clk) needs to be generated inside the slave _ CPLD. The frequency of the reference clock slave _ clk is required to be more than 2 times higher than that of the main board clock host _ clk, so that the slave _ CPLD can accurately capture the edge state of signal conversion on the data signal line. When the back board is ready to receive the data sent by the mainboard, the CPLD of the back board can detect the state of the data signal line and determine whether the data signal line is in the clock initial state, and if the data signal line is in the clock initial state, the CPLD of the back board can start to receive the data sent by the mainboard.

S302, when the data signal line is detected to be in the clock initial state, signal transmission is carried out between the data signal line and the mainboard.

The data signal line is a clock initial state and represents that the back plate receives data in advance or returns data in advance. In this embodiment, when the motherboard sends data to the backplane in advance, the CPLD of the motherboard sets the state of the data signal line to the clock start state, for the backplane, the CPLD of the backplane starts to receive data by reading the state of the data signal line, and after data reception is completed, the backplane is changed from the data reception stage to the data transmission stage, the CPLD of the backplane can start to send data by controlling the state of the data signal line, at this time, the CPLD of the corresponding motherboard reads data by detecting the state of the data signal line, and completes data transmission by the backplane, and the motherboard receives data.

The signal transmission method provided by the embodiment is applied to the backboard of the server, and the backboard carries out signal transmission with the mainboard through the data signal line when detecting that the data signal line is in the clock starting state by detecting the state of the data signal line. The method indicates the signal transmission between the mainboard and the backboard by setting the clock starting state of the data signal line, so that the synchronous clock is embedded into the data signal line for signal transmission, compared with the traditional asynchronous serial transmission mode, the method has the advantages that the communication between the mainboard and the backboard does not need accurate clock synchronization, the baud rate matching problem of asynchronous communication between the mainboard and the backboard can be solved, and the error rate of signal transmission is reduced; compared with the traditional synchronous serial transmission mode, the method does not need to additionally increase clock synchronous signal lines, reduces the number of signal line connections between the mainboard and the backboard, and further greatly reduces the cost of the server mainboard.

In an embodiment, a signal transmission manner is provided in which the backplane receives data sent by the motherboard, as shown in fig. 8, the method includes:

s401, when the data signal line is detected to be converted from the high-impedance state to the low-electrical level state, entering a data receiving stage, starting a low-electrical level counter to count, stopping the low-electrical level counter to count when the data signal line is detected to be converted from the low-electrical level state to the high-electrical level state, starting a high-electrical level counter to count, and stopping the high-electrical level counter to count when the data signal line is detected to be converted from the high-electrical level state to the low-electrical level state.

Wherein, a low level COUNTER (represented by L _ COUNTER) and a high level COUNTER (represented by H _ COUNTER) are arranged inside the CPLD of the backplane. The low level counter is used for recording the clock period number corresponding to the data with the data bit of 0 sent by the mainboard, and the high level counter is used for recording the clock period number corresponding to the data with the data bit of 1 sent by the mainboard.

In this embodiment, when the motherboard sends data to the backplane in advance, the CPLD of the motherboard pulls down the data signal line to prompt the CPLD of the backplane to start receiving the data, and the CPLD of the backplane immediately starts the low level counter to count, that is, when the state of the data signal line is converted from the high resistance state to the low level state, the low level counter is triggered to count at the falling edge of the data signal line; when the state of the data signal line is converted from a low-level state to a high-impedance state, a high-level counter is triggered to count at the rising edge of the data signal line, and the counting of the low-level counter is stopped; when the state of the data signal line is again changed from the high-impedance state to the low-level state, the counting of the high-level counter is terminated at a further falling edge of the data signal line.

S402, determining a data bit of the first receiving data according to the count value of the low level counter and the count value of the high level counter, so as to receive the first receiving data from the motherboard.

In this embodiment, after the CPLD of the backplane terminates the counting of the high level counter, the CPLD of the backplane may determine that the data bit of the received data is "1" or "0" by comparing the count value of the low level counter with the count value of the high level counter. Optionally, the specific determination method may be: if the ratio of the count value in the low-level counter to the count value in the high-level counter is a first preset ratio, determining that the data bit of the first received data is a first value, wherein the first preset ratio can be determined by the state change condition of a data signal line in a transmission period of one data bit, and the first value is a value of '1'; and if the ratio of the count value in the low-level counter to the count value in the high-level counter is a second preset ratio, determining that the data bit of the first received data is a second value, wherein the second preset ratio can be determined by the state change condition of the data signal line in the transmission period of one data bit, and the second value is a value of '0'. It should be noted that, the ratio of the count value in the low-level counter to the count value in the high-level counter represents the duty ratio value of the low level and the high level, and when the duty ratio value is smaller than 1, the data bit of the first transmission data is set to be a value of "1" correspondingly; and when the duty ratio value is larger than 1, correspondingly setting the data bit of the first sending data to be a value of 0.

In the method illustrated in the embodiment of fig. 8, in the phase that the CPLD of the backplane receives data, the slave _ CPLD internally generates the reference clock slave _ clk, and when specifically receives data of one data bit, taking the data with the data bit of 0 as an example, as shown in fig. 9, a timing chart of receiving one data bit of 0 (in the figure, a timing chart of sending one data bit of 0 by the motherboard is shown as a comparison), at the time of a rising edge of a first host _ clk cycle of the motherboard (position indicated in fig. 1), the host _ CPLD pulls down the data signal line as an implicit clock start bit, at the time of a rising edge of a second host _ clk cycle (position indicated in fig. 2), according to the state of the data bit of first sending data being 0, the state of the data signal line is set to the low level state (1 bb 0), at this time, the slave _ CPLD detects the state of the data signal line through the reference clock slave _ clk, and when the state of the data signal line is switched from the high resistance state to the low level state, the slave _ CPLD triggers the counter to count; when the state of the data signal line is detected to be converted from the low-level state to the high-resistance state, a high-level counter is triggered to count. At the end of the transmission cycle of one data bit, i.e. at the rising edge time of the fourth Host _ clk cycle (position marked by 4 in the figure), the CPLD of the motherboard sets the state of the data signal line to be in a high impedance state (1 ″), and correspondingly, the CPLD of the backplane determines that the received data is "1" or "0" through comparison of two counters, in fig. 9, the ratio of the two comparators is 3, i.e. it is determined that the data bit of the first received data received by the backplane is "0".

For example, as shown in fig. 10, when the transmit data bit is 1, a timing chart of receiving one data bit is 1 (in the diagram, the timing chart of transmitting one data bit is 1 is shown as a comparison), at a rising edge time of a first host _ clk period of the motherboard (position indicated by 1 in the diagram), the host _ CPLD pulls down the data signal line as an implicit clock start bit, and at a rising edge time of a second host _ clk period (position indicated by 2 in the diagram), the state of the data signal line is set to a high-impedance state of 1'bz according to the state of the data bit of the first transmit data, at which time, the CPLD of the backplane detects the state of the data signal line by reference clock slave _ clk, and when the state of the data signal line is detected to be converted from 1' bz to 1 'b0', the low-level counter is triggered to count; when the state of the data signal line is detected to be converted from 1'b0 to 1' bz, a high level counter is triggered to count. At the end of the transmission cycle of one data bit, i.e. at the rising edge time of the fourth Host _ clk cycle (position of mark 4 in the figure), the CPLD of the motherboard sets the state of the data signal line to 1' bz, and the CPLD of the backplane determines that the received data is "1" or "0" through comparison of two counters, in fig. 10, the ratio of the two comparators is 1.

Specifically, during operation, the CPLD of the backplane may set the state of the data signal line by setting the finite state machine, that is, may specifically use slave _ DAT _ Ctr to indicate the state of the data signal line, and may set slave _ DAT _ Ctr to "1'bz" if the state of the data signal line is in the high-impedance state, and may set slave _ DAT _ Ctr to "1' b0" if the state of the data signal line is in the low-level state. For example, when the data bit of the first transmission data is 1, slave _ DAT _ Ctr =1' bz; when the data bit of the first transmission data is 0, slave _ DAT _ Ctr =1' b0.

In one embodiment, when the motherboard finishes sending one data bit and the backplane finishes receiving one data bit, the backplane further needs to determine whether to continue receiving data or stop receiving data. Therefore, as shown in fig. 11, the method in the embodiment of fig. 8 further includes:

s403, when it is detected that the data signal line is switched from the high impedance state to the low level state, starting the third counter to count, and determining whether the count value in the third counter reaches the length of the first received data, if so, executing step S404, and if not, executing step S405.

The CPLD of the backboard is internally provided with a third counter which is used for recording the digits of the data received by the backboard, so that whether the backboard completely receives the first received data is determined according to the recorded digits.

In this embodiment, a half-duplex transceiving mode is adopted between the motherboard and the backplane, and the byte length of the first received data to be transmitted can be defined as a fixed length according to design requirements. When the backplane receives the first received data, and each time the last clock cycle of the transmission cycle is reached, i.e., the rising edge of the last clock cycle (e.g., the position marked with the reference number 4 in fig. 9 or fig. 10), the backplane starts a third counter to count, and determines whether the count value of the third counter reaches the length of the first received data. Here, the first received data is actually the aforementioned first transmission data, and the length thereof is also the same as the length of the first received data.

S404, entering a data transmission phase.

If the count value of the third counter reaches the length of the first received data, it indicates that the backplane has already received the first received data, and correspondingly, the motherboard has already sent the data. At this time, the backplane is switched from the data receiving stage to the data sending stage, and the corresponding motherboard enters the data receiving stage.

S405, re-detecting the state of the data signal line, and entering a data receiving stage when detecting that the data signal line is in a clock starting state.

If the count value of the third counter does not reach the length of the first receiving data, it indicates that the backplane has not received the first receiving data, and needs to continue receiving the first receiving data, at this time, the backplane re-detects the state of the data signal line, i.e. returns to the step of S301 again, and enters the data receiving stage to continue receiving the first receiving data. The embodiments of fig. 7 to 11 provide a method for the backplane to receive the first received data, and when the backplane receives the data, the backplane immediately switches from the data receiving state to the data sending state, i.e., enters a data sending stage, and the embodiments of fig. 12 to 15 provide a method for the backplane to send the second sent data.

As shown in fig. 12, the signal transmission method is applied to a backplane of the server in fig. 1, and relates to a process in which the backplane transmits data back to a motherboard and the motherboard receives the data, and the method includes the following steps:

s501, detecting the state of the data signal line.

In this embodiment, when the backplane is ready to return the second sending data to the motherboard, the CPLD of the backplane may detect the state of the data signal line, determine whether the data signal line is in the clock start state, and if the data signal line is in the clock start state, the CPLD of the backplane may start to take over the data signal line and return the second sending data to the motherboard through the data signal line.

S502, when it is detected that the data signal line is in the clock start state, the state of the data signal line is set according to the data bit of the second sending data.

In this embodiment, when the CPLD of the backplane detects that the data signal line is in the clock start state, that is, when the data signal line is pulled low, the data transmission can be started afterwards. Specifically, a data bit of second sending data to be returned may be determined first, and if the data bit of the second sending data is a first value, the state of the data signal line is set to a high-impedance state, where the first value may specifically be a value of "1"; if the data bit of the second transmission data is a second value, the state of the data signal line is set to a low state, wherein the second value may be a value of "0".

S503, releasing the data signal line after the state of the data signal line is maintained for a preset time period.

When the CPLD of the backplane sets the state of the data signal line according to the data bit of the second transmission data, the return data counter may be started to count the number of cycles of the return data, the current state of the data signal line may be continuously maintained during the counting, and when the duration indicated by the count value of the return data counter reaches a preset duration, the CPLD of the backplane indicates that the CPLD of the backplane has returned one data bit, and at this time, the CPLD of the backplane converts the state of the data signal line into a high impedance state, which is equivalent to releasing the data signal line. It should be noted that the preset time length may be determined in advance by the CPLD of the backplane according to the number of clock cycles of the motherboard occupied when receiving data, for example, the preset time length may be determined according to a maximum count value in a low level counter and a high level counter that are started when the backplane receives data before.

In the method of fig. 12, during the phase of returning data from the CPLD of the backplane, the slave _ CPLD internally generates the reference clock slave _ clk, when data of one data bit is specifically returned, taking the data of the returned data bit 1 as an example, the timing chart of returning data bit 1 shown in fig. 13 (in the figure, the timing chart of receiving one data bit 1 by the motherboard is shown as a comparison), at the time of the rising edge of the first host _ clk period of the motherboard (the position marked with 1 on the motherboard clock in the figure), the host _ CPLD pulls down the data signal line as an implicit clock start bit, when the CPLD of the backplane detects that the data signal line is pulled down at this time (the position marked with 1 on the reference clock slave _ clk in fig. 13 is the position of detecting that the data signal line is pulled down), the state of the data signal line is set to be the high-impedance state (1 bz) according to the state of the data bit 1 of the second transmitted data is set to be the state of the second transmitted data, and when the data signal line is pulled high-impedance is detected, the state of the data line is set to be the state (1 b z of the master board is kept in the state of the first high-impedance state of the motherboard 13, and the second transmitted data line is kept in the state of the first bus 1, and the bus 1, the bus 13.

For another example, taking the data with the transmission data bit of 0 as an example, as shown in fig. 14, a timing chart with one data bit of 0 is returned (in the figure, the timing chart with one data bit of 0 is received by the motherboard as a comparison), at the time of the rising edge of the first host _ clk period of the motherboard (the position marked by 1 on the motherboard clock in the figure), the host _ CPLD pulls down the data signal line as an implicit clock start bit, when the CPLD of the backplane detects that the data signal line is pulled down at this time (the position marked by 1 on the reference clock slave _ clk in fig. 14 is the position where the data signal line is pulled down), according to the state with the data bit of 0 of the second transmission data, the state of the data signal line is set to be the low level state (1 ' b0 '), the low level state (1 ' b 0) is continuously maintained for a certain period of time, and the data signal line in fig. 14 is in the low level state in the first, second and third clock periods of the motherboard, so as to transmit the data "0".

In one embodiment, when the backplane finishes returning one data bit and the motherboard finishes receiving one data bit, the backplane further needs to determine whether to continue returning data or stop returning data. Therefore, the method according to the embodiment in fig. 12, as shown in fig. 15, further includes:

s504 starts the fourth counter to count, and determines whether the count value in the fourth counter reaches the length of the second transmission data, if yes, step S505 is executed, and if not, step S506 is executed.

And a fourth counter is arranged inside the CPLD of the backboard. The fourth counter is used for recording the number of bits of the back data of the back plate, so that whether the back plate completely returns all the second sending data is determined according to the recorded number of bits.

In this embodiment, the byte length of the second sending data to be returned can be defined as a fixed length according to design requirements. When the backplane returns the second sending data and detects that the data signal line is pulled high (for example, the position of the mark 4 on the reference clock slave _ clk in fig. 13 or fig. 14), the fourth counter is started to count, and it is determined whether the count value of the fourth counter reaches the length of the second sending data.

And S505, entering a data confirmation phase.

If the count value of the fourth counter reaches the length of the second sending data, it indicates that the backboard has already returned the second sending data, and correspondingly, the mainboard has already received the data, at this time, the backboard shifts from the data returning stage to the data confirmation stage to confirm whether the received and sent data is complete.

S506, re-detecting the state of the data signal line, and entering a data sending stage when detecting that the data signal line is in a clock starting state.

If the count value of the fourth counter does not reach the length of the second sending data, it indicates that the backplane has not sent the second sending data, and needs to continue sending the second sending data, at this time, the backplane reenters the data sending stage, and returns to the step of S501 again, and enters the next transmission cycle to continue returning the second sending data.

The embodiments of fig. 12-15 described above provide a method for the backplane to transmit the second sending data back to the motherboard, and correspondingly, during the data transmission back stage of the backplane, the motherboard is in the data receiving stage, and the embodiments of fig. 16-19 described below provide a method for the motherboard to receive the data.

In one embodiment, a manner is provided for the motherboard to receive the backplane return data, as shown in fig. 16, the method includes:

s601, setting the state of the data signal line to a clock start state in a first clock cycle of each transmission cycle of the data receiving stage.

The transmission period is a clock period required by the mainboard to receive one data bit. In this embodiment, when the motherboard is in the data receiving stage, a clock signal is generated inside the CPLD of the motherboard, and at the rising edge time of the first clock cycle of the transmission cycle of each data bit, the data signal line is pulled down as a hidden clock start bit, that is, the state of the data signal line is set to the clock start state, so as to synchronously notify that the backplane can start to return data, and the motherboard can start to synchronously receive the data returned by the backplane.

S602, starting from the second clock cycle of each transmission cycle of the data receiving stage, determining a data bit of the first receiving data according to the state of the signal data line, so as to receive the second receiving data from the backplane.

In this embodiment, after the data signal line is pulled down by the motherboard, the data reception may be started at the rising edge of the second clock cycle of the transmission cycle. Specifically, the state of the data signal line may be read at the rising edge time of the third clock cycle to determine the data bit of the first received data, and if the state of the signal data line is in the high impedance state, the data bit of the first received data is determined to be a first value, where the first value may specifically be a value of "1"; if the state of the signal data line is a low state, the data bit of the first received data is determined to be a second value, wherein the second value may be a value of "0".

S603, the data signal line is released in the last clock cycle of each transmission cycle of the data reception phase.

In this embodiment, after the motherboard reads data in the second and third clock cycles, the data signal line may be pulled high at the rising edge of the last clock cycle of the transmission cycle, that is, the state of the data signal line is set to a high impedance state, so as to release the data signal line, and notify the backplane that the return data is finished.

In the method illustrated in fig. 16, when a CPLD of a motherboard receives data, a motherboard clock host _ clk is generated inside the host CPLD, and when data of one data bit is specifically received, taking the data with the received data bit of 0 as an example, as shown in fig. 14, a timing chart with the data bit of 0 is received (a timing chart with the backplane returning the data bit of 0 is shown in the figure), at a rising edge time of a first host _ clk period of the motherboard (a position labeled as 1 on the motherboard clock in the figure), the host CPLD pulls down a data signal line as an implicit clock start bit, and at a rising edge time of a second host _ clk period (a position labeled as 2 on the motherboard clock in the figure), the data is received by reading a state of the data signal line, where the state of the data signal line is a low level state, and thus the read data bit is "0"; or, in order to improve the accuracy and stability of reading data, data is received by reading the state of the data signal line at the rising edge time of the third host _ clk period (position of the superscript 3 of the motherboard clock in the figure), where the state of the data signal line is in a low state, and thus the read data bit is "0"; in the fourth host _ clk period, the state of the data signal line is set to a high-impedance state of 1' bz to release the data line.

For another example, taking the data with the transmitted data bit 1 as an example, as shown in fig. 13, a timing chart (shown in the figure) with one data bit 1 is received, at the rising edge time of the first host _ clk period of the motherboard (the position marked by 1 on the motherboard clock in the figure), the host CPLD pulls down the data signal line as an implicit clock start bit, and at the rising edge time of the second host _ clk period (the position marked by 2 on the motherboard clock in the figure), the data is received by reading the state of the data signal line, where the state of the data signal line is in the high impedance state 1' bz, so that the read data bit is "1"; alternatively, in order to improve the accuracy and stability of the read data, the data is received by reading the state of the data signal line at the rising edge time of the third host _ clk period (position marked by 3 on the motherboard clock in the figure), where the state of the data signal line is in the high-impedance state of 1' bz, so that the read data bit is "1"; in the fourth host _ clk period, the state of the data signal line is set to a high-impedance state of 1' bz to release the data line.

In one embodiment, when the motherboard has received a data bit, the motherboard also needs to determine whether to continue receiving data or stop receiving data. Therefore, as shown in fig. 17, the method in the embodiment of fig. 16 further includes:

s604, starting the second counter to count each time the last clock cycle of each transmission cycle of the data receiving stage is reached, and determining whether the count value of the second counter reaches the length of the first received data, if so, executing step S605, and if not, executing step S606.

And a second counter is arranged inside the CPLD of the mainboard. The second counter is used for recording the digit of the data received by the mainboard, so that whether the mainboard completely receives all the first received data is determined according to the recorded digit.

In this embodiment, the byte length of the first received data to be transmitted can be defined as a fixed length according to design requirements. When the motherboard receives the data returned by the backplane, and each time the last clock cycle of the transmission cycle is reached, i.e. the rising edge time of the last clock cycle (for example, the position marked with 4 in fig. 13 or fig. 14), the second counter is started to count, and it is determined whether the count value of the second counter reaches the length of the first received data.

S605, enter the data confirmation phase.

If the count value of the second counter reaches the length of the first receiving data, it is indicated that the main board has received the first receiving data, that is, the main board has performed one round of sending and receiving data, at this time, because in practical application, hot plugging to the cable may cause transmission of an incomplete data packet or an error data packet in the transmission process of the data signal line, for the data receiving side, only after detecting that transmission of a complete data packet (sending data + receiving data) is completed, the received data is given to the data register from the temporary storage device for storage, so the main board needs to enter a data confirmation stage to confirm whether the sent first sending data and the received first receiving data meet the requirement of the complete data packet.

Optionally, after the motherboard enters the data confirmation stage, the CPLD of the motherboard pulls down the data signal line, and determines whether data transmission is complete according to the length of the first sending data and the length of the first receiving data, and if it is determined that data transmission is complete, stores the first receiving data, and enters the idle stage; and if the data is determined not to be completely transmitted, discarding the first received data, and re-entering a data sending stage to send new first sent data.

When the CPLD of the motherboard determines whether data transmission is complete, the CPLD may sum the length of the first transmission data and the length of the first reception data, and then compare the sum result with the length of the preset data packet, and if the sum result is consistent with the length of the preset data packet, it indicates that data transmission is complete, at this time, the first reception data may be transferred from the temporary memory to the data register for storage, and then the motherboard stops transmitting the synchronized motherboard clock signal host _ clk, and forces the data signal line to enter the idle stage. And if the summation result is inconsistent with the length of the preset data packet, indicating that the data transmission is incomplete. At this time, the first received data may be directly discarded, and a round of processes of sending and receiving data may be performed again, that is, the main board data sending stage (the step of S201 described above) is re-entered to resend and receive data until complete first received data is obtained.

Optionally, when entering the data confirmation phase, in addition to confirming whether the data transmission is complete, the received data may be further checked, specifically, a Cyclic Redundancy Check (CRC) check code may be added to the last byte of the received data to further enhance the reliability of the data transmission, and when a CRC error is detected, the data packet transmitted this time is discarded. Because the serial IO signal is refreshed in real time, the data refreshing delay caused by discarding the unreliable data packet has no influence on the detection and control of the hard disk state on the backboard, the LED lamp and other low-speed signals.

S606, re-enter the first clock cycle of the next transmission cycle, and set the state of the data signal line to the clock start state.

If the count value of the second counter does not reach the length of the first receiving data, it indicates that the main board has not received the first receiving data, and the first receiving data needs to be continuously received, at this time, the main board enters the data receiving stage again, and returns to the step of S601 again, and enters the next transmission cycle to continuously receive the first receiving data.

It should be noted that, after the motherboard enters the idle state, the CPLD of the motherboard further executes the following steps: and pulling up the data signal line, starting an idle counter to count, and entering a data sending stage to send new first sending data when the count value in the idle counter reaches a preset threshold value so as to enter a new round of data sending and receiving.

The idle period corresponding to the idle state can be determined by the main board according to the actual data transmission condition. For example, a clock period exceeding the transmission period may be regarded as an idle period, and when the state of the data signal line is in a high impedance state in the idle period, it is determined that the data signal line is in an idle state. For example, if four host _ clk cycles are transmission cycles of one data bit, the corresponding six host _ clk cycles may be regarded as one idle cycle, or five host _ clk cycles may be regarded as one idle cycle. An idle counter is arranged in the CPLD on the mainboard and used for recording the clock periodicity corresponding to the idle state.

In actual operation, after the motherboard enters an idle stage, the CPLD of the motherboard pulls up the data signal line to make the state of the data signal line in a high impedance state and keep this state all the time in the idle period, and then the idle counter can be started to count, when the count value in the idle counter reaches a preset threshold value, the motherboard starts sending new data in advance, the idle state is converted into a data sending state, at this time, the motherboard pulls down the data signal line to send out a synchronous motherboard clock host _ clk, that is, the motherboard can enter a data sending stage to send new first sending data to enter a new round of data sending and receiving.

For example, as shown in the timing chart shown in fig. 18, when the motherboard sends data and the backplane sends data, the motherboard completes sending and receiving of a data packet, the motherboard enters the idle state with six motherboard clock cycles, and when the six motherboard clock cycles end, the motherboard reenters the data sending stage to send data.

In practical applications, according to bit data transmission of 300Kbps, a data packet for sending 48 bits and receiving 48 bits is completed in a half-duplex manner, the time is 325.8us, the time occupied by an idle state is removed, and the refresh rate of Input/Output (I/O) is kept within 3 KHz. In the last clock cycle of the transmission cycle of the data transmission

The signal transmission method provided by the application can also be realized by adopting the design of a finite-state machine, wherein the design of implicit clock synchronous serial I/O transmission and receiving interface functions is carried out. A Finite State Machine (FSM) is a mathematical model that represents the behavior of a Finite number of states and transitions and actions between these states. The following embodiments illustrate the implementation of the signal transmission method using a finite state machine.

The following is explained in advance: the host _ DAT _ Ctr represents a control state of the host _ CPLD on the data signal line, and the Slave _ DAT _ Ctr represents a control state of the Slave _ CPLD on the data signal line. The main board and the back board are physically connected by a data signal line (see fig. 1). Each of the host _ DAT _ Ctr and slave _ DAT _ Ctr has two states of "1' bz" and "1' b0", i.e., a high-impedance state and a low-impedance state, and when one of the host _ DAT _ Ctr and slave _ DAT _ Ctr is set to "1' bz", the state of the data signal line is determined by the state of the other, which is specifically referred to the data signal line control table shown in table one.

Watch 1

The state "1" b1 "in the table one indicates that the data signal line is pulled up to" 1 "by the external pull-up resistor, and the data signal line at this time is also in a high impedance state, i.e., not controlled by the backplane.

In one embodiment, a state transition process for implementing the data transmitting and receiving function of host _ CPLD by using a finite state machine is provided, as shown in fig. 19, the process includes:

(1) State 0 (IDLE state SM _ IDLE): after the host _ CPLD is powered on, the host _ CPLD is initialized to enter an IDLE state (represented by IDLE), and the IDLE state is realized by setting and stopping 6 host _ clk periods by an IDLE COUNTER IDLE _ COUNTER. After the end of the IDLE _ COUNTER count, the state transitions to state 1 (data transmission phase SM _ TXD _ START). At this stage, the Slave CPLD does not control the data signal line, therefore, the high-resistance state 1' bz is always maintained for the control state Slave _ DAT _ Ctr of the data signal line.

(2) State 1 (data transmission phase SM _ TXD _ START): the host _ CPLD internally generates a motherboard clock signal host _ clk, which transmits data of 1 data bit every four host _ clk. At the rising edge of the 1 st _ clk, the host _ CPLD pulls down the data signal line to make the state of the data signal line a clock start state, even if the control state host _ DAT _ Ctr =1' br 0 of the data signal line marks the start of data transmission, at which time the host _ CPLD transitions to state 2 (transmission data SM _ TXD _ transmission is set);

(3) State 2 (set transmission data SM _ TXD _ transmission): at the 2 nd rising edge of host _ clk, host _ CPLD sets host _ DAT _ Ctr according to the state of the 1 st transmitted data bit TXD [ n ], and when TXD [ n ] data is 1, host _ DAT _ Ctr is set to the high-impedance state 1'bz, and when TXD [ n ] data is 0, host _ DAT _ Ctr is set to the low-level state 1' b0. When the host _ CPLD sets the host _ DAT _ Ctr, the host _ CPLD transitions to state 3 (data retention SM _ TXD _ HOLD);

(4) State 3 (data HOLD SM _ TXD _ HOLD): the clock cycle starting at the 3 rd rising edge of host _ clk is the data holding cycle, the control state host _ DAT _ Ctr of the data signal line is kept at the current state, the data signal line provides a stable state for the slave _ CPLD to read data, and then the host _ CPLD transitions to state 4 (RELEASE of the data signal line SM _ TXD _ RELEASE).

(5) State 4 (RELEASE data signal line SM _ TXD _ RELEASE): in a clock period starting from the 4 th rising edge of host _ clk, the control state host _ DAT _ Ctr of the data signal line is set to the high-impedance state 1' bz, so that the data signal line is released by host _ CPLD, and the data signal line is set to be high by an external pull-up resistor during specific operation. In this state, the data bits that have been transmitted are counted, i.e., the transmitted data COUNTER TXD _ COUNTER is started to count. If the length of the data bit recorded by TXD _ COUNTER has reached the length of the transmitted data, transition to state 5 at the time of the next rising edge of host _ clk (data receive phase SM _ RXD _ START); if the length of the data bit recorded by the TXD _ COUNTER does not reach the length of the transmission data, indicating that the host _ CPLD transmission data is not finished, the state is shifted to the state 1 (data transmission phase SM _ TXD _ START) to enter the transmission period of the next data bit.

During the data bit transmission process of the 4 host clk, setting host _ DAT _ Ctr =1' b0 in the 1 st clock cycle of host _ clk; the state of host _ DAT _ Ctr at the 2,3 clock cycle of host _ clk is determined by the data bit to be transmitted. When the transmission data is 1, the state of host _ DAT _ Ctr remains in the high-impedance state of 1' bz for the 2,3,4 th cycle within 4 clock cycles of host _ clk. When the transmission data is 0, the state of the host _ DAT _ Ctr is maintained in the low level state of 1'b0 in the 1,2,3 th cycle of the clock cycle of 4 host _ clk, and the state of the host _ DAT _ Ctr set in the 4 th clock cycle is 1' bz.

(6) State 5 (data reception phase SM _ RXD _ START): the host _ CPLD repeats the process of transmitting data until all data transmission is completed. And after the data is sent, the data is transferred to the backboard to transmit the data back to the mainboard, and at the moment, the mainboard starts 4 host _ clk cycles of received data received by one data bit. In the 1 st _ clk period of the received data, the host _ CPLD pulls down the data signal line, sets the state of the host _ DAT _ Ctr to the low state 1' b0, sets the state of the data signal line to the clock start state, and notifies the slave _ CPLD to start a data loopback cycle to the host _ CPLD. At this time, the host _ CPLD receives the data looped back by the slave _ CPLD, and shifts to state 6 (ready to receive data SM _ RXD _ preamble).

(7) State 6 (ready-to-receive data SM _ RXD _ preamble): in the 2 nd host _ clk clock cycle of receiving data, the host _ CPLD sets the state of the host _ DAT _ Ctr to be a high-impedance state 1' bz, and releases the control of the data signal line; the actual state of the data signal line at this time depends on the state of the slave _ DAT _ Ctr, and the host _ CPLD starts to be ready to receive data. Then, the host _ CPLD transitions to state 7 (read data SM _ RXD _ LATCH).

(8) State 7 (read data SM _ RXD _ LATCH): in the 3 rd host _ clk clock cycle of receiving data, the host _ CPLD sets the state of the host _ DAT _ Ctr to be a high-impedance state 1' bz, and releases the control of the data signal line; at this time, the host _ CPLD reads data according to the actual state of the host _ DAT _ Ctr of the data signal line, which depends on the setting of the slave _ DAT _ Ctr, and saves the read data to the data receiving register RXD _ TEMP [ n ], n = RXD _ COUNTER. RXD _ COUNTER is a received data COUNTER in which the count value represents the length of the received data. Then, the host _ CPLD transitions to state 8 (RELEASE data signal line SM _ RXD _ RELEASE).

(9) State 8 (RELEASE data signal line SM _ RXD _ RELEASE): at the 4 th host _ clk clock cycle when the host _ CPLD receives data, host _ DAT _ Ctr is set to the high-impedance state 1' bz, and the host _ CPLD releases the control of the data signal line; at this time, the slave _ CPLD will also release the control of the data signal line, which is pulled high by the external pull-up resistor, indicating that the reception of one data bit is finished. If the data LENGTH recorded by the received data COUNTER RXD COUNTER is smaller than the data transmission LENGTH to be received RXD LENGTH, a transition is made back to state 5 (data reception stage SM _ RXD _ START) for reception of the next data bit. Otherwise, after the data LENGTH recorded by RXD COUNTER reaches the LENGTH RXD LENGTH of the received data, the state 9 is entered in the rising edge of the 4 th host _ clk clock cycle (data acknowledge SM _ RXD _ END).

(10) State 9 (data acknowledgment SM _ RXD _ END): after entering the state, the Host _ CPLD pulls down the data signal line, so that the Host _ DAT _ Ctr state of the data signal line is set to be a low level state to notify the slave _ CPLD to prepare to enter an IDLE state IDLE after completing sending the data packet, and at the same time, data packet confirmation is performed in the state, specifically, the sum of the sending data LENGTH TXD _ LENGTH and the receiving data LENGTH RXD _ LENGTH is compared with the LENGTH of an actual data packet, and then whether the data packet is completely transmitted is determined according to the comparison result, if the data packet is completely transmitted, the state 0 (IDLE state SM _ IDLE) is entered, if the data packet is not completely transmitted, the previously received data is discarded, and the state 1 (data sending stage SM _ TXD _ START) is entered again. In this state, a CRC check function may be further configured to check the received data, and if there is no problem in checking the received data, the state 0 (IDLE state SM _ IDLE) is entered; if there is a problem with the check of the received data, the received data is discarded and state 5 is entered (data reception stage SM _ RXD _ START) to re-receive the data. When the state 0 (IDLE state SM _ IDLE) is entered, the IDLE COUNTER IDLE _ COUNTER in the IDLE state may be set, and when the count value in the IDLE COUNTER IDLE _ COUNTER reaches a preset threshold, the state 0 (IDLE state SM _ IDLE) is transferred to at the rising edge of the next host _ clk clock period.

The execution period from the above state 0 to the state 9 is the sum of the clock period occupied by the transmission data, the clock period occupied by the reception data, the clock period occupied by the data acknowledgement, and the clock period occupied by the idle state. In practical applications, if 4 host _ clk clock cycles are transmission cycles of one data bit, the total required execution cycle for transmitting 64-bit transmission data and 64-bit reception data is 4 × 128+7=519 host _ clk clock cycles. When the host _ clk frequency is 1.2MHz (the clock period is 0.83 us), the transmission duration for completing one data packet is 432.5us.

In one embodiment, a state transition process for implementing the data receiving and transmitting functions of the slave _ CPLD by using a finite state machine is provided, at a receiving end of the slave _ CPLD, a reference clock slave _ clk is set inside the slave _ CPLD, and the frequency of the slave _ clk needs to be more than 2 times that of the host _ clk compared with the frequency of the host _ clk, so that the slave _ CPLD can accurately distinguish the rising or falling edge of a data signal line. As shown in fig. 20, the above process includes:

(1) State 0 (IDLE state SM _ IDLE): after the initialization is finished, the slave _ CPLD enters an IDLE state IDLE in which the slave _ DAT _ Ctr is set to a high impedance state of 1' bz. When the slave _ CPLD detects the 1 st falling edge of the data signal line, the state of the data signal line is at the clock START state, and the slave _ CPLD transitions to the state 1 (START receiving data SM _ RXD _ START) to START preparing to receive data.

(2) State 1 (START reception data SM _ RXD _ START): the slave _ CPLD starts a low counter L _ counter to record the duration of the low period while the data signal line is held low. When it is detected that the data signal line is pulled high from the low level, the L _ counter count is suspended, and the state is shifted to the state 2 (reception data SM _ RXD _ preatch).

(3) State 2 (reception data SM _ RXD _ preamble): and when the slave _ CPLD detects that the data signal line is pulled high from the low level, starting a high level counter H _ counter to record the duration of the high-resistance period. When the slave _ CPLD detects the data signal line is switched from the high-impedance state to the low-impedance state again, the H _ counter is stopped from counting, and the state is switched to the state 3 (reading the data SM _ RXD _ LATCH);

(4) State 3 (read data SM _ RXD _ LATCH): since the host _ CPLD end is designed such that in a transmission period of a data bit, the duration of the data signal line being pulled down and pulled up is determined by the value of the transmitted data, when the transmitted data is 1, the ratio of the duration of the low level to the duration of the high level in the transmission period of a data bit is 1:3, when the transmitted data is 0, the ratio of the duration of the low level and the high level in the transmission period of one data bit is 3:1. at the slave _ CPLD end, it can be determined whether the data bit of the data received by the slave _ CPLD is 1 or 0 by comparing the count values of L _ counter and H _ counter when the transmission cycle of the data bit ends.

When the determination of the data bit is completed, the received data may be written into the received data register RXD _ TEMP [ n ]. Judging whether the data reception is finished or not according to a received data bit counter RXD _ counter, and if the count value recorded by the RXD _ counter reaches the Length RXD _ Length of the received data, transferring to a state 4 (starting to send data SM _ TXD _ START); if the count value recorded by RXD _ counter does not reach RXD _ Length, the state is shifted to state 1 (START of receiving data SM _ RXD _ START) to continue receiving data transmitted from host _ CPLD terminal.

(5) State 4 (START transmission data SM _ TXD _ START): in this state, the slave _ CPLD detects the state of the data signal line, and starts to transmit data if the data signal line is detected to be in the clock initial state, and sets the state of the data signal line according to the state of the data to be transmitted. If the to-be-transmitted data of the slave _ CPLD is 1, the slave _ CPLD end sets the state of the data signal line to be a high-impedance state 1' bz, so that the data signal line is pulled high after the host _ CPLD finishes transmitting the synchronous host _ clk; if the to-be-transmitted data of the slave _ CPLD is 0, the slave _ CPLD end sets the state of the data signal line to be in a low level state of 1' b0, so that the data signal line is pulled down, and since the frequency of the reference clock slave _ clk in the slave _ CPLD is more than 2 times higher than that of the clock host _ clk in the host _ CPLD, the slave _ CPLD can take over the control right of the data signal line before the host _ CPLD releases the data signal line. During data transmission, the slave _ CPLD locks the data signal line to 1' b0 and keeps the state for a preset duration, which can be recorded by using a data hold COUNTER hold _ timer, and the duration recorded by the data hold COUNTER hold _ timer can be determined according to the count values in the low level COUNTER L _ COUNTER in the state 1 and the high level COUNTER H _ COUNTER in the state 2, for example, the hold _ timer = maximum { L _ COUNTER, H _ COUNTER }, which means that the slave _ CPLD can lock the data signal line until the count of the hold _ timer is over, and at this time, the rising edge of the 3 rd host _ CPLD of the slave _ CPLD is over, so as to ensure that the slave _ CPLD can reliably lock the data bit returned by the slave _ CPLD. After the count of the locking delay hold _ timer is finished, the slave _ CPLD releases the data signal line, and the data signal line is pulled high under the action of an external pull-up resistor so as to finish the transmission of data '0'. When the hold _ counter count reaches the duration of the hold _ timer recording and the state of the data signal line transitions from the low state to the high state, transition is made to state 5 (RELEASE of the data signal line SM _ TXD _ RELEASE).

(6) State 5 (RELEASE data signal line SM _ TXD _ RELEASE): in this state, slave _ DAT _ Ctr is set to a high-resistance state of 1' bz, and slave_cpld releases control of the data signal lines; if it is detected that the data signal line is pulled low, transition is made to state 6 (END of transmitting data SM _ TXD _ PRE _ END) on the rising edge of the reference clock slave _ clk.

(7) State 6 (END transmission data SM _ TXD _ PRE _ END): in this state, the slave _ CPLD counts the looped-back data bits, and if the data length corresponding to the count value of the looped-back data counter TXD _ counter is smaller than the data bit length TXD _ length to be looped-back, the state is shifted to state 4 (data SM _ TXD _ START STARTs to be transmitted) on the rising edge of the reference clock slave _ clk; if the data length corresponding to the count value of TXD _ counter reaches the data bit length TXD _ length to be looped back, the state transitions to state 7 (data acknowledge SM _ END) on the rising edge of slave _ clk.

(8) State 7 (data confirmation SM _ END): after entering the state, the slave _ CPLD pulls down the data signal line, and on the falling edge of the pulled-down data signal line, the slave _ CPLD judges whether data transmission is completed, and meanwhile, performs CRC check on the data of the RXD _ TEM temporary memory received in the receiving stage, and verifies the integrity of the data packet, and if the data packet passes the verification, gives the received data to the data register. The slave _ CPLD transitions to the state 0 (IDLE state SM _ IDLE) when the reference clock slave _ clk rises and the data signal line is pulled high by the host _ CPLD, discards the received data if the data packet is not verified, and transitions to the state 1 (START receiving data SM _ RXD _ START) to resume receiving data. In the transition between the states 0 to 7, if the data signal line is pulled up for more than 5 host _ clk periods, the state is forced to return to the state 0 (IDLE state SM _ IDLE).

When the signal transmission method described in fig. 19 and fig. 20 is applied to the circuit board shown in fig. 21, compression of sideband signals between the motherboard and the backplane is achieved, as shown in fig. 21, a data signal line between the motherboard and the backplane is also called smart _ link, and besides signals such as CLK _100m _p, CLK _100m _n, and pcie #, other sideband signals are transmitted through the smart _ link. The state information of the Hard Disk (Hard Drive Disk, HDD) on the backplane and the lighting control ATTENTION _ LED of the I2C _ HP are also transmitted by smart _ link, so that the I2C _ HP only needs to enter the motherboard CPLD, read the HDD state of each Mini Input/output (Mini Cool Edge Input/output, MCIO) through the motherboard CPLD, and control the LED. Thus, the sideband signal is compressed as: CLK _100M _P, CLK _100M _N, PCIERST #, SMART _ LINK, P3V3_ AUX, and so on. The original 2 x 37pin MCIO or slim connector can be implemented by a 2 x 28pin Genz-1C connector.

In this embodiment, the design of the MCIO connection line is simplified by applying smart _ link. By adopting smart _ link, the sideband signals except PCIE _ CLK, PCIE RESET and PCIE/SATA signals can be integrated into a serial transmission signal, and the synchronous serial connection is established between the main board CPLD and the back board CPLD at each MCIO.

Signals such as PORT _ ID [4..0], BP _ SLOT _ ID [4..0], BP _ TYPE [2..0], BIF [2..0] and the like are all transmitted through smart _ link, and state signals HDD _ PRSNT #, ACTIVITY, IFDET # and the like of the hard disk HDD are transmitted from the CPLD of the backboard to the CPLD of the mainboard through the smart _ link. The I2C _ HP of the Central Processing Unit (CPU) and the I2C _ BMC of the Baseboard Management Controller (BMC) access the motherboard CPLD through the I2C bus, and the BMC transmits LED control signals to the backplane, such as HDD _ local #, HDD _ ERR #, and the like, from the motherboard CPLD to the B backplane CPLD.

The design reduces sideband signals in each group of MCIO cables, and 15 signal lines such as PORT _ ID [4..0], BP _ SLOT _ ID [4..0], BP _ TYPE [2..0], BIF [2..0] and the like can be integrated into smart _ link, so that the cost of the MCIO cables is reduced. The I2C _ HP is also changed from accessing the backplane CPLD to accessing the motherboard CPLD, so that the MCIO cable or a dedicated I2C cable is prevented from being connected to the backplane, and the complexity of the system cable connection is reduced, for example, see the schematic connection diagram of the motherboard and the backplane that adopts the smart _ link reduced sideband signal shown in fig. 22.

The signal transmission method provided by the application can achieve the following technical effects:

(1) According to the smart _ link protocol for synchronous serial communication, a synchronous clock is embedded into a data signal line to transmit data, the synchronous clock signal line does not need to be additionally arranged, the number of signal line connections between a mainboard and a backboard is reduced, and the connection mode between the mainboard and the backboard is simplified.

(2) In the design of smart _ link, the embedded synchronous clock can realize the baud rate consistency of communication between the mainboard and the backboard, and solve the baud rate matching problem of asynchronous communication between the mainboard and the backboard.

(3) The mainboard and the backboard do not need precise clock synchronization, as long as the frequency of the mainboard clock host _ clk is ensured to be 2 times or more higher than that of the reference clock of the backboard, and the embedded clocks of the CPLD of the mainboard and the backboard can reach tens of megameters, which is far higher than the transmission rate basic frequency requirement of serial transmission.

(4) At the backboard end, the duty ratio of the data bit is adopted to judge whether the received data is '0' or '1', and the received data value is judged according to the duty ratio of the low level and the high level in the transmission period of one data bit, so that the time sequence requirement when latching based on the clock edge is avoided. The data signal line is insensitive to the capture operation, and the stability of data transmission is improved. Better accuracy and interference immunity than using clock edge latching.

(5) Adopt smart _ link to realize the sideband signal transmission of backplate and mainboard, greatly reduced the sideband signal quantity of cable, reduced connection complexity and cost.

(6) Because smart _ link has the characteristics of high speed and large signal capacity, the CPU accesses the back board through the I2C _ HP and can read information from the register of the mainboard CPLD instead, and the connection complexity of the I2C is reduced.

(7) Comparing the MCIO of 2 × 37 with the Gen-Z1-C connector of 2 × 28, one is the reduction of the transmitted sideband signals, from 20 to 4, and the total number of signals from 2 × 37=74 to 2 × 28=56, and the reduction of the number of signals means a substantial reduction of the cost of the cable and the connector (15% to 20% of the cost), especially the valuable space occupied by the connector on the Printed Circuit Board (PCB) of the backplane and the motherboard.

It should be understood that, although the steps in the flowcharts related to the embodiments described above are shown in sequence as indicated by the arrows, the steps are not necessarily performed in sequence as indicated by the arrows. The steps are not performed in the exact order shown and described, and may be performed in other orders, unless explicitly stated otherwise. Moreover, at least a part of the steps in the flowcharts related to the embodiments described above may include multiple steps or multiple stages, which are not necessarily performed at the same time, but may be performed at different times, and the execution order of the steps or stages is not necessarily sequential, but may be rotated or alternated with other steps or at least a part of the steps or stages in other steps.

Based on the same inventive concept, the embodiment of the present application further provides a signal transmission apparatus for implementing the above related signal transmission method. The implementation scheme for solving the problem provided by the apparatus is similar to the implementation scheme described in the above method, so specific limitations in one or more embodiments of the signal transmission apparatus provided below may refer to the limitations on the signal transmission method in the foregoing, and details are not described here.

In one embodiment, as shown in fig. 23, there is provided a signal transmission device including:

and the setting module 11 is configured to set the state of the data signal line to a clock start state.

The first transmission module 12 is configured to perform signal transmission with the backplane through the data signal line when the data signal line is in the clock start state.

In one embodiment, as shown in fig. 24, there is provided a signal transmission device including:

the detecting module 21 is configured to detect a state of the data signal line.

And the second transmission module 22 is configured to perform signal transmission with the motherboard through the data signal line when detecting that the data signal line is in a clock start state.

The modules in the signal transmission device can be wholly or partially implemented by software, hardware and a combination thereof. The modules can be embedded in a hardware form or independent from a processor in the computer device, and can also be stored in a memory in the computer device in a software form, so that the processor can call and execute operations corresponding to the modules.

In one embodiment, a computer device is provided, comprising a memory and a processor, the memory having a computer program stored therein, the processor implementing the following steps when executing the computer program:

setting the state of the data signal line to a clock start state;

In one embodiment, a computer device is provided, comprising a memory having a computer program stored therein and a processor that when executing the computer program performs the steps of:

detecting the state of the data signal line;

and when the data signal line is detected to be in a clock starting state, carrying out signal transmission with the mainboard through the data signal line.

In one embodiment, a computer-readable storage medium is provided, having a computer program stored thereon, which when executed by a processor, performs the steps of:

setting the state of the data signal line to a clock start state;

and under the condition that the data signal line is in the clock starting state, carrying out signal transmission with the backboard through the data signal line.

detecting the state of the data signal line;

In one embodiment, a computer program product is provided, comprising a computer program which, when executed by a processor, performs the steps of:

setting the state of the data signal line to a clock start state;

detecting the state of the data signal line;

It will be understood by those skilled in the art that all or part of the processes of the methods of the embodiments described above can be implemented by hardware instructions of a computer program, which can be stored in a non-volatile computer-readable storage medium, and when executed, can include the processes of the embodiments of the methods described above. Any reference to memory, database, or other medium used in the embodiments provided herein may include at least one of non-volatile and volatile memory. The nonvolatile Memory may include Read-Only Memory (ROM), magnetic tape, floppy disk, flash Memory, optical Memory, high-density embedded nonvolatile Memory, resistive Random Access Memory (ReRAM), magnetic Random Access Memory (MRAM), ferroelectric Random Access Memory (FRAM), phase Change Memory (PCM), graphene Memory, and the like. Volatile Memory can include Random Access Memory (RAM), external cache Memory, and the like. By way of illustration and not limitation, RAM can take many forms, such as Static Random Access Memory (SRAM) or Dynamic Random Access Memory (DRAM), among others. The databases referred to in various embodiments provided herein may include at least one of relational and non-relational databases. The non-relational database may include, but is not limited to, a block chain based distributed database, and the like. The processors referred to in the embodiments provided herein may be general purpose processors, central processing units, graphics processors, digital signal processors, programmable logic devices, quantum computing based data processing logic devices, etc., without limitation.

The technical features of the above embodiments can be arbitrarily combined, and for the sake of brevity, all possible combinations of the technical features in the above embodiments are not described, but should be considered as the scope of the present specification as long as there is no contradiction between the combinations of the technical features.

The above-mentioned embodiments only express several embodiments of the present application, and the description thereof is more specific and detailed, but not construed as limiting the scope of the present application. It should be noted that, for a person skilled in the art, several variations and modifications can be made without departing from the concept of the present application, which falls within the scope of protection of the present application. Therefore, the protection scope of the present application should be subject to the appended claims.

Claims

1. A signal transmission method is characterized in that the signal transmission method is applied to a mainboard of a server, and the mainboard is connected with a back plate of the server through a data signal line; the method comprises the following steps:

setting the state of the data signal line to a clock start state;

2. The method of claim 1, wherein setting the state of the data signal line to a clock start state comprises:

setting the state of the data signal line to a clock start state in a first clock cycle of each transmission cycle of a data transmission phase;

setting the state of the data signal line according to a data bit of first transmission data from the second clock cycle of the transmission cycle to transmit the first transmission data to the backplane;

releasing the data signal line at a last clock cycle of the transmission cycle.

3. The method of claim 2, wherein setting the state of the data signal line according to the data bit of the first transmission data comprises:

if the data bit of the first sending data is a first numerical value, setting the state of the data signal line to be a high-impedance state;

and if the data bit of the first sending data is a second value, setting the state of the data signal line to be a low level state.

4. A method according to claim 2 or 3, characterized in that the method further comprises:

starting a first counter to count each time when the last clock cycle of the transmission cycle is reached, and determining whether the count value of the first counter reaches the length of the first sending data;

if so, entering a data receiving stage, setting the state of the data signal line to be a clock starting state in a first clock cycle of each transmission cycle of the data receiving stage, determining a data bit of first received data according to the state of the signal data line from a second clock cycle of each transmission cycle of the data receiving stage so as to receive the first received data from the backboard, and releasing the data signal line in a last clock cycle of each transmission cycle of the data receiving stage;

and if not, re-entering the first clock cycle of the next transmission cycle, and setting the state of the data signal line as the clock starting state.

5. The method of claim 4, wherein determining the data bit of the first received data based on the state of the signal data line comprises:

if the state of the signal data line is a high-impedance state, determining that the data bit of the first received data is a first numerical value;

and if the state of the signal data line is a low level state, determining that the data bit of the first received data is a second numerical value.

6. The method of claim 5, further comprising:

starting a second counter to count when the last clock cycle of each transmission cycle of the data receiving stage is reached each time, and determining whether the count value of the second counter reaches the length of the first received data;

if so, entering a data confirmation stage, pulling down the data signal line, and determining whether the data transmission is complete according to the length of the first sending data and the length of the first receiving data; if the data transmission is determined to be complete, storing the first received data, and entering an idle stage; if the data is determined not to be completely transmitted, discarding the first received data, and re-entering the data sending stage to send new first sent data;

7. A signal transmission method is characterized in that the signal transmission method is applied to a backboard of a server, and the backboard is connected with a main board of the server through a data signal line; the method comprises the following steps:

detecting the state of the data signal line;

8. The method of claim 7, wherein the performing signal transmission with the motherboard through the data signal line when detecting that the data signal line is in a clock start state comprises:

when the data signal line is detected to be converted from the high-impedance state to the low-level state, entering a data receiving stage, starting a low-level counter to count, and when the data signal line is detected to be converted from the low-level state to the high-impedance state, stopping counting of the low-level counter; starting a high-level counter to count, and stopping counting of the high-level counter when the data signal line is detected to be converted from a high-resistance state to a low-level state; and determining a data bit of first receiving data according to the count value of the low-level counter and the count value of the high-level counter so as to receive the first receiving data from the mainboard.

9. The method of claim 8, wherein determining the data bit of the first received data according to the count value of the low level counter and the count value of the high level counter comprises:

if the ratio of the count value in the low-level counter to the count value in the high-level counter is a first preset ratio, determining that the data bit of the first received data is a first numerical value;

and if the ratio of the count value in the low-level counter to the count value in the high-level counter is a second preset ratio, determining that the data bit of the first received data is a second value.

10. The method of claim 9, wherein upon detecting a transition of the data signal line from a high impedance state to a low level state, the method further comprises:

starting a third counter to count and determining whether the count value in the third counter reaches the length of the first received data;

if so, entering a data sending stage, detecting the state of the data signal line, and setting the state of the data signal line according to a data bit of second sending data when detecting that the data signal line is in a clock initial state; releasing the data signal line after the state of the data signal line is maintained within a preset time length;

if not, re-detecting the state of the data signal line, and entering the data receiving stage when detecting that the data signal line is in the clock starting state.

11. The method of claim 10, wherein setting the state of the data signal line according to the data bit of the second transmit data comprises:

if the data bit of the second sending data is the first numerical value, setting the state of the data signal line to be a high-impedance state;

and if the data bit of the second sending data is the second numerical value, setting the state of the data signal line to be a low level state.

12. The method of claim 11, wherein after releasing the data signal line, the method further comprises:

starting a fourth counter to count and determining whether the count value in the fourth counter reaches the length of second sending data;

if so, entering a data confirmation stage;

if not, re-detecting the state of the data signal line, and entering the data sending stage when detecting that the data signal line is in the clock starting state.

13. A computer device comprising a memory and a processor, the memory storing a computer program, characterized in that the processor, when executing the computer program, implements the steps of the method of any of claims 1 to 12.

14. A computer-readable storage medium, on which a computer program is stored, which, when being executed by a processor, carries out the steps of the method of any one of claims 1 to 12.