CN113656340A - Communication control method, system and device of I2C bus - Google Patents
Communication control method, system and device of I2C bus Download PDFInfo
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- G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
- G06F13/38—Information transfer, e.g. on bus
- G06F13/40—Bus structure
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- G06F13/4068—Electrical coupling
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- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
- G06F13/38—Information transfer, e.g. on bus
- G06F13/42—Bus transfer protocol, e.g. handshake; Synchronisation
- G06F13/4282—Bus transfer protocol, e.g. handshake; Synchronisation on a serial bus, e.g. I2C bus, SPI bus
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Abstract
The application provides a communication control method, a system and a device of an I2C bus, wherein the method comprises the following steps: if the falling edge of a first clock signal corresponding to the master device is monitored, setting the first clock signal and a second clock signal corresponding to the slave device to be low level; after the first preset duration, converting the second clock signal from a low level to a high impedance state, and monitoring the state of the second clock signal; and controlling the state of the first clock signal according to the state of the second clock signal. According to the method, under the condition of I2C transparent transmission, the clock signal of the master device can be controlled according to the clock signal of the slave device, the communication failure of the master device and the slave device when the slave device triggers clock extension is avoided, and the stability and the effectiveness of data transmission are improved.
Description
Technical Field
The embodiment of the application relates to the technical field of communication, in particular to a communication control method, a communication control system and a communication control device for an I2C bus.
Background
An Integrated Circuit bus (I2C) is a common serial communication bus. An I2C serial bus typically has two signal lines, one for bidirectional data and one for a clock. The device that controls the bus data transfer is called the master and the device that receives the master command is called the slave. The master device can send a clock signal through the clock line output circuit and decide when to send a control command according to the level of the clock signal. The slave devices typically send or receive signals on the data lines according to a clock signal on the bus, and may also send a low signal to the clock line to pull the clock signal low to extend the bus clock signal period. The process of pulling the clock signal low from the device is called clock stretching.
However, in the case of I2C transparent transmission, since the master device and the slave device are not directly connected, when the slave device initiates a clock extension, the master device cannot respond to the clock extension, and data transmission is suspended, and if the master device still sends an instruction to the slave device at this time, the slave device may not respond to the instruction in time, resulting in communication failure.
Disclosure of Invention
The application provides a communication control method, a system and a device of an I2C bus, under the condition of I2C transparent transmission, the clock signal of a master device can be controlled according to the clock signal of a slave device, the communication failure of the master device and the slave device when the slave device triggers clock extension is avoided, and the stability and the effectiveness of data transmission are improved.
In a first aspect, the present application provides a communication control method for an I2C bus, the method including: if the falling edge of a first clock signal corresponding to the master device is monitored, setting the first clock signal and a second clock signal corresponding to the slave device to be low level; after the first preset duration, converting the second clock signal from a low level to a high impedance state, and monitoring the state of the second clock signal; and controlling the state of the first clock signal according to the state of the second clock signal.
Optionally, controlling the state of the first clock signal according to the state of the second clock signal includes: and if the second clock signal is monitored to be at a low level, setting the first clock signal to be at a low level.
Optionally, after setting the first clock signal to a low level, the method further includes: and setting the second clock signal to be in a high impedance state, and continuously monitoring the state of the second clock signal until the second clock signal is in a high level.
Optionally, controlling the state of the first clock signal according to the state of the second clock signal includes: and if the second clock signal is monitored to be in a high level, setting the first clock signal to be in a high impedance state.
Optionally, the method further comprises: acquiring a first clock signal within a fourth preset time length; determining the duty ratio and the period of the first clock signal according to the first clock signal within the fourth preset time length; and determining a first preset time length according to the duty ratio and the period.
Optionally, monitoring a state of the second clock signal comprises: and monitoring the state of the second clock signal after a second preset time after the second clock signal is set to be in the high impedance state.
In a second aspect, the present application provides a communication control system of an I2C bus, including: the device comprises a master device, a control device and a slave device.
The control device is in communication connection with the master device and the slave device respectively.
The master device is used for sending the first clock signal to the control device.
And the slave device is used for receiving the second clock signal sent by the control device.
And the control equipment is used for monitoring the first clock signal, setting the first clock signal and the second clock signal to be low level if the falling edge of the first clock signal is monitored, converting the second clock signal from the low level to a high impedance state after a first preset time length, monitoring the state of the second clock signal, and controlling the state of the first clock signal according to the state of the second clock signal.
Optionally, the control device is specifically configured to set the first clock signal to a low level if it is monitored that the second clock signal is a low level.
Optionally, the control device is further configured to set the second clock signal to a high impedance state, and continue to monitor a state of the second clock signal until the second clock signal is at a high level.
Optionally, the control device is specifically configured to set the first clock signal to a high impedance state if it is monitored that the second clock signal is at a high level.
Optionally, the control device is further configured to obtain a first clock signal within a fourth preset duration; determining the duty ratio and the period of the first clock signal according to the first clock signal within the fourth preset time length; and determining a first preset time length according to the duty ratio and the period.
Optionally, the control device is specifically configured to monitor a state of the second clock signal after a second preset duration after the second clock signal is set to the high impedance state.
In a third aspect, the present application provides a communication control apparatus for an I2C bus, the apparatus including:
and the monitoring module is used for setting the first clock signal and the second clock signal corresponding to the slave device to be low level if the falling edge of the first clock signal corresponding to the master device is monitored.
And the control module is used for switching the second clock signal from the low level to the high impedance state after the first preset duration.
And the monitoring module is also used for monitoring the state of the second clock signal after a second preset time length.
And the control module is also used for controlling the first clock signal according to the state of the second clock signal.
Optionally, the control module is specifically configured to set the first clock signal to a low level if it is monitored that the second clock signal is a low level.
Optionally, the control module is further configured to set the second clock signal to a high impedance state.
And the monitoring module is further used for continuously monitoring the state of the second clock signal until the second clock signal is at a high level.
Optionally, the control module is specifically configured to set the first clock signal to a high impedance state if it is monitored that the second clock signal is at a high level.
Optionally, the control module is further configured to obtain a first clock signal within a fourth preset duration; determining the duty ratio and the period of the first clock signal according to the first clock signal within the fourth preset time length; and determining a first preset time length according to the duty ratio and the period.
Optionally, the monitoring module is further configured to monitor a state of the second clock signal after a second preset duration after the second clock signal is set to the high impedance state.
In a fourth aspect, the present application provides an electronic device comprising: at least one processor; and a memory communicatively coupled to the at least one processor; wherein the memory stores instructions executable by the at least one processor to enable the at least one processor to perform the method of the first aspect or the alternatives of the first aspect.
In a fifth aspect, the present application provides a computer readable storage medium having stored thereon computer executable instructions for performing a method as the first aspect or an alternative to the first aspect when executed by a processor.
The application provides a communication control method, a system and a device of an I2C bus, wherein the method comprises the steps of setting a first clock signal and a second clock signal corresponding to slave equipment to be low level if the falling edge of the first clock signal corresponding to master equipment is monitored, converting the low level of the second clock signal into a high impedance state after a first preset duration, and monitoring the state of the second clock signal; the state of the first clock signal is controlled according to the state of the second clock signal, the clock signal of the master device can be controlled according to the clock signal of the slave device, communication failure between the master device and the slave device when the slave device triggers clock extension is avoided, and stability and effectiveness of data transmission are improved.
Drawings
Fig. 1 is a schematic diagram of an application scenario of a communication control method of an I2C bus provided in the present application;
fig. 2 is a schematic flowchart of a communication control method of an I2C bus provided in the present application;
FIG. 3 is a schematic flow chart of another communication control method for an I2C bus provided by the present application;
FIG. 4 is a timing diagram of an I2C clock signal provided herein;
fig. 5 is a schematic structural diagram of a communication control system of an I2C bus provided in the present application;
fig. 6 is a schematic structural diagram of a communication control device of an I2C bus provided by the present application;
fig. 7 is a schematic structural diagram of an electronic device provided in the present application.
With the foregoing drawings in mind, certain embodiments of the disclosure have been shown and described in more detail below. These drawings and written description are not intended to limit the scope of the disclosed concepts in any way, but rather to illustrate the concepts of the disclosure to those skilled in the art by reference to specific embodiments.
Detailed Description
Reference will now be made in detail to the exemplary embodiments, examples of which are illustrated in the accompanying drawings. When the following description refers to the accompanying drawings, like numbers in different drawings represent the same or similar elements unless otherwise indicated. The implementations described in the exemplary embodiments below are not intended to represent all implementations consistent with the present disclosure. Rather, they are merely examples of apparatus and methods consistent with certain aspects of the present disclosure, as detailed in the appended claims.
An Integrated Circuit bus (I2C) is a serial communication bus. An I2C serial bus typically has two signal lines, one being a bidirectional data line and the other being a bidirectional clock line. As a master device controlling the bus data transfer, on the one hand, a clock signal is sent through a clock line output circuit, and on the other hand, the level of the clock signal on the bus is detected to determine when to send the next clock pulse level. The slave device receiving the command from the master device may send or receive a signal on the data line according to a clock signal on the bus, or may send a low level signal to the clock line to extend the period of the bus clock signal. For example, when the slave needs to perform other tasks, or when the rate of the slave does not keep up with the master, the slave may pull the clock signal low, suspend data transmission with the master, and not resume data transmission between the master and the slave until the slave releases the clock signal. The process of pulling the clock signal low from the device is called clock stretching. However, in the case of I2C transparent transmission, since the master device and the slave device are not directly connected, when the slave device initiates a clock extension, the master device cannot respond to the clock extension, and data transmission is suspended, and if the master device still sends an instruction to the slave device at this time, the slave device may not respond to the instruction in time, resulting in communication failure.
If the clock of the master device can be controlled when the slave device initiates the clock extension, the master device can be controlled to suspend data transmission, so that the reliability of data transmission between the master device and the slave device is guaranteed.
Based on this, the present application provides a communication control method of an I2C bus, which is applied to an electronic device connected in series between a master device and a slave device, that is, the electronic device is connected in series between an I2C clock signal port of the master device and an I2C clock signal port of the slave device, and which can realize I2C passthrough. After the device is powered on, a port of the electronic device, which is connected with an I2C clock signal of the main device, is set to be in a high impedance state during initialization so as to monitor the state of the clock signal of the main device. When the falling edge of the clock signal of the master device is monitored, the clock of the master device and the clock of the slave device are controlled to be in low level, and timing is started. In general, the clock signal is a square wave signal, and is low for half a clock cycle and high for half a clock cycle. Therefore, by monitoring whether the clock signal of the slave device jumps to the high-point level after half a clock cycle, it can be determined whether the slave device has triggered the clock stretching. Based on this, after half a clock cycle, the electronic device sets the clock of the slave device to a high impedance state, and releases the control right of the clock to monitor the state of the clock signal of the slave device. If the clock signal of the slave equipment is monitored to be changed into high level, the slave equipment does not extend the clock, the clock signal of the master equipment is set to be in a high impedance state, and the control right of the clock signal of the master equipment is released; if the clock signal of the slave equipment is monitored to be changed into low level, the clock signal of the slave equipment is still controlled to be low level, the state of the clock signal of the slave equipment is continuously monitored, the clock signal of the master equipment is set to be in a high impedance state until the clock signal of the slave equipment jumps to be high point level, and the control right of the clock signal of the master equipment is released. By the method, when the slave device triggers clock extension under the condition that the electronic device transparently transmits I2C, the electronic device can timely control the clock signal of the master device to keep a low level state, further suspend communication between the master device and the slave device, and release the control right of the clock signal of the master device after the slave device finishes the clock extension so as to enable the master device and the slave device to recover normal communication.
Fig. 1 is a schematic diagram of an application scenario of a communication control method of an I2C bus provided in the present application, as shown in fig. 1, the scenario includes: a master device 11, an electronic device 12 and a slave device 13.
The electronic device 12 is connected to the master device 11 and the slave device 12 via an I2C bus, respectively. When the master device 11 and the slave device 13 communicate via the I2C bus, the electronic device 13 may pass through the relevant data.
The electronic Device 12 may specifically include a Programmable Logic Device (FPGA), a Complex Programmable Logic Device (CPLD), and other devices having a control function.
Fig. 2 is a schematic flowchart of a communication control method of an I2C bus provided in the present application, where the method is applied to an electronic device, and as shown in fig. 2, the method includes:
s201, if the falling edge of the first clock signal corresponding to the master device is monitored, setting the first clock signal and the second clock signal corresponding to the slave device to be low level.
Specifically, a master device generally refers to a device that issues a primary command; a slave device generally refers to a device that receives a command.
The first clock signal is an I2C clock signal corresponding to the master device; the second clock signal is the slave's corresponding I2C clock signal.
S202, after the first preset duration, converting the second clock signal from a low level to a high impedance state, and monitoring the state of the second clock signal.
The first preset duration may be a specific duration set by a user; the electronic device may also be determined based on the duty cycle and the period of the first clock signal. Specifically, the first preset time duration may be a time duration corresponding to a low level of the clock signal in one clock cycle.
In general, the clock signal of the I2C bus is a square wave, and accordingly, the first predetermined duration is half a clock cycle. The user can finish timely by setting a timer inside the electronic equipment.
And S203, controlling the state of the first clock signal according to the state of the second clock signal.
If the second clock signal is at low level, controlling the first clock signal to be at low level; and if the second clock signal is in a high-point flat state, controlling the first clock signal to be in a high-impedance state, releasing the control right of the first clock signal, and enabling the master device to control the state of the first clock signal.
According to the method and the device, if the falling edge of a first clock signal corresponding to the master device is monitored, the first clock signal and a second clock signal corresponding to the slave device are set to be low level, after a first preset time length, the second clock signal is converted from the low level to a high impedance state, and the state of the second clock signal is monitored; the state of the first clock signal is controlled according to the state of the second clock signal, and under the condition of I2C transparent transmission, the clock signal of the master device can be controlled according to the clock signal of the slave device, so that the communication failure between the master device and the slave device when the slave device triggers clock extension is avoided, and the stability and effectiveness of data transmission are improved.
Fig. 3 is a schematic flowchart of another communication control method for an I2C bus provided in the present application, where the method is applied to an electronic device, and as shown in fig. 3, the method includes:
s301, if the falling edge of the first clock signal corresponding to the master device is monitored, setting the first clock signal and the second clock signal corresponding to the slave device to be low level.
S301 and S201 have the same technical features, and specific description may refer to S201, which is not described herein again.
If the electronic device is just powered on, before performing S301, the method further includes setting the first clock signal to a high impedance state, that is, setting a state of a port of the electronic device, which is used for receiving the first clock signal corresponding to the master device, to the high impedance state. Through the arrangement, the port state of the electronic equipment can change along with the change of the first clock signal corresponding to the main equipment, and the first clock signal can be further monitored.
If a falling edge of the first signal is detected, it indicates that the first clock signal is to be entered into a low state, and thus, the states of both the first clock signal and the second clock signal are set to a low level.
Fig. 4 is a timing diagram of an I2C clock signal provided by the present application, and as shown in fig. 4, if a falling edge of a first clock signal corresponding to a master device is detected, both the first clock signal and a second clock signal corresponding to a slave device are set to a low level.
S302, after the first preset duration, converting the second clock signal from a low level to a high impedance state, and monitoring the state of the second clock signal.
S302 and S202 have the same technical features, and for the specific description, reference may be made to S202, which is not described herein again.
The clock signal is usually a signal with alternating high and low levels, and the first preset duration is specifically a duration of the low level of the first clock signal in one clock cycle. Typically, the clock signal is a square wave signal with a 50% duty cycle, and the first preset duration may be set to be half a clock period based on this.
The duty ratios of the clock signals are different, and the corresponding durations in the low level state are also different.
Optionally, the method further comprises: acquiring a first clock signal within a fourth preset time length; determining the duty ratio and the period of the first clock signal according to the first clock signal within the fourth preset time length; and determining a first preset time length according to the duty ratio and the period.
Specifically, the fourth preset time period should be longer than the period of the first clock signal.
By the method, the period and the duty ratio of the first clock signal can be determined, and then the corresponding first preset time length can be determined according to the period and the duty ratio.
Optionally, monitoring the state of the second clock signal comprises: and monitoring the state of the second clock signal after a second preset time after the second clock signal is set to be in the high impedance state.
By setting the second preset time length, the time allowance can be reserved for pulling down the clock signal of the slave equipment, the accuracy of the monitoring result is improved, and the accuracy of control is improved.
The second clock signal is set to be in a high impedance state, which is essentially that the electronic device sets a port, connected with the second clock signal corresponding to the slave device, to be in the high impedance state, and then the state of the port can change along with the change of the second clock signal, that is, the state of the second clock signal can be monitored.
With continued reference to fig. 4, the second predetermined duration shown in fig. 4 is one-eighth of a clock cycle, i.e., 1/8 Tscl. The electronic device monitors the state of the second clock signal for a duration of 1/8Tscl after setting the second clock signal to the high impedance state.
S303, if the second clock signal is monitored to be in a low level, executing S304; if the second clock signal is detected to be high, S306 is executed.
S304, continuously setting the first clock signal to be in a low level.
S305, setting the second clock signal to be in a high impedance state, and continuously monitoring the state of the second clock signal until the second clock signal is in a high level.
With reference to fig. 4, assuming that the first preset duration is half a clock cycle, after half a clock cycle, that is, after 1/2Tscl, if it is detected that the second clock signal is still at a low level, it indicates that the slave device pulls down the clock signal, that is, the slave device triggers clock extension, and the state of the first clock signal is not changed, but the first clock signal is still set at a low level. When the second clock signal jumps from low level to high point level, it indicates that the slave device is finished clock stretching.
S306, setting the first clock signal to be in a high impedance state.
Continuing with fig. 4, if it is detected that the second clock signal is high-flat, indicating that the slave device does not pull down the clock signal, setting the first clock signal to a high impedance state, releasing the control right of the state of the first clock signal, and the master device controlling the state of the first clock signal. The master device may continue to communicate with the slave device. The electronic device sets the first clock signal to a high impedance state to detect the state of the first clock signal. And when the falling edge of the next first clock signal is monitored, the steps are executed again, and the first clock signal is controlled for a new round.
On the basis of the above embodiment, if it is monitored that the second clock signal is at a low level, setting the second clock signal to a high impedance state, and continuing to detect the state of the second clock signal until the second clock signal is at a high level, so that when the slave device triggers clock extension, the clock signal of the master device is controlled to be at a low level, and communication between the master device and the slave device is suspended; if the second clock signal is monitored to be in a high level, the first clock signal is set to be in a high impedance state so as to release the control right of the first clock signal, the master device controls the state of the first clock signal, and further the master device and the slave device can continue to communicate, communication failure caused by the fact that the slave device triggers clock extension in the communication process of the master device and the slave device under the condition of transparent transmission is avoided, and stability and effectiveness of data transmission are improved.
Fig. 5 is a schematic structural diagram of a communication control system of an I2C bus provided in the present application, and as shown in fig. 5, the system includes: a master device 51, a control device 52 and a slave device 53.
The control device 52 is communicatively connected to the master device 51 and the slave device 53, respectively.
A master device 51 for sending a first clock signal to a control device 52.
The slave device 51 is used for receiving the second clock signal sent by the control device 52.
The control device 52 is configured to monitor the first clock signal, set the first clock signal and the second clock signal to be low levels if a falling edge of the first clock signal is monitored, convert the second clock signal from the low level to a high impedance state after a first preset time duration, monitor a state of the second clock signal, and control a state of the first clock signal according to the state of the second clock signal.
Optionally, the control device 52 is specifically configured to, if it is detected that the second clock signal is at a low level, continue to set the first clock signal to a low level.
Optionally, the control device 52 is further configured to set the second clock signal to a high impedance state, and continue to monitor the state of the second clock signal until the second clock signal is at a high level.
Optionally, the control device 52 is specifically configured to set the first clock signal to a high impedance state if it is detected that the second clock signal is at a high level.
Optionally, the control device 52 is further configured to obtain a first clock signal within a fourth preset time duration; determining the duty ratio and the period of the first clock signal according to the first clock signal within the fourth preset time length; and determining a first preset time length according to the duty ratio and the period.
Optionally, the control device 52 is specifically configured to monitor the state of the second clock signal after a second preset time period after the second clock signal is set to the high impedance state.
The system can implement the method, and the content and effect thereof can refer to the embodiment of the method, which is not described again.
Fig. 6 is a schematic structural diagram of a communication control device of an I2C bus provided in the present application, and as shown in fig. 6, the device includes:
the monitoring module 61 is configured to set the first clock signal and the second clock signal corresponding to the slave device to a low level if a falling edge of the first clock signal corresponding to the master device is monitored.
And the control module 62 is configured to convert the second clock signal from the low level to the high impedance state after the first preset time duration.
The monitoring module 61 is further configured to monitor a state of the second clock signal after a second preset time period.
The control module 62 is further configured to control the first clock signal according to a state of the second clock signal.
Optionally, the control module 62 is specifically configured to, if it is detected that the second clock signal is at a low level, continue to set the first clock signal to a low level.
Optionally, the control module 62 is further configured to set the second clock signal to a high impedance state.
The monitoring module 61 is further configured to continue monitoring the state of the second clock signal until the second clock signal is at a high level.
Optionally, the control module 62 is specifically configured to set the first clock signal to a high impedance state if it is detected that the second clock signal is at a high level.
Optionally, the control module 62 is further configured to obtain a first clock signal within a fourth preset time duration; determining the duty ratio and the period of the first clock signal according to the first clock signal within the fourth preset time length; and determining a first preset time length according to the duty ratio and the period.
Optionally, the monitoring module 62 is further configured to monitor the state of the second clock signal after a second preset time period after the second clock signal is set to the high impedance state.
The device can execute the method, and the content and effect thereof can refer to the embodiment part of the method, which is not described again.
Fig. 7 is a schematic structural diagram of an electronic device provided in the present application, and as shown in fig. 7, the electronic device includes: a processor 71, a memory 72; the processor 71 is communicatively connected to the memory 72. The memory 72 is used to store computer programs. The processor 71 is adapted to call a computer program stored in the memory 72 to implement the method in the above-described method embodiment.
Optionally, the electronic device further comprises: a transceiver 73 for enabling communication with other devices.
The electronic device can execute the method, and the content and effect of the method can refer to the embodiment of the method, which is not described again.
The present application also provides a computer-readable storage medium having stored therein computer-executable instructions for implementing the above method when executed by a processor.
The content and effect of the method can be referred to in the embodiment section of the method, and details are not repeated here.
Other embodiments of the disclosure will be apparent to those skilled in the art from consideration of the specification and practice of the disclosure disclosed herein. This application is intended to cover any variations, uses, or adaptations of the disclosure following, in general, the principles of the disclosure and including such departures from the present disclosure as come within known or customary practice within the art to which the disclosure pertains. It is intended that the specification and examples be considered as exemplary only, with a true scope and spirit of the disclosure being indicated by the following claims. It will be understood that the present disclosure is not limited to the precise arrangements described above and shown in the drawings and that various modifications and changes may be made without departing from the scope thereof. The scope of the present disclosure is limited only by the appended claims.
Claims (10)
1. A communication control method for an I2C bus, comprising:
if the falling edge of a first clock signal corresponding to the master device is monitored, setting the first clock signal and a second clock signal corresponding to the slave device to be low level;
after a first preset time, converting the low level of the second clock signal into a high impedance state, and monitoring the state of the second clock signal;
and controlling the state of the first clock signal according to the state of the second clock signal.
2. The method of claim 1, wherein controlling the state of the first clock signal according to the state of the second clock signal comprises:
and if the second clock signal is monitored to be at a low level, continuing to set the first clock signal to be at the low level.
3. The method of claim 2, wherein after the setting the first clock signal low, the method further comprises:
and setting the second clock signal to be in a high impedance state, and continuously monitoring the state of the second clock signal until the second clock signal is in a high level.
4. The method of claim 1, wherein controlling the state of the first clock signal according to the state of the second clock signal comprises:
and if the second clock signal is monitored to be in a high level, setting the first clock signal to be in a high impedance state.
5. The method according to any one of claims 1-4, further comprising:
acquiring the first clock signal within a fourth preset time length;
determining the duty ratio and the period of the first clock signal according to the first clock signal within the fourth preset time length;
and determining the first preset time according to the duty ratio and the period.
6. The method of claim 3, wherein monitoring the state of the second clock signal comprises:
and monitoring the state of the second clock signal after a second preset time after the second clock signal is set to be in the high impedance state.
7. A communication control system of an I2C bus, comprising: a master device, a control device and a slave device;
the control device is in communication connection with the master device and the slave device respectively;
the master device is used for sending a first clock signal to the control device;
the slave device is used for receiving a second clock signal sent by the control device;
the control device is configured to monitor the first clock signal, set the first clock signal and the second clock signal to a low level if a falling edge of the first clock signal is monitored, convert the second clock signal from the low level to a high impedance state after a first preset time duration, monitor a state of the second clock signal, and control the state of the first clock signal according to the state of the second clock signal.
8. A communication control apparatus of an I2C bus, comprising:
the monitoring module is used for setting the first clock signal and a second clock signal corresponding to the slave device to be low level if the falling edge of the first clock signal corresponding to the master device is monitored;
and the control module is used for switching the second clock signal from the low level to a high impedance state after a first preset time length, monitoring the state of the second clock signal after a second preset time length, and controlling the state of the first clock signal according to the state of the second clock signal.
9. A control apparatus, characterized by comprising:
at least one processor; and
a memory communicatively coupled to the at least one processor; wherein the content of the first and second substances,
the memory stores instructions executable by the at least one processor to enable the at least one processor to perform the method of any one of claims 1 to 6.
10. A readable storage medium, characterized in that the readable storage medium has stored thereon a computer program which, when being executed by a processor, carries out the method according to any one of claims 1 to 6.
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| CN202110959742.7A CN113656340A (en) | 2021-08-20 | 2021-08-20 | Communication control method, system and device of I2C bus |
| PCT/CN2021/128509 WO2023019753A1 (en) | 2021-08-20 | 2021-11-03 | Communication control method, system and apparatus for i2c bus |
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| CN202110959742.7A CN113656340A (en) | 2021-08-20 | 2021-08-20 | Communication control method, system and device of I2C bus |
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