CN109710556A - Slave device and method for serial communication - Google Patents
Slave device and method for serial communication Download PDFInfo
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- CN109710556A CN109710556A CN201811501631.6A CN201811501631A CN109710556A CN 109710556 A CN109710556 A CN 109710556A CN 201811501631 A CN201811501631 A CN 201811501631A CN 109710556 A CN109710556 A CN 109710556A
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
- G06F13/38—Information transfer, e.g. on bus
- G06F13/42—Bus transfer protocol, e.g. handshake; Synchronisation
- G06F13/4282—Bus transfer protocol, e.g. handshake; Synchronisation on a serial bus, e.g. I2C bus, SPI bus
- G06F13/4291—Bus transfer protocol, e.g. handshake; Synchronisation on a serial bus, e.g. I2C bus, SPI bus using a clocked protocol
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
- G06F13/38—Information transfer, e.g. on bus
- G06F13/42—Bus transfer protocol, e.g. handshake; Synchronisation
Abstract
A kind of slave device and method for serial communication are disclosed, this method comprises: receiving serial clock signal via clock signal terminal；Data are received via data input pin, the data include multiple continuous position data；It is synchronous with clock signal of system, the data are shifted to obtain a data；And it is synchronous with the serial clock signal, latch institute's bit data, and the position data that at least part latches are sent via data output end, wherein, the serial clock signal and the clock signal of system are respectively provided with the first clock cycle and second clock period, and first clock cycle is greater than the second clock period.This method shift amount evidence synchronous with clock signal of system, the position data that latch synchronous with serial clock signal and transmission shift in advance, it is transferred to before sending edge to which the data preparation time will be sent, so that system clock/serial clock signal frequency ratio is lower, so as to improve transmission rate.
Description
Technical field
The present invention relates to data communication technology fields, and in particular to a kind of slave device and method for serial communication.
Background technique
In the prior art, SPI (Serial Peripheral Interface, Serial Peripheral Interface (SPI)) sends number from equipment
According to a kind of conventional design method structural block diagram it is as shown in Figure 1.SPI is received via clock signal terminal SCLK from equipment 100 and is gone here and there
Row clock signal SCLK receives data via data input pin MOSI, and sends data via data output end MISO.SPI
The system clock (SYSCLK) of one higher than SPI serial clock (SCLK) frequency several times inside from equipment, in Edge check mould
Block 110 is synchronous and detects the edge SPI serial clock signal SCLK, also referred to as transmission edge, i.e. the rising of serial clock signal SCLK
The jump of edge or failing edge, obtained transmission is along signal.The transmission, as enable signal ENTX, only maintains a system along signal
The high level in clock SYSCLK period is effective.Logic module 120 reads data from memory module 130 according to enable signal, and
And displacement output one is sent data on data output end MISO, and has been exported in one group of data (usually 8bit) displacement
Bi Hou is sent from memory next group of data of taking-up and again displacement.
Fig. 2 is the waveform diagram that this method SPI mode 0 sends data.As shown, SPI serial clock usually only exists
(CS valid period) works when SPI transmits data, and other times, which are kept fixed level, which not to be changed, (can also use CS even if changing
It gates).SPI mode 0, which needs to send in first SPI serial clock, gets out a data before arriving, and is output to
On data output end MISO.Before the arrival of SPI serial clock, it is not available SPI serial clock and is carried out from memory read data
The transmission of a data, therefore data are sent usually using clock signal of system SYSCLK.
There is some shortcomings for this data transmission method for uplink.In Fig. 2, from the transmission edge of SPI serial clock to system clock
SYSCLK cross clock domain it is synchronous and detect SPI serial clock transmission along skip signal, use the skip signal to believe as enabled
Number ENTX shifts output data, this segment data prepare delay Ta (MISO data prepare delay) and be usually 2~3 be
Unite clock SYSCLK period (TSYSCLK).Another delay is data transmission delay Tb (MISO PAD/ on PAD/board
board delay).Half period (the T of SPI serial clockSCLK/ 2) data preparation delay Ta and data are subtracted to pass in PAD/board
Defeated delay Tb (MISO PAD/board delay) is exactly settling time Tc (MISO setup of the output data in receiving end
time).In one project, data PAD/board transmission delay Tb be fixed, bigger data preparation delay Ta will so that
Output data settling time Tc is smaller, limits the raising of transmission rate.
It is required to meet settling time of the output data in receiving end, in SPI serial clock frequency (i.e. transmission rate)
(i.e. T in the case where certainSCLK/ 2 is certain), the higher clock signal of system SYSCLK of frequency is needed, is prolonged with reducing data preparation
Slow Ta；In other words in the case where clock signal of system SYSCLK frequency is certain, the highest frequency for the SPI serial clock that can be supported
It is lower；The frequency proportions that this all shows as system clock SYSCLK/ serial clock SCLK are higher.
Summary of the invention
In view of the above problems, the purpose of the present invention is to provide a kind of slave device and method for serial communication, thus
The frequency proportions for reducing system clock SYSCLK/ serial clock signal SCLK, obtain better output data settling time.
According to an aspect of the present invention, a kind of serial communication method for from equipment is provided, comprising:
Serial clock signal is received via clock signal terminal；
Data are received via data input pin, the data include multiple continuous position data；
It is synchronous with clock signal of system, the data are shifted to obtain a data；And
It is synchronous with the serial clock signal, institute's bit data is latched, and send at least one via data output end
Divide the position data latched,
Wherein, the serial clock signal and the clock signal of system are respectively provided with the first clock cycle and second clock
Period, first clock cycle are greater than the second clock period.
Optionally, in the continuous cycles of the serial clock signal, the selection position data of the data are carried out respectively
Displacement and latch and transmission.
Optionally, further includes: driving clock signal is generated according to the serial clock signal, wherein in the driving
The edge of clock signal sends institute's bit data.
Optionally, the driving clock signal is obtained by the serial clock signal by gate and/or phse conversion.
Optionally, the step of shifting to the data include:
In the first clock cycle of the serial clock signal, postpone at least one second clock period, to obtain
The enable signal synchronous with the clock signal of system；And
According to the enable signal, the data are shifted to obtain a data.
Optionally, further includes: according to the enable signal, institute's bit data is shifted to obtain a data,
And a data is latched, and send a data latched.
Optionally, further includes: selection signal is obtained according to the serial clock signal, for selectively by the data
A data and remaining data offer sent to data output end.
Optionally, it according to the operating mode from equipment, is sent out in the rising edge or failing edge of the serial clock signal
Send institute's bit data.
Optionally, according to the operating mode from equipment, before first edge of the serial clock signal or
The a data is sent later.
According to another aspect of the present invention, a kind of slave equipment for serial communication is provided, it is described from equipment via clock
Signal end receives serial clock signal, receives data via data input pin, and send the data via data output end,
It is characterized in that, described include: from equipment
Memory module, for storing the data；
Logic module is coupled with memory module, for synchronous with clock signal of system, is shifted the data to obtain
Obtain position data；
First latch module is coupled with logic module, for latching a data of the data；
Second latch module is coupled with logic module, for latching remaining data of the data；
Selection signal generation module, for obtaining the selection signal synchronous with the serial clock signal；
Selecting module is coupled with the first latch module, the second latch module and selection signal generation module, for according to choosing
It selects signal and one of a data and remaining described data is provided to the data output end,
Wherein, the serial clock signal and the clock signal of system are respectively provided with the first clock cycle and second clock
Period, first clock cycle are greater than the second clock period.
Optionally, further includes: Edge check module, for prolonging in the first clock cycle of the serial clock signal
At least one slow second clock period, to obtain the enable signal synchronous with the clock signal of system.
Optionally, further includes: clock module, for being obtained to the serial clock signal by gate and/or phse conversion
To driving clock signal,
Wherein, the selection signal generation module generates the selection according to the Edge check of the driving clock signal and believes
Number.
Optionally, the logic module is displaced to described the according to from the selection of the operating mode of equipment by first position data
One latch module or second latch module.
Optionally, first latch module includes trigger and control logic, for latching and exporting a data.
Optionally, second latch module, including trigger, the driving clock signal act on the clock of trigger
End, for latching and exporting remaining data.
Optionally, the selection signal generation module includes trigger and control logic module, is used for control selections signal.
A kind of slave device and method for serial communication provided according to the present invention, have the following advantages that or benefit: using
System clock SYSCLK, according to the edge serial clock signal SCLK detected, also referred to as transmission edge, i.e. serial clock signal
SCLK rising edge or failing edge, in advance displacement get out position data pending, and serial clock signal SCLK is used when sending along arrival
The clock latches and sends out the outgoing data, and the selection output of chosen device along transmission trigger is acted on.In this way, will hair
It send the preparation Branch-delay of data to arrive transmission before arriving, sends data to up to receiving end and there was only transmission delay (PAD/
Board delay), to obtain best transmission data setup time, reduce system clock SYSCLK/ serial clock letter
The frequency proportions of number SCLK.
Further, it is the serial clock signal detected according to system clock SYSCLK that displacement in advance, which prepares outgoing data,
SCLK is sent along what is carried out, and maximum delay time is 3 system clock SYSCLK periods, as long as serial clock signal SCLK
Two transmissions are greater than 3 system clock SYSCLK periods along interval (i.e. period), (are pressed with the transmission edge of serial clock signal SCLK
Mode conversion be driving clock signal GSCLK) directly latch and send system clock SYSCLK shift in advance it is ready pending
Data, it is sufficient to meet the settling time for sending trigger and the retention time requires, it is ensured that the correct transmission of data.
Further, memory module is operated with system clock SYSCLK, solves before SPI transmission starts and believes without serial clock
The problem of a data reads, prepares, sending in the case of number SCLK and memory module are in no serial clock signal SCLK
The manipulation problem (such as empty, synchronize) of period.
Further, increase a data latch module, solve in SPI different mode a data at first
Serial clock signal SCLK sends the problem of sending before, and a data latch module only uses a trigger, expense
It is minimum.
Further, increase shifted data latch and sending module, it is ensured that every transmission data are in each serial clock
Signal SCLK, which is sent, just sends out the transmission position data after, ensure that and sends data in the retention time (hold of receiving end
Time), it is ensured that data transmission is unlikely to misplace, and shifted data latches and sending module only uses a trigger, expense pole
It is small.
Further, selection signal generation module and selecting module are increased, it is ensured that in different mode, selecting module choosing
Correct shift amount is selected according to output.
Detailed description of the invention
By referring to the drawings to the description of the embodiment of the present invention, above-mentioned and other purposes of the invention, feature and
Advantage will be apparent from, in the accompanying drawings:
Fig. 1 shows the structural block diagram for the slave equipment of serial communication in the prior art；
Fig. 2 shows in the prior art from the timing diagram of equipment serial communication；
Fig. 3 shows first embodiment of the invention from the flow chart of equipment serial communication method；
Fig. 4 shows second embodiment of the invention from the flow chart of equipment serial communication method；
Fig. 5 shows four kind operating modes of the embodiment of the present invention from equipment serial communication；
Fig. 6 shows structural block diagram of the third embodiment of the invention for the slave equipment of serial communication；
Fig. 7 shows the timing diagram that fourth embodiment of the invention sends data method from equipment SPI mode 0.
Fig. 8 shows the timing diagram that fifth embodiment of the invention sends data method from equipment SPI mode 1.
Specific embodiment
The various embodiments that the present invention will be described in more detail that hereinafter reference will be made to the drawings.In various figures, identical element
It is indicated using same or similar appended drawing reference.For the sake of clarity, the various pieces in attached drawing are not necessarily to scale.
With reference to the accompanying drawings and examples, specific embodiments of the present invention will be described in further detail.
Spi bus is a kind of full duplex, and synchronous peripheral interface bus, which includes 4 signal wires: low level is effective
Slave selection line CS, serial time clock line (SCLK), host input/slave output data line MISO, host output/slave input
Data line MOSI.Since signal wire is few, agreement is simple, relative data rate is high, and substantial portion of integrated chip SPI connects
Mouthful.SPI is worked with master-slave mode, and this mode usually has a main equipment and one or more from equipment, and data are set in principal and subordinate
Data transmit-receive is carried out along a data is sent, is accomplished along a data, transmission is received according to the sampling of SPI serial clock between standby
Full duplex transmission (transmitting-receiving).
CS is chip selection signal, is generated by main equipment, each corresponds to unique CS from equipment, and characterization is set from whether equipment is led
In alternative, usual low level is effective.The CS valid period is only primary effective SPI transmission between master-slave equipment, can transmit multiple groups
Long numeric data.SPI serial clock SCLK is also generated by main equipment, and master-slave equipment presses the sampling edge/transmission of SPI serial clock SCLK
Edge transmits/receives data；Main equipment is sampling the MISO data sent along sampling reception from equipment, sends data to MOSI sending edge
To from equipment；From equipment sampling along sampling receive main equipment send MOSI data, send along send data to MISO to
Main equipment.
It sends along the level jump edge for being clock signal, is rising edge or failing edge, in a timing diagram, send edge
It is the starting point of Time-Series analysis.
Fig. 3 shows first embodiment of the invention from the flow chart of equipment serial communication method, and this method is by from equipment string
Row communication device realizes that specific steps include:
Step S301: receiving serial clock signal and receives data.
Before the chip selection signal CS of SPI from equipment is effective, the serial clock signal SCLK for carrying out autonomous device is received, via
Data access end (MOSI) receives the data to be sent (DATA), and is stored in data memory module.
Serial clock signal SCLK is SPI master system clock signal, is generated by main equipment.
Step S302: it is synchronous with clock signal of system, displacement is carried out to data and obtains position data.
Clock signal of system SYSCLK is SPI from the system clock inside equipment, synchronous with clock signal of system SYSCLK
And the edge of serial clock signal SCLK is detected, obtain enable signal ENBIT.Enable signal ENBIT, which maintains corresponding one, to be had
The period is imitated, effective period of time is since the edge delays first time period of serial clock signal, and effective period of time continues
Second time period, first time period and the second time period respectively include at least one second clock period.Such as: when system
The period of clock signal SYSCLK is the second clock period, and the effective period of time of enable signal ENBIT is compared to serial clock signal
The edge of SCLK has the delay in 2~3 clock signal of system periods, and effective period of time only maintains a system clock cycle
It is effective.
The edge of enable signal ENBIT and the edge synchronization of clock signal of system SYSCLK, at this edge to memory
In data shifted, to obtain a data.
The edge is the level jump edge of clock signal, is rising edge or failing edge, also referred to as transmission edge.
Step S303: it is synchronous with serial clock signal, it latches and sends the position data shifted in advance.
Edge is sent at the edge of serial clock signal SCLK, the position data shifted in advance are latched and sent, are latched
In the second latch module, it is sent to selecting module.
It is clock signal of system SYSCLK synchronous simultaneously that the position data of the pre- displacement, which refer to that this sends along the data sent,
The last data for sending and shifting along the enable signal ENBIT obtained are detected, and clock signal of system SYSCLK is synchronous and detects this
A send then is sent in next transmission along the moment along the data that the enable signal ENBIT obtained is shifted.
Enable signal ENBIT has a delay compared to the edge of serial clock signal SCLK, therefore according to enable signal
And serial clock there is also a delays at edge of the position data that ENBIT is shifted compared to serial clock signal SCLK, i.e.,
Signal is synchronous, latches and the shift amount evidence sent is obtained according to the edge in detection serial clock signal SCLK last period
The position data of enable signal displacement.
Step S304: generating selection signal, and selecting module selects output bit data according to selection signal.
Selection signal SEL is obtained according to serial clock signal SCLK.In first hair of serial clock signal SCLK
It send before arriving, selection signal SEL is 1, and in first transmission after, selection signal SEL is 0.When selection signal SEL is
When 1, selecting module is connected to the first latch output, and when selection signal SEL is 0, it is defeated that selecting module is connected to the second latch
Outlet.
Above-mentioned steps illustrate only after equipment serial communication method is data transmission, i.e., open from first transmission edge
The data transmission stream journey of beginning.Before transmitting data since equipment is formally, i.e., before first transmission edge, this method further include:
Before first transmission edge, what a shift amount evidence prepared, is sent to be sent at first along the moment.According to SPI from
The different selections of equipment mode, this method further include: before preparing what a shift amount evidence in advance, carry out a bit data
Displacement and latch, shifted and be latching to the first latch module, and send it to data before first transmission edge
Output end MISO.
Fig. 4 shows second embodiment of the invention from the flow chart of equipment serial communication method, with the method phase shown in Fig. 3
Compare, Fig. 4 is a preferred embodiment, the difference is that a driving clock signal GSCLK is increased, in driving clock
Edge to shift amount according to being latched and sent, the step of this method includes:
Step S401: receiving serial clock signal and receives data.
Before the chip selection signal CS of SPI from equipment is effective, the serial clock signal SCLK for carrying out autonomous device is received, via
Data access end (MOSI) receives the data to be sent (DATA), and is stored in data memory module.
Serial clock signal SCLK is SPI master system clock signal, is generated by main equipment.
Step S402: driving clock signal is obtained according to serial clock signal.
Increase a module, input as serial clock signal SCLK, export to drive clock signal GSCLK, specifically, driving
Dynamic clock signal GSCLK can be generated by transformation phase and/or gate serial clock signal SCLK.It is only enabled in the CS valid period
Gate allows to drive clock signal GSCLK work.
Step S403: it is synchronous with clock signal of system, displacement is carried out to data and obtains position data.
Clock signal of system SYSCLK is SPI from the system clock inside equipment, synchronous with clock signal of system SYSCLK
And the edge of serial clock signal SCLK is detected, obtain enable signal ENBIT.Enable signal ENBIT, which maintains corresponding one, to be had
The period is imitated, effective period of time is since the edge delays first time period of serial clock signal, and effective period of time continues
Second time period, first time period and the second time period respectively include at least one second clock period.Such as: when system
The period of clock signal SYSCLK is the second clock period, and the effective period of time of enable signal ENBIT is compared to serial clock signal
The edge of SCLK has the delay in 2~3 clock signal of system periods, and effective period of time only maintains a system clock cycle
It is effective.
The edge of enable signal ENBIT and the edge synchronization of clock signal of system SYSCLK, at this edge to memory
In data shifted, to obtain a data.
The edge is the level jump edge of clock signal, is rising edge or failing edge, also referred to as transmission edge.
Step S404: it with driving clock signal synchronization, latches and sends the position data shifted in advance.
Edge is sent at the edge of driving clock signal SCLK, the position data shifted in advance are latched and sent, are latched
In the second latch module, it is sent to selecting module.
It is clock signal of system SYSCLK synchronous simultaneously that the position data of the pre- displacement, which refer to that this sends along the data sent,
The last data for sending and shifting along the enable signal ENBIT obtained are detected, and clock signal of system SYSCLK is synchronous and detects this
A send then is sent in next transmission along the moment along the data that the enable signal ENBIT obtained is shifted.
In a second embodiment, it is obtained due to driving clock by transformation phase and/or gate serial clock signal SCLK, because
The edge of this driving clock and the edge synchronization of serial clock.
Enable signal ENBIT has a delay compared to the edge of serial clock signal SCLK, therefore according to enable signal
There is also a delays at edge of the position data that ENBIT is shifted compared to serial clock signal SCLK.With driving clock letter
Number GSCLK is synchronous, i.e., synchronous with serial clock signal SCLK, latches and the shift amount that sends is according to being according to detecting serial clock
The position data for the enable signal displacement that the edge in signal SCLK last period obtains.
Step S405: generating selection signal, and selecting module selects output bit data according to selection signal.
Selection signal SEL is obtained according to serial clock signal SCLK and driving clock signal GSCLK.In serial clock
Before arriving, selection signal SEL is 1 for first transmission of signal SCLK, in first transmission after, selection signal SEL
It is 0.When selection signal SEL is 1, selecting module is connected to the first latch output, when selection signal SEL is 0, selects mould
Block is connected to the second latch output.
Above-mentioned steps illustrate only after equipment serial communication method is data transmission, i.e., open from first transmission edge
Beginning data transmission stream journey.Before transmitting data since equipment is formally, i.e., before first transmission edge, this method further include:
Before first transmission edge, what a shift amount evidence prepared, is sent to be sent at first along the moment.According to SPI from setting
The different selections of standby mode, this method further include: before preparing what a shift amount evidence in advance, carry out a bit data
It shifts and latches, shifted and be latching to the first latch module, and it is defeated before first transmission edge to send it to data
Outlet MISO.
Fig. 5 shows four kind operating modes of the embodiment of the present invention from equipment serial communication.As shown, when according to system
The phase CPHA and polarity CPOL of clock, are classified as four kinds of working methods.
Mode one (SPI0): polarity CPOL is 0, and phase CPHA is 0,
Mode two (SPI1): polarity CPOL is 0, and phase CPHA is 1,
Mode three (SPI2): polarity CPOL is 1, and phase CPHA is 0,
Mode four (SPI3): polarity CPOL is 1, and phase CPHA is 1,
Polarity CPOL indicates SPI during idle time, and serial clock signal SCLK is high level or low level.If CPOL quilt
It is set as 1, then the clock signal under serial clock signal SCLK pin is high level to the equipment during idle time.When CPOL is set as
It is then exactly the opposite when 0.
Phase CPHA indicates that SPI equipment is when the clock signal on serial clock signal SCLK pin becomes rising edge
Trigger data sampling, or when serial clock signal SCLK becomes failing edge, trigger data is sampled.If CPHA is arranged to 1,
Then SPI equipment trigger data when serial clock signal SCLK becomes failing edge samples, and sends data in rising edge.Work as CPHA
It is set as also exactly the opposite when 0.
In the present invention, the difference of four kinds of modes is also embodied by:
The difference of one: SPI tetra- kind of mode of table
From Fig. 5 and table one as can be seen that the transmission data beat of SPI mode 2 and mode 0 be it is the same, uniquely not
With mode 2 is, it drives the same phase of clock signal GSCLK and serial clock signal SCLK.
SPI mode 1 as the transmission data beat of mode 3, but mode 1 drive clock signal GSCLK and it is serial when
The same phase of clock signal SCLK, mode 3 drive clock signal GSCLK and serial clock signal SCLK reverse phase.
The difference that SPI mode 1 sends data beat with mode 0 is: SPI mode 0 is in first transmission before arriving
A data is sent, and mode 1 then sends a data after in first transmission.
In mode 1 and mode 3, all transmission data are all sent from the second latch module, and selection signal SEL is always
Remain 0.In mode 0 and mode 2, first transmission data comes from the first latch module, remaining sends data and comes from second
Latch module, the level of selection signal SEL are 1 before first transmission edge, remain 0. after in first transmission
Fig. 6 shows structural block diagram of the third embodiment of the invention for the slave equipment of serial communication, which is specially real
Structural block diagram corresponding to flow chart shown in existing Fig. 4.As shown, SPI of the embodiment of the present invention is segmented into system from equipment 200
Clock domain D1 and driving clock signal GSCLK domain D2, further includes clock module 310, selecting module 214.
The system clock domain D1, including Edge check module 110, memory module 130, logic module 120 and the first lock
Storing module 211.
The driving clock domain needs D2 includes the second latch module 212 and selection signal generation module 213.
Edge check module 110 is obtained using the transmission edge of internal system time clock SYSCLK detection serial clock signal SCLK
To maintain an internal system time clock period transmission along enable signal ENBIT.
Memory module 130 stores all data to be sent.
Logic module 120 takes transmission data a group by a group from memory module 130, and obtains one in detection and enable
Signal ENBIT shift sends the bit data BITDATA to the second latch module 212 in data group.
First latch module 211, including a trigger and control logic, use in SPI mode 0 and mode 2, every
Secondary transmission latches this good time and transmits first group of first transmissions data before starting, and in CS effectively first digit of transmission later
According to, and be always maintained in this transmission.
Clock module 310 only enables gate when CS is effective, takes inverted serial clock to believe in SPI mode 0 and mode 3
Number SCLK, mode 1 and mode 2 take same phase serial clock signal SCLK, to obtain driving clock signal GSCLK.Drive clock
Signal GSCLK only works in the CS valid period, and drives the transmission of clock signal GSCLK along corresponding in the various modes of SPI
The transmission edge of serial system clock SCLK, driving the transmission edge of clock signal GSCLK is all rising edge in the various modes, thus
Driving clock domain needs D2 is unified to be worked with rising edge flip-flops.
Second latch module 212, including a trigger drive the transmission edge of clock signal GSCLK to act on trigger
Ready transmission position data BITDATA is shifted in clock end, latch and transmission system clock domain D1 in advance, and via the second lock
The output end of storing module 212 is sent to selecting module 214.
Selection signal generation module 213, including a trigger and control logic, for generating selection signal SEL and selecting
It selects and sends the output of position data, it is required that being, the selection signal of SPI mode 0 and mode 2 is 1, first before first transmission edge
A transmission is 0 after, and is always maintained at 0 to SPI end of transmission；SPI mode 1 and mode 3 always remain as 0.
Selecting module 214, with the output end of the first latch module 211 in selection signal SEL selection system clock domain D1
The fan-out evidence of data or the second latch module 212 in driving clock domain needs D2.Specifically, working as selection signal
SEL selects the fan-out evidence of the first latch module 211 when being 1, select the second latch module 212 when selection signal SEL is 0
Fan-out evidence.
Fig. 7 shows the timing diagram that fourth embodiment of the invention SPI sends data method from equipment SPI mode 0.In conjunction with figure
5, which is divided into two parts, and signal works in system clock domain D1 above dotted line, and dotted line lower signal works in driving
Clock signal GSCLK domain D2.
The driving clock signal GSCLK of SPI mode 0 is the antiphase for taking serial clock signal SCLK.
Before CS becomes low level, in system clock domain D1, first group of data is taken out from memory module 130 from equipment, and
A data is stored in the first latch module of BIT0 211, and shifts and first is sent along data to be sent
BITDATA moves on to the second latch module of BIT1-N 212.Meanwhile system clock domain D1 generates an asynchronous reset signal, resets and drives
Selection signal SEL in dynamic clock signal GSCLK domain D2 is 1.
After CS becomes low level, in driving clock domain D2, first is sent along preceding, and selection signal SEL is 1, selects mould
Block 214 selects the bit 0 of the first latch module of BIT0 211 to be output on MISO as bit 0.First sends along rear, when driving
Clock signal GSCLK is latched via the second latch module 212 and is sent BITDATA to selecting module 214, selection signal SEL transformation
It is 0, selecting module 214 selects the data of the second latch module 212 to be output on MISO.
Meanwhile in system clock domain D1, the transmission edge of system clock SYSCLK detection serial clock signal SCLK is obtained
Enable signal ENBIT, logic module 120 carry out the displacement of a bit data BITDATA, the digit according to enable signal ENBIT
The second latch module 212 is displaced to according to BITDATA.
Specifically as shown in fig. 7, the digit sent before the t0 moment, in the first latch module of BIT0 211 at first
It is had been output on MISO according to bit0, at the t0 moment, drives clock signal GSCLK to latch and send out before transmission starts
Ready bit1, while being also the bit 1 in the second memory module of BIT1-N 212, then selected to export by selecting module 214
It is bit1 on to MISO.
Meanwhile at the t0 moment, serial clock signal SCLK is sent along being detected by system clock SYSCLK, generates enabled letter
Number ENBIT (maintains a system clock SYSCLK period effective period of time), and enable signal ENBIT is in t1 moment shifted data
Bit2 is obtained, gets out data for second transmission edge.
It is sent at second along the t2 moment, drives clock signal GSCLK to latch and send out before transmission starts and have been prepared for
Good bit2, the i.e. bit2 in the second memory module, is then selected to be output on MISO by selecting module 214 as bit2.
Meanwhile at the t2 moment, serial clock signal SCLK is sent along being detected by system clock SYSCLK, generates enabled letter
Number ENBIT, the enable signal obtain bit3 in t3 moment shifted data, send edge for third and get out data.
The t4 moment is that third was sent along the moment, according to above-mentioned beat, goes on to assembly line and sends data.First
After group data are sent, next group of data are taken out from memory and are sent, (CS is got higher into from low up to this SPI end of transmission
In vain).
In transmission process, if the clock cycle of system clock SYSCLK be serial system clock SCLK period at least
Three times, so that it may which, when the transmission of serial system clock signal SCLK is along arrival, data DATA1 to be sent is sufficiently stable, meets
The readiness time T1 of BITDATA.
Fig. 8 shows the timing diagram that fifth embodiment of the invention SPI sends data method from equipment SPI mode 1, as schemed institute
Show, which is divided into two parts, and signal works in system clock domain D1 above dotted line, and dotted line lower signal works in driving
Clock domain needs D2.The driving clock signal GSCLK of SPI mode 1 is the same-phase for taking serial clock signal SCLK.
Before CS becomes low level, in system clock domain D1, first group of data, and handle are taken out from equipment from memory module 130
A data bit 0 is displaced to the second latch module 212.Selection signal SEL always remains as 0.
After CS becomes low level, driving clock domain D2 in, selection signal SEL before and after first transmission edge all
0 is always remained as, selecting module 214 selects the data of the second latch module 212 to be output on MISO according to selection signal SEL.
Simultaneously in system clock domain D1, the transmission edge of system clock SYSCLK detection serial clock signal SCLK is made
Energy signal ENBIT, logic module 120 move the bit data in memory module 130 according to enable signal ENBIT
Position obtains BITDATA, and this bit of data BITDATA is displaced to the second latch module 212.
Specifically as shown in figure 8, being sent before the t0 moment at first, the data displacement in memory module 130 is obtained
BITDATA is obtained, at the t0 moment, drives clock signal GSCLK to latch and sends out the bit0 having had been prepared for before transmission starts, together
When be also bit 0 in the second memory module of BIT1-N 212, then selected to be output on MISO by selecting module 214 as bit0.
Meanwhile at the t0 moment, serial clock signal SCLK is sent along being detected by system clock SYSCLK, generates enabled letter
Number ENBIT (maintains a system clock SYSCLK period effective period of time), and enable signal ENBIT is in t1 moment shifted data
Bit1 is obtained, gets out data for second transmission edge.
It is sent at second along the t2 moment, drives clock signal GSCLK to latch and send out before transmission starts and have been prepared for
Good bit1, the i.e. bit1 in the second memory module, is then selected to be output on MISO by selecting module 214 as bit1.
Meanwhile at the t2 moment, serial clock signal SCLK is sent along being detected by system clock SYSCLK, generates enabled letter
Number ENBIT, the enable signal obtain bit2 in t3 moment shifted data, send edge for third and get out data.
The t4 moment is that third was sent along the moment, according to above-mentioned beat, goes on to assembly line and sends data.First
After group data are sent, next group of data are taken out from memory and are sent, (CS is got higher into from low up to this SPI end of transmission
In vain).
Provided by the present invention for the slave device and method of serial communication, system clock SYSCLK/ string can be substantially reduced
The frequency proportions of row clock signal SCLK are improved from device data transmission rate, or are reduced from device systems clock SYSCLK
Frequency.Illustrate the beneficial effect of the present invention compared with prior art below by two examples.
Assuming that sending data transfer delay (PAD/board delay) time (T3 in Fig. 7) from equipment is 15ns (other
Related subtle secondary delay is not considered herein, can uniformly be included in this total delay), receiving end receives the transmission data from equipment
Settling time (T4 in Fig. 7) minimum require to be that 5ns as example compares two schemes:
Table two: the highest frequency for the SPI serial clock signal SCLK that clock signal of system SYSCLK can be supported when being 50MHz
As can be seen from Table II, same clock signal of system SYSCLK is 50MHz, and former scheme supports SPI serial clock letter
Number SCLK highest frequency is 6.25MHz, and this programme can support SPI serial clock signal SCLK highest frequency to 16.6MHz.
When three: SPI serial clock of table believes that SCLK is 10MHz, to the requirement of clock signal of system SYSCLK low-limit frequency
As can be seen from Table III, same SPI serial clock signal SCLK is 10MHz, and former scheme requires clock signal of system
SYSCLK low-limit frequency is 100MHz, and it is 33MHz that this programme, which requires clock signal of system SYSCLK low-limit frequency,.
By the comparison of above-mentioned two table, it should be apparent that the frequency in SPI system clock SYSCLK determines
When, the present invention in the support frequency of serial clock signal SCLK is greatly improved, therefore can be improved SPI data transmission speed
Rate；And when SPI serial clock signal SCLK frequency determines, the frequency requirement of system clock SYSCLK is substantially dropped in the present invention
It is low, therefore power consumption can be reduced.Therefore, the present invention has good effect in improve data transfer rate and reduction power consumption.
It is as described above according to the embodiment of the present invention, these embodiments details all there is no detailed descriptionthe, also not
Limiting the invention is only the specific embodiment.Obviously, as described above, can make many modifications and variations.This explanation
These embodiments are chosen and specifically described to book, is principle and practical application in order to better explain the present invention, thus belonging to making
Technical field technical staff can be used using modification of the invention and on the basis of the present invention well.The present invention is only by right
The limitation of claim and its full scope and equivalent.
Claims (17)
1. a kind of serial communication method for from equipment, it is characterised in that:
Serial clock signal is received via clock signal terminal；
Data are received via data input pin, the data include multiple continuous position data；
It is synchronous with clock signal of system, the data are shifted to obtain a data；And
It is synchronous with the serial clock signal, institute's bit data is latched, and send at least part via data output end and lock
The position data deposited,
Wherein, the serial clock signal and the clock signal of system are respectively provided with the first clock cycle and second clock week
Phase, first clock cycle are greater than the second clock period.
2. serial communication method according to claim 1, which is characterized in that in the continuous cycles of the serial clock signal
In, the selection position data of the data are shifted and latched and sent respectively.
3. serial communication method according to claim 1, which is characterized in that further include: according to the serial clock signal
Generate driving clock signal, wherein send institute's bit data at the edge of the driving clock signal.
4. serial communication method according to claim 3, which is characterized in that the driving clock signal by it is described serial when
Clock signal is obtained by gate and/or phse conversion.
5. serial communication method according to claim 1, which is characterized in that the step of being shifted to data packet
It includes:
In the first clock cycle of the serial clock signal, postpone at least one second clock period, thus acquisition and institute
State the synchronous enable signal of clock signal of system；And
According to the enable signal, the data are shifted to obtain a data.
6. serial communication method according to claim 5, which is characterized in that further include: according to the enable signal, to institute
Bit data is shifted to obtain a data, and latches a data, and send first latched
Data.
7. serial communication method according to claim 6, which is characterized in that further include: according to the serial clock signal
Obtain selection signal, for selectively by a data of the data and remaining data provide data output end into
Row is sent.
8. serial communication method according to claim 1, which is characterized in that according to the operating mode from equipment,
The rising edge or failing edge of the serial clock signal send institute's bit data.
9. serial approach according to claim 1, which is characterized in that according to the operating mode from equipment, described
The a data is sent before or after first edge of serial clock signal.
10. a kind of slave equipment for serial communication, described to receive serial clock signal via clock signal terminal from equipment, via
Data input pin receives data, and sends the data via data output end, which is characterized in that described to include: from equipment
Memory module, for storing the data；
Logic module is coupled with memory module, for synchronous with clock signal of system, is shifted the data to obtain position
Data；
First latch module is coupled with logic module, for latching a data of the data；
Second latch module is coupled with logic module, for latching remaining data of the data；
Selection signal generation module, for obtaining the selection signal synchronous with the serial clock signal；
Selecting module is coupled with the first latch module, the second latch module and selection signal generation module, for being believed according to selection
Number one of a data and remaining described data are provided to the data output end,
Wherein, the serial clock signal and the clock signal of system are respectively provided with the first clock cycle and second clock week
Phase, first clock cycle are greater than the second clock period.
11. according to claim 10 from equipment, which is characterized in that in the continuous cycles of the serial clock signal,
The logic module and second latch module are shifted and are latched and sent out to the selection position data of the data respectively
It send.
12. according to claim 10 from equipment, which is characterized in that further include:
Edge check module, for postponing at least one second clock in the first clock cycle of the serial clock signal
Period, to obtain the enable signal synchronous with the clock signal of system.
13. according to claim 10 from equipment, which is characterized in that further include:
Clock module, for obtaining driving clock signal by gate and/or phse conversion to the serial clock signal,
Wherein, the selection signal generation module generates the selection signal according to the Edge check of the driving clock signal.
14. according to claim 10 from equipment, which is characterized in that the logic module is according to the operating mode from equipment
The a data is displaced to first latch module or second latch module by selection.
15. according to claim 10 from equipment, which is characterized in that first latch module includes trigger and control
Logic, for latching and exporting a data.
16. according to claim 10 from equipment, which is characterized in that second latch module, including trigger, it is described
Driving clock signal acts on the clock end of trigger, for latching and exporting remaining data.
17. according to claim 10 from equipment, which is characterized in that the selection signal generation module include trigger and
Control logic module is used for control selections signal.
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| CN201811501631.6A CN109710556B (en) | 2018-12-10 | 2018-12-10 | Slave device and method for serial communication |
| KR1020197038605A KR102289930B1 (en) | 2018-12-10 | 2019-03-19 | Slave device and method for serial communication |
| JP2019572645A JP7212637B2 (en) | 2018-12-10 | 2019-03-19 | Slave device and method for serial communication |
| PCT/CN2019/078699 WO2020118950A1 (en) | 2018-12-10 | 2019-03-19 | Slave device for serial communications, and method |
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| CN201811501631.6A CN109710556B (en) | 2018-12-10 | 2018-12-10 | Slave device and method for serial communication |
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| JP (1) | JP7212637B2 (en) |
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| CN111061337A (en) * | 2019-12-10 | 2020-04-24 | 北京智联安科技有限公司 | Host computer receiving and transmitting interface design method |
| CN111785309A (en) * | 2020-07-01 | 2020-10-16 | 深圳市芯天下技术有限公司 | Method, circuit, storage medium and terminal for realizing non-flash memory interface circuit |
| CN112559426A (en) * | 2020-12-15 | 2021-03-26 | 广州智慧城市发展研究院 | Data transmission method, interface circuit and device |
| CN112860613A (en) * | 2021-04-06 | 2021-05-28 | 北京集创北方科技股份有限公司 | Communication system |
| CN113626355A (en) * | 2020-05-06 | 2021-11-09 | 华润微集成电路(无锡)有限公司 | Circuit structure of slave chip for realizing serial interface full duplex communication |
| CN113656340A (en) * | 2021-08-20 | 2021-11-16 | 西安易朴通讯技术有限公司 | Communication control method, system and device of I2C bus |
| CN115328845A (en) * | 2022-08-26 | 2022-11-11 | 润芯微科技(江苏)有限公司 | Method for designing four-wire serial peripheral interface communication protocol |
| CN115766332A (en) * | 2023-01-03 | 2023-03-07 | 杭州视芯科技股份有限公司 | Serial communication device, serial communication system, and serial communication method |
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| CN113407476B (en) * | 2021-06-17 | 2024-02-23 | 芯天下技术股份有限公司 | Method and device for improving data channel speed, storage medium and terminal |
| CN117251403A (en) * | 2023-11-08 | 2023-12-19 | 北京紫光芯能科技有限公司 | Communication mode configuration method and device of SPI protocol master-slave equipment |
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| CN111061337A (en) * | 2019-12-10 | 2020-04-24 | 北京智联安科技有限公司 | Host computer receiving and transmitting interface design method |
| CN113626355A (en) * | 2020-05-06 | 2021-11-09 | 华润微集成电路(无锡)有限公司 | Circuit structure of slave chip for realizing serial interface full duplex communication |
| CN113626355B (en) * | 2020-05-06 | 2023-11-14 | 华润微集成电路(无锡)有限公司 | Circuit structure of slave chip for realizing serial interface full duplex communication |
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| CN115328845B (en) * | 2022-08-26 | 2023-05-12 | 润芯微科技(江苏)有限公司 | Four-wire serial peripheral interface communication protocol design method |
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Also Published As
| Publication number | Publication date |
|---|---|
| JP7212637B2 (en) | 2023-01-25 |
| JP2021536043A (en) | 2021-12-23 |
| WO2020118950A1 (en) | 2020-06-18 |
| KR20200074917A (en) | 2020-06-25 |
| CN109710556B (en) | 2020-08-11 |
| KR102289930B1 (en) | 2021-08-17 |
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