CN111061337A

CN111061337A - Host computer receiving and transmitting interface design method

Info

Publication number: CN111061337A
Application number: CN201911259619.3A
Authority: CN
Inventors: 杨澍宁
Original assignee: Beijing Zhilianan Technology Co ltd
Current assignee: Beijing Zhilianan Technology Co ltd
Priority date: 2019-12-10
Filing date: 2019-12-10
Publication date: 2020-04-24

Abstract

The invention discloses a host interface design method, wherein the host interface comprises a clock signal end, a chip selection signal end, a host output slave input signal end and a host input slave output signal end, and comprises a data sending part, and the data sending part comprises the following processes: giving a rising edge of the clock signal end as a sending edge of data, and then inverting a clock and gating the clock; the invention can enhance the robustness of the transmitted data and add an adjustable clock edge for receiving data.

Description

Host computer receiving and transmitting interface design method

Technical Field

The invention relates to the technical field of interfaces, in particular to a structured processing method and a processing device for a referee document.

Background

Although the SPI host interface is relatively simple to implement and has a relatively high transmission rate in a general peripheral, the conventional SPI host interface is slightly insufficient in high-frequency implementation along with the requirements for improving the performance of a chip and the interface rate. Mainly due to the limitation of a digital interface, the limitation of chip interface rate and the limitation of board-level wiring in design, the clock frequency cannot be increased. Most of the existing solutions for realizing high-speed digital interfaces are to insert an adjustable delay module to perform delay compensation of received data and to make a flat clock and a data line in the integrated circuit synthesis stage.

If high-speed data transmission speed is required, high requirements on chip routing and board-level routing are required. If the delay is too large, an adjustable delay unit is needed for adjustment, the whole adjustment process is complex, and multiple selections are needed. Not only increases the power consumption of the whole chip, but also leads to the increase of the design complexity of the chip synthesis and the back end

Therefore, how to provide a host transceiver interface design method capable of solving the above problems is a problem that needs to be solved by those skilled in the art.

Disclosure of Invention

In view of the above, the present invention provides a method for designing a host transceiver interface, which can enhance the robustness of transmitting data and add an adjustable clock edge for receiving data. If design support is provided, data receiving with large delay can be supported, and all data line chips and board-level wiring are ensured to be the same in length.

In order to achieve the purpose, the invention adopts the following technical scheme:

a design method of a host interface comprises a clock signal end, a chip selection signal end, a host output slave input signal end and a host input slave output signal end, and comprises a data sending part, wherein the data sending part comprises the following processes:

and giving a rising edge of the clock signal end as a sending edge of the data, and then inverting the clock and then performing clock gating.

Preferably, the data receiving part is further included, a register is arranged at the output signal end of the machine input slave machine, and a fixed data receiving clock edge is configured through the register, so that data receiving with different delays is realized.

Preferably, the clock signal end has adjustable clock phase and adjustable polarity.

Preferably, each receive clock adjustment edge differs by half of a clock cycle

According to the technical scheme, compared with the prior art, the invention discloses and provides the host interface design method, which ensures that the surplus of the data received by the slave equipment is sufficient under a long path and high frequency;

the phase of the receiving part is adjustable, and long-delay data can be received theoretically; the design is simple, the software adjusts the sampling edge through the register, and a delay module is not needed. The software is simple to operate, the sampling phase can be adjusted at any time, and the adjustment is not needed in the test stage; meanwhile, the power consumption is optimized, and unnecessary area is reduced.

Drawings

In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the drawings used in the description of the embodiments or the prior art will be briefly described below, it is obvious that the drawings in the following description are only embodiments of the present invention, and for those skilled in the art, other drawings can be obtained according to the provided drawings without creative efforts.

FIG. 1 is a diagram illustrating a host interface transmission timing diagram according to the present invention;

FIG. 2 is a timing diagram illustrating host interface reception according to the present invention;

FIG. 3 is a timing diagram of data sampling with four adjustable phases according to the present invention.

Detailed Description

The technical solutions in the embodiments of the present invention will be clearly and completely described below with reference to the drawings in the embodiments of the present invention, and it is obvious that the described embodiments are only a part of the embodiments of the present invention, and not all of the embodiments. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present invention.

Referring to fig. 1, an embodiment of the present invention discloses a method for designing a host interface, where the host interface includes a clock signal terminal, a chip select signal terminal, a host input/slave input signal terminal, and a host input/slave output signal terminal, and is characterized by including a data sending part, where the data sending part includes the following processes:

In a specific embodiment, the data receiving part is further included, a register is arranged at the output signal end of the machine input slave machine, and a fixed data receiving clock edge is configured through the register, so that data receiving with different delays is achieved.

In a specific embodiment, the clock phase of the clock signal end is adjustable, and the polarity of the clock signal end is adjustable.

In a specific embodiment, each receive clock adjustment edge differs by half an always period.

As shown in FIG. 1 below, the timing on the bus is as shown in the figure, but the transmission clock at the host end is the inverse clock of SCLK, and the first beat of data is supposed to be sent by the falling edge of SCLK in the figure, but actually is sent by the rising edge of the inverse SCLK.

Referring to fig. 2, a SPI transfer read data process with a command is shown, with the received data sampled on the next rising clock edge after the command process.

Referring to fig. 3, four phase adjustable models are shown that are supported by design at the time of receiving data. RX _ SAM _ ADJ in the figure is the name of the register in the implementation, and the values in the figure are configuration values, and in practice more or less bits can be set as needed to implement more or less delay phase adjustment.

The embodiments in the present description are described in a progressive manner, each embodiment focuses on differences from other embodiments, and the same and similar parts among the embodiments are referred to each other. The device disclosed by the embodiment corresponds to the method disclosed by the embodiment, so that the description is simple, and the relevant points can be referred to the method part for description.

The previous description of the disclosed embodiments is provided to enable any person skilled in the art to make or use the present invention. Various modifications to these embodiments will be readily apparent to those skilled in the art, and the generic principles defined herein may be applied to other embodiments without departing from the spirit or scope of the invention. Thus, the present invention is not intended to be limited to the embodiments shown herein but is to be accorded the widest scope consistent with the principles and novel features disclosed herein.

Claims

1. A design method of a host interface comprises a clock signal end, a chip selection signal end, a host output slave input signal end and a host input slave output signal end, and is characterized by comprising a data sending part, wherein the data sending part comprises the following processes:

2. The design method of a host interface according to claim 1, further comprising a data receiving portion, wherein a register is disposed at an output signal end of the input slave, and a fixed clock edge for receiving data is configured through the register, so as to implement data receiving with different delays.

3. The method as claimed in claim 1, wherein the clock signal terminal has an adjustable clock phase and an adjustable polarity.

4. The method of claim 1, wherein each receive clock adjustment edge differs by half of a clock cycle.