CN102495581A - Expanded programmable logic controller (EPLC) output point module - Google Patents
Expanded programmable logic controller (EPLC) output point module Download PDFInfo
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- CN102495581A CN102495581A CN201110388579XA CN201110388579A CN102495581A CN 102495581 A CN102495581 A CN 102495581A CN 201110388579X A CN201110388579X A CN 201110388579XA CN 201110388579 A CN201110388579 A CN 201110388579A CN 102495581 A CN102495581 A CN 102495581A
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Abstract
The invention discloses an expanded programmable logic controller (EPLC) output point module. The EPLC output point module is a serial peripheral interface (SPI) output expanded circuit, wherein a signal input port of the SPI output expanded circuit is connected with a master-out slave-in port of an SPI module in a PLC; and a clock signal end of the SPI output expanded circuit is connected with the clock signal end of the SPI module in the PLC. The invention adopts the design scheme that an SPI bus is combined with a shifting register and the output of an embedded intelligent PLC master module is expanded. The SPI output expanded circuit is simple in design and low in cost, and an output expanded module is relatively independent, and convenient and reliable to apply. By widely applying the expansion design to an embedded intelligent PLC, the problem of insufficient output interfaces is effectively solved.
Description
Technical field
The present invention relates to a kind of Programmable Logic Controller, especially the output expansion module in the Programmable Logic Controller is specifically expanded EPLC output point digital-to-analogue piece.
Background technology
At present; Programmable Logic Controller PLC is owing to characteristics such as simple in structure, convenient programming, excellent performance and convenient in application; Especially in recent years the Application and Development of programmable logic controller and intelligent miniature device able to programme makes PLC become current purposes wide industrial controller the most.But raising along with application complexity; The application bottleneck of PLC also shows, the embedded intelligence programmable logic controller (PLC), and primary module output is counted scope generally from 16 o'clock to 60 o'clock; But a part of delivery outlet is multiplexing after control and communication interface, and what give over to output has only about 30.For the expansion that must consider greater than 30 module to export.At present, adopt the mode of multistage PLC control usually, the complexity that makes The whole control system is improved greatly, and the fluctuation of service of system.
Summary of the invention
The objective of the invention is to embedded programmable controller can be less with output interface, adopt multistage PLC to have again that complexity is high, system's problem of unstable, expansion EPLC output point digital-to-analogue piece is proposed.
Technical scheme of the present invention is:
Expansion EPLC output point digital-to-analogue piece; It is a SPI out-expander; The master of SPI module goes out from entering the mouth to link to each other in the signal input port of described SPI out-expander and the PLC controller, and the clock signal terminal of SPI out-expander links to each other with the clock signal terminal of SPI module in the PLC controller.
SPI out-expander of the present invention comprises a plurality of shift registers of serial connection successively; The master of SPI module goes out from entering the mouth to link to each other in the serial signal input end of first shift register and the PLC controller, and the serial signal output terminal of first shift register links to each other with the serial signal input end of next shift register; The signal output part of each shift register is as the delivery outlet of output module.
The shift register of SPI out-expander of the present invention is two.
The shift register of SPI out-expander of the present invention all is serial input, parallel Output Shift Register.
Beneficial effect of the present invention:
Synchronous serial output interface of the present invention is the equipment of serial datum stream immigration under the effect of synchronous clock.The characteristics of utilizing spi bus clock speed, data bit length, clock module can programme and control flexibly do not have and need carry out the addressing operation advantage.The present invention combines spi bus with shift register, the design proposal of expansion embedded intelligence programmable logic controller (PLC) primary module output.This circuit design is simple; Cost is lower, and output expansion is a relatively independent module, should use conveniently, reliable; To make this expansion design be applied to widely on the embedded intelligence programmable logic controller (PLC), efficiently solve the not enough problem of output interface.
The present invention proposes a kind of through spi bus combine with shift register 16 the tunnel output method for designing.The spi bus module is three-way to be operated under the Master mode, to HC595 the synchronous clock input is provided.In the primary module, the SPI1 of TMS470R1A288 is used for the communication between the output of primary module and expansion module, and SPI2 is used for expanding the output of primary module and counts.The signal wire SPI2 master of SPI goes out from going into (SIMO) to be used for expansion output and to count, and connects the serial input terminal of HC595.
Description of drawings
Fig. 1 is based on the Embedded PLC system chart of TMS470R1A288 microprocessor.
Fig. 2 is the circuit diagram of SPI out-expander of the present invention.
Fig. 3 is the high-level schematic functional block diagram of shift register HC595 of the present invention.
Fig. 4 is a SPI output control flow chart of the present invention.
Embodiment
Below in conjunction with accompanying drawing and embodiment the present invention is further described.
As shown in Figure 1; Expansion EPLC output point digital-to-analogue piece; It is a SPI out-expander; The master of SPI module goes out from entering the mouth to link to each other in the signal input port of described SPI out-expander and the PLC controller, and the clock signal terminal of SPI out-expander links to each other with the clock signal terminal of SPI module in the PLC controller.
SPI out-expander of the present invention comprises a plurality of shift registers (model can be HC595) of serial connection successively; The master of SPI module goes out from entering the mouth to link to each other in the serial signal input end of first shift register and the PLC controller, and the serial signal output terminal of first shift register links to each other with the serial signal input end of next shift register; The signal output part of each shift register is as the delivery outlet of output module.
The shift register of SPI out-expander of the present invention is two.
The shift register of SPI out-expander of the present invention all is serial input, parallel Output Shift Register
Out-expander is as shown in Figure 2; Two HC595 are relations of cascade; The spi bus data output signal end SPI2SIMO of TMS470R1A288 is connected to the serial data input end DS of U1, and the serial data input end Q7 ' of U1 is connected to the serial data input end DS of U2.Receive the input end of clock SH_CP of two HC595 behind the clock signal SPI2CLK process phase inverter U3 of SPI simultaneously.Packing into of signal UDTY control HC595 data, the data that are connected to U1 and the U2 simultaneously end of packing into.The another one control signal OUT_EN of TMS470R1A288, the OE that is connected to two HC595 simultaneously holds, the output of control parallel data.
Fig. 3 is a HC595 inner function module synoptic diagram; In conjunction with Fig. 2 and Fig. 3; Data output to the parallel data output terminal from SPI2SIMO can be divided into three phases: at first, can only remove the content in the shift register when serial input data SPI2SIMO of HC595 immigration shift register under the effect of shift clock SPI2CLK, register are removed end MR for low level; State that can not the control output end is moved this pin to high level through R3 resistance in the design.Secondly, behind the complete immigration shift register of 8 bit data, under the effect of UDTY signal, in the storage register of the data storage to 8 in the shift register, serial data output terminal Q7 ' output be the state of most significant digit Q7; At last, when the OE signal was effective, data outputed to 8 bit parallel data output ends.
The present invention does not relate to all identical with the prior art prior art that maybe can adopt of part and realizes.
Claims (4)
1. expand EPLC output point digital-to-analogue piece for one kind; It is characterized in that it is a SPI out-expander; The master of SPI module goes out from entering the mouth to link to each other in the signal input port of described SPI out-expander and the PLC controller, and the clock signal terminal of SPI out-expander links to each other with the clock signal terminal of SPI module in the PLC controller.
2. expansion EPLC output point digital-to-analogue piece according to claim 1; It is characterized in that described SPI out-expander comprises a plurality of shift registers of serial connection successively; The master of SPI module goes out from entering the mouth to link to each other in the serial signal input end of first shift register and the PLC controller, and the serial signal output terminal of first shift register links to each other with the serial signal input end of next shift register; The signal output part of each shift register is as the delivery outlet of output module.
3. expansion EPLC output point digital-to-analogue piece according to claim 2, the shift register that it is characterized in that described SPI out-expander is two.
4. expansion EPLC output point digital-to-analogue piece according to claim 2, the shift register that it is characterized in that described SPI out-expander all are serial input, parallel Output Shift Register.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201110388579XA CN102495581A (en) | 2011-11-30 | 2011-11-30 | Expanded programmable logic controller (EPLC) output point module |
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201110388579XA CN102495581A (en) | 2011-11-30 | 2011-11-30 | Expanded programmable logic controller (EPLC) output point module |
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| CN102495581A true CN102495581A (en) | 2012-06-13 |
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| CN201110388579XA Pending CN102495581A (en) | 2011-11-30 | 2011-11-30 | Expanded programmable logic controller (EPLC) output point module |
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Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN110456726A (en) * | 2019-07-30 | 2019-11-15 | 深圳市云林电气技术有限公司 | A kind of Interface Expanding method of programmable logic controller (PLC) and frequency converter |
| CN111061337A (en) * | 2019-12-10 | 2020-04-24 | 北京智联安科技有限公司 | Host computer receiving and transmitting interface design method |
-
2011
- 2011-11-30 CN CN201110388579XA patent/CN102495581A/en active Pending
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN110456726A (en) * | 2019-07-30 | 2019-11-15 | 深圳市云林电气技术有限公司 | A kind of Interface Expanding method of programmable logic controller (PLC) and frequency converter |
| CN111061337A (en) * | 2019-12-10 | 2020-04-24 | 北京智联安科技有限公司 | Host computer receiving and transmitting interface design method |
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Application publication date: 20120613 |