CN103488601B - A kind of clock delay, data access method, system and equipment - Google Patents
A kind of clock delay, data access method, system and equipment Download PDFInfo
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Abstract
Embodiments provide a kind of clock delay, data access method, system and equipment, main contents comprise: clock delay module receives the clock delay number bit number of main equipment, and for each bit clock time delay, to the instruction of main equipment forward delay interval, the universal input that instruction main equipment is used for the clock port in analog series external interface SPI exports GPIO port within a clock period, at the high level of half clock period of output after the low level exporting half clock period from the clock port in the SPI of equipment, due in above-mentioned time delay process, utilize the GPIO port of main equipment to simulate the clock port in SPI, achieve the clock delay of any bit number, no longer only can realize 8 bit integer clock delay doubly by the clock port in SPI to limit, therefore, meet the clock delay demand of the specific bit number from equipment.
Description
Technical field
The present invention relates to communication technical field, particularly relate to a kind of clock delay, data access method, system and equipment.
Background technology
Current mobile communication system, proposes higher requirement to the Linear Amplifer of power amplifier.Digital pre-distortion technology because its volume is little, efficiency is high, high reliability, and to linear improvement also clearly, obtains paying close attention to of industry.Digital pre-distortion (DigitalPre-Distortional, DPD) chip can provide digital pre-distortion, it provides Serial Peripheral Interface (SPI) (SerialPeripheralInterface, SPI) for the data in other device access therein shift registers, at DPD chip as during from equipment, the SPI interface on it is the special access sequential (such as: the delay operation that step-by-step is waited for) carrying out autonomous device (such as: microprocessor) from port accepts.
SPI serial communication is mainly used in the short haul connection between system chip on board, can send simultaneously and receive serial data.Four lines are needed to complete main equipment and the communication from equipment, these four lines are: the input of serial clock (CSK) line, main equipment exports (MasterInputSlaveOutput from equipment, MISO) data line, main equipment export from equipment input (MasterOutputSlaveInput, MOSI) data line, Low level effective from equipment choice (CS) line.SPI communication process is a serial-shift process on realizing, and it carries out the data transmission procedure of a byte as shown in Figure 1: the data in self shift register, by internal clocking CLK, are shifted out by MOSI signal wire by main equipment by turn; From equipment under described clock CLK effect, also the data of self shift register are moved in the shift register of main equipment by turn by MISO signal wire simultaneously.When the exchanges data of both sides' shift register is complete, one time communications completes.If need the data of the multiple byte of transmission continuously, then between every two byte datas, insert the idle waiting of a universal serial bus, the output of clock CLK as shown in Figure 2.
In the realization of above-mentioned communication process, main equipment and all there is SPI from equipment, now, when utilizing SPI to carry out data transmission, the shift register used is all in units of byte, each transmission byte and 8bit position, clock delay in reading and writing data access process also can only the integral multiple of 8bit clock delay carry out accordingly, and such as above-mentioned DPD chip is to the clock delay requirement having 4bit and 2bit in data access process, as shown in Figure 3, for DPD chip requires that main equipment reads the time diagram of data in self by spi bus, in figure 3, SPIS_MOSI represents that DPD chip is as the data receiving main equipment output from equipment, SPIS_MISO represents that DPD chip is as the data exported from equipment to main equipment, SPIS_CLK represents the clock that DPD chip receives from main equipment, can find out, DPD chip receive master transmissions read indicate (1 byte), data address (2 byte), data length (2 byte) is after totally 5 bytes, need the data (in Fig. 3 dotted-line ellipse frame) of clock delay preparation needed for main equipment of 4bit, then data are exported to main equipment by SPIS_MOSI, the clock (in Fig. 3 dotted-line ellipse frame) of last time delay 2bit, complete the data access process of a DPD chip.Fig. 4 is that DPD chip requirement main equipment is by the time diagram of spi bus to self write data.In the diagram, SPI_CS represents chip selection signal, and during low level, DPD chip is selected, and SPIS_MOSI represents that DPD chip is as the data receiving main equipment output from equipment.
Clock delay demand due to above-mentioned DPD chip is 4bit and 2bit, and the SPI clock port of main equipment only can realize the clock delay of the integral multiple of 8bit, therefore, the clock delay of above-mentioned 4bit and 2bit can not be realized, in addition, when the clock delay of other chip demands is specific bit (not being the integral multiple of 8bit), utilize the SPI of described main equipment can not meet the clock delay demand of other chips described.
Summary of the invention
Embodiments provide a kind of clock delay, data access method, system and equipment, the problem of the clock delay demand of the specific bit of chip can not be met in order to solve in prior art the SPI utilizing main equipment.
A kind of clock delay method, described method comprises:
Receive the first clock delay number N bit that main equipment sends, described N is positive integer;
Circulation performs following operation N time:
To the instruction of described main equipment forward delay interval, instruction main equipment is within a clock period, (GeneralPurposeInputOutput is exported by universal input, GPIO) port is after the low level exporting half clock period from the clock port in the SPI of equipment, export the high level of half clock period again, wherein, described GPIO port is in multiple GPIO ports of main equipment, for simulating the GPIO port of the clock port in SPI.
A method for data access, described data access method comprises:
Main equipment utilize GPIO port export read flag data, reference address data and access length data give from the MOSI port the SPI of equipment, wherein, for exporting the described GPIO port reading flag data, reference address data and access length data be: in multiple GPIO ports of main equipment, for simulating the GPIO port of the MOSI port in SPI;
After utilizing above-mentioned clock delay method to perform the clock delay of N bit to main equipment, by GPIO port to from the clock port output low level in the SPI of equipment;
The data that main equipment utilizes local GPIO port accepts to export from the MISO port the SPI of equipment, wherein, for receiving the GPIO port of the data exported from the MISO port the SPI of equipment be: in multiple GPIO ports of main equipment, for simulating the GPIO port of the MISO port of SPI;
After utilizing above-mentioned clock delay method to perform the clock delay of M-bit to main equipment, by GPIO port to from the clock port output low level in the SPI of equipment, wherein, for to the GPIO port from the clock port output low level in the SPI of equipment being: in multiple GPIO ports of main equipment, for the GPIO port of analog series external interface SPI clock port, described M, N are positive integer.
A kind of clock delay module, described clock delay module comprises: receive submodule and implementation sub-module, wherein:
Described reception submodule, for receiving the first clock delay number N bit that main equipment sends, and triggers described implementation sub-module;
Described implementation sub-module, following operation N time is performed: to the instruction of described main equipment forward delay interval for circulating, instruction main equipment is within a clock period, by GPIO port after the low level exporting half clock period from the clock port in the SPI of equipment, export the high level of half clock period again, wherein, described GPIO port is in multiple GPIO ports of main equipment, for simulating the GPIO port of the clock port in SPI.
A kind of main equipment, described main equipment comprises:
Sending module, for sending the first clock delay number N bit to clock delay module, described N is positive integer;
Time delay command receiver module, for the N bar time delay command that receive clock time delay module sends, and when receiving every bar time delay command, trigger pip output module;
Signal output module, for within a clock period, by GPIO port after the low level exporting half clock period from the clock port in the SPI of equipment, export the high level of half clock period again, wherein, described GPIO port is in multiple GPIO ports of main equipment, for simulating the GPIO port of the clock port in SPI.
A kind of clock delay system, described clock delay system comprises: main equipment, clock delay module and at least one is from equipment, wherein:
Described main equipment, for sending the first clock delay number N bit to clock delay module, the N bar time delay command that receive clock time delay module sends, and when receiving every bar time delay command, within a clock period, by local GPIO port after the low level exporting half clock period from the clock port in the SPI of equipment, export the high level of half clock period again, wherein, described GPIO port is in multiple GPIO ports of main equipment, for simulating the GPIO port of the clock port in SPI, described N is positive integer;
Described clock delay module, for when receiving the clock delay number N bit that main equipment sends, circulation performs following operation N time: to the instruction of described main equipment forward delay interval;
Described from equipment, for the low level and the high level that utilize the clock port in local SPI to receive main equipment output.
A kind of data access system, described data access system comprises: main equipment, clock delay module and at least one is from equipment, wherein:
Described main equipment, export for utilizing GPIO port and read flag data, reference address data and access length data are given from the MOSI port the SPI of equipment, send from the first clock delay number N bit needed for equipment to clock delay module, the N bar time delay command that receive clock time delay module sends, and for every bar time delay command, perform following operation: within a clock period, by GPIO port after the low level exporting half clock period from the clock port in the SPI of equipment, export the high level of half clock period again, after executing aforesaid operations N time, by GPIO port to from the clock port output low level in the SPI of equipment, utilize the data that local GPIO port accepts exports from the MISO port the SPI of equipment, send from the second clock time delay number M-bit needed for equipment to clock delay module, the M bar time delay command that receive clock time delay module sends, and after execution described operation M time, by GPIO port to from the clock port output low level in the SPI of equipment, described M, N is positive integer, wherein:
For exporting the described GPIO port reading flag data, reference address data and access length data be: in multiple GPIO ports of main equipment, for simulating the GPIO port of the MOSI port in SPI,
For receiving the GPIO port of the data exported from the MISO port the SPI of equipment be: in multiple GPIO ports of main equipment, for simulating the GPIO port of the MISO port of SPI,
For to the GPIO port of the low level and high level that export half clock period from the clock port in the SPI of equipment being: in multiple GPIO ports of main equipment, for the GPIO port of analog series external interface SPI clock port;
For to the GPIO port from the clock port output low level in the SPI of equipment being: in multiple GPIO ports of main equipment, for the GPIO port of analog series external interface SPI clock port;
Described from equipment, for receiving reading flag data, reference address data and accessing length data of main equipment output, receive high level and the low level of main equipment output, and export the local data stored according to described flag data, reference address data and the access length data read to main equipment;
Described clock delay module, for receiving the first clock delay number N bit that main equipment sends, and sends N bar time delay command to main equipment, and receives the second clock time delay number M-bit of main equipment transmission, and send M bar time delay command to main equipment.
The beneficial effect of the embodiment of the present invention comprises:
A kind of clock delay, data access method, system and equipment that the embodiment of the present invention provides, in the time delay process of main equipment, utilize the GPIO port of main equipment to simulate the clock port in SPI, the clock delay of any bit number can be realized, and no longer only can realize 8 bit integer clock delay doubly by the clock port in SPI and limit, therefore, the clock delay demand of the specific bit number from equipment is met.
Accompanying drawing explanation
Fig. 1 is main equipment and carry out the data transmission procedure schematic diagram of a byte from the respective SPI of equipment utilization in background technology;
Fig. 2 be in background technology main equipment and transmit the data of multiple byte continuously from equipment utilization SPI time main equipment SPI clock port export clocked sequential schematic diagram;
Fig. 3 is that the DPD chip in background technology requires that main equipment reads the time diagram of data in self by spi bus;
Fig. 4 is that the DPD chip in background technology requires that main equipment is by the time diagram of spi bus to self write data;
Fig. 5 is main equipment and from the annexation schematic diagram between the port of equipment in the present invention;
The process flow diagram of the clock delay method that Fig. 6 provides for the embodiment of the present invention one;
The process flow diagram of the data access method that Fig. 7 provides for the embodiment of the present invention two;
The structural representation of the clock delay module that Fig. 8 provides for the embodiment of the present invention three;
The structural representation of the main equipment that Fig. 9 provides for the embodiment of the present invention four;
The clock delay system architecture schematic diagram that Figure 10 provides for the embodiment of the present invention five;
Figure 11 is the microprocessor of the embodiment of the present invention seven carries out read access schematic flow sheet to DPD chip;
Figure 12 is the clocked sequential that in the embodiment of the present invention seven, microprocessor GPIO_CLK port exports and the schematic diagram data that the port of GPIO_MOSI exports under this clocked sequential;
Figure 13 is that in the embodiment of the present invention seven, in this read access process, microprocessor carries out the process flow schematic diagram of write access to DPD chip;
Figure 14 is the clocked sequential that in the embodiment of the present invention seven, in number of write access operations, microprocessor GPIO_CLK port exports and the schematic diagram data that the port of GPIO_MOSI exports under this clocked sequential.
Embodiment
In an embodiment of the present invention, can meet to realize main equipment there is the clock delay demand of SPI from equipment, utilize the GPIO port of main equipment to simulate the MOSI port in the clock port in SPI, the MISO port in SPI and SPI, and utilize time delay command to control in main equipment, for the GPIO port of simulating the clock port in SPI to the height of the level from the clock port in the SPI of equipment and retention time thereof, and then realize clock delay.
Above-mentioned main equipment and from the annexation between the port of equipment as shown in Figure 5, in the GPIO port of wherein main equipment,
Be used for the clock port of simulating in SPI GPIO port (representing with GPIO_CLK in Figure 5) be connected from the clock port in the SPI of equipment (representing with SPIS_CLK in Figure 5);
The GPIO port (representing with GPIO_MOSI in Figure 5) of the MOSI port be used in simulation SPI is connected with from the MOSI port (representing with SPIS_MOSI in Figure 5) in the SPI of equipment;
The GPIO port (representing with GPIO_MISO in Figure 5) of the MISO port be used in simulation SPI is connected with from the MOSI port (representing with SPIS_MOSI in Figure 5) in the SPI of equipment;
In addition, in Fig. 5, chip selection signal (CS) port of main equipment is connected (representing with SPI_CS Fig. 5) from equipment choice port with from the Low level effective in the SPI of equipment, the chip selection signal of main equipment controls whether this selected from equipment, main equipment, by chip selection signal, can be connected from equipment with multiple.
Below in conjunction with embodiment, the embodiment of clock delay, data access method, system and equipment that the embodiment of the present invention provides is described in detail.
Embodiment one
As shown in Figure 6, the process flow diagram of a kind of clock delay method that the embodiment of the present invention one provides, comprises the following steps:
Step 101: receive the first clock delay number N bit (bit) that main equipment sends, described N is positive integer.
Described main equipment is microcontroller or microprocessor.
The first clock delay number that described main equipment sends is that main equipment is determined from the clock delay demand of equipment according to coupled.
Preferably, when described main equipment with multiple be connected from equipment time, main equipment, for each clock delay demand from equipment, determines that this is from the first clock delay number needed for equipment.
Step 102: the counting in local counter is initialized as 0.
Step 103: judge whether the counting in counter is less than N, if the determination result is YES, then performs step 104; If judged result is no, then terminate.
Step 104: to the instruction of described main equipment forward delay interval, instruction main equipment, within a clock period, after exporting the low level of half clock period, then exports the high level of half clock period by GPIO_CLK port to the SPIS_CLK port from equipment.
Main equipment is after executing above-mentioned steps 104, namely the time delay of a clock period has been carried out, due under normal conditions, data be main equipment and from equipment export and receive data synchronous clock effect carry out, when rising edge or the negative edge of synchronous clock, data are exported by GPIO_MOSI port, SPIS_MISO port, GPIO_MISO port, SPIS_MOSI port receives data, the data volume of 1bit can be exported in the clock period, therefore, delay clock time delay number Nbit, is time delay N number of clock period.
Above-mentioned steps 104 also can have been come by following two steps:
The first step: to transmission first time delay command of described main equipment, instruction main equipment passes through GPIO_CLK port to the SPIS_CLK port output low level from equipment, and keeps half clock period of this low level;
Second step: at the end of the low level of described half clock period, sends the second time delay command to described main equipment, and instruction main equipment exports high level by GPIO_CLK port to the SPIS_CLK port from equipment, and keeps half clock period of this high level.
Step 105: the counting in local counter is added 1, and jumps to step 103.
Preferably, in step 103, if judged result is no, performs and send the 3rd time delay command to described main equipment, instruction main equipment by operation from GPIO_CLK port to the SPIS_CLK port output low level from equipment after terminate again.
It is above-mentioned that to send the 3rd time delay command to described main equipment be to meet the needs transmitted from the data of the SPI of equipment, because when transmitting the data of multiple byte, need the idle waiting inserting a universal serial bus between every two byte datas, and after carrying out clock delay, main equipment and carry out data transmission between equipment, in order to carry out data transmission accurately, after clock delay, keep the low level of certain time length, realize the idle waiting of a universal serial bus.
When carrying out above-mentioned clock delay, main equipment can not export data to from equipment; Also can export data by local GPIO_MOSI port to the SPI_MOSI port from equipment, but now from equipment because need to carry out clock delay, after the data receiving main equipment transmission, these data can be abandoned.
Preferably, after considering that main equipment executes the clock delay of above-mentioned N bit according to time delay command, from equipment to main equipment after the data of input needed for main equipment, also need from equipment the clock delay carrying out Mbit, therefore, described method also comprises:
Receive the second clock time delay number M-bit that main equipment sends, described M is positive integer;
The second clock time delay number that described main equipment sends is that main equipment is determined from the clock delay demand of equipment according to coupled.
Preferably, when described main equipment with multiple be connected from equipment time, main equipment, for each clock delay demand from equipment, determines that this is from the second clock time delay number needed for equipment.
Perform above-mentioned steps 102-step 105, it should be noted that, now step 103 should be: judge whether the counting in counter is less than M, if the determination result is YES, then performs step 104; If judged result is no, then terminate.
In embodiments of the invention one, make use of the GPIO port of main equipment to simulate SPI clock port, MISO port and MOSI port, communicate with from each corresponding port in the SPI of equipment, achieve from the clock delay needed for equipment by above-mentioned clock delay method, when carrying out data transmission, the GPIO port of simulation SPI clock port is utilized to produce synchronous clock, under the effect of synchronous clock, carry out data transmission with from equipment, and then complete main equipment and from the communication between equipment.
Embodiment two
As shown in Figure 7, the data access method of a kind of clock delay method based on embodiment one that the embodiment of the present invention two provides, described data access method comprises the following steps:
Step 201: main equipment utilizes local GPIO_MOSI port to export and reads flag data, reference address data and access length data to the SPI_MOSI port from equipment.
Concrete, the transmission of data (reading flag data and reference address data described in comprising) is all carry out transmitting under the effect of the synchronous clock exported at the GPIO_CLK port of main equipment, is described below to the data transmission procedure of every 8bit.
The SPI_MOSI port of this locality and SPI_MISO port initialization are low level by the first step: main equipment initialization, are low level by the GPIO_CLK port initialization of this locality.
Second step: the end level of half clock period that main equipment utilizes local GPIO_CLK port to export is to the SPIS_CLK port from equipment, recycle this GPIO_CLK port and export the high level of half clock period to the SPIS_CLK port from equipment, now namely achieve the synchronous clock of a bit (bit), at synchronous clock by low level in the rising edge process of high level, the data that main equipment utilizes SPI_MOSI port to export 1bit are to from the SPI_MOSI port of equipment.
3rd step: repeat above-mentioned second step 7 times.
Namely completed the data transmission of 8bit by the above-mentioned first step to the 3rd step, after transmission, insert the idle waiting of a universal serial bus, main equipment can continue through the above-mentioned first step to the 3rd step to the data from device transmission 8bit.
Step 202: main equipment is when receiving N bar time delay command, for every bar time delay command, within a clock period, after exporting the low level of half clock period by GPIO_CLK to the SPIS_CLK port from equipment, then export the high level of half clock period.
Step 203: main equipment utilizes local GPIO_CLK port output low level.
Step 204: the data that main equipment utilizes local GPIO_MISO port accepts to export from the SPI_MISO port of equipment.
In this step 204, the transmitting procedure of data is identical with the transmitting procedure of data in step 201, repeats no more here.
Step 205: main equipment is when receiving M bar time delay command, for every bar time delay command, within a clock period, after exporting the low level of half clock period by GPIO_CLK to the SPIS_CLK port from equipment, then export the high level of half clock period.
Step 206: main equipment utilizes local GPIO_CLK port output low level.
Embodiment three
As shown in Figure 8, be the structural representation of the clock delay module that the embodiment of the present invention three provides, comprise: receive submodule 11 and implementation sub-module 12, wherein:
Described reception submodule 11, for receiving the first clock delay number Nbit that main equipment sends, and triggers described implementation sub-module 12;
Described implementation sub-module 12, following operation N time is performed: to the instruction of described main equipment forward delay interval for circulating, instruction main equipment is within a clock period, after exporting the low level of half clock period by GPIO_CLK port to the SPIS_CLK port from equipment, then export the high level of half clock period.
Preferably, described reception submodule 11, also for after input the data needed for main equipment from equipment to main equipment, receive the second clock time delay number M-bit that main equipment sends, and trigger described implementation sub-module 12, described M is positive integer;
Described implementation sub-module 12, also performs described operation M time for circulating.
Embodiment four
As shown in Figure 9, be the structural representation of the main equipment 200 that the embodiment of the present invention four provides, comprise: sending module 21, time delay command receiver module 22 and signal output module 23, wherein:
Sending module 21, for sending the first clock delay number N bit to clock delay module, described N is positive integer;
Time delay command receiver module 22, for the N bar time delay command that receive clock time delay module sends, and when receiving every bar time delay command, trigger pip output module 23;
Signal output module 23, within a clock period, after exporting the low level of half clock period, then exports the high level of half clock period by GPIO_CLK port to the SPIS_CLK port from equipment.
Preferably, described sending module 21, also for receiving after the data of equipment input at main equipment, send second clock time delay number M-bit to clock delay module, described M is positive integer;
Described time delay command receiver module 22, also for the M bar time delay command that receive clock time delay module sends, and when receiving every bar time delay command, trigger pip output module 23.
Embodiment five
As shown in Figure 10, be the clock delay system architecture schematic diagram that the embodiment of the present invention five provides, described clock delay system comprises: main equipment 31, clock delay module 32 and at least one is from equipment 33, wherein:
Described main equipment 31, for sending the first clock delay number N bit to clock delay module, the N bar time delay command that receive clock time delay module sends, and when receiving every bar time delay command, within a clock period, after exporting the low level of half clock period by GPIO_CLK port to the SPI_CLK port from equipment, then export the high level of half clock period, described N is positive integer;
Described clock delay module 32, for when receiving the clock delay number N bit that main equipment sends, sends N bar time delay command to described main equipment;
Described from equipment 33, the low level exported for utilizing local SPIS_CLK port accepts main equipment and high level.
Described main equipment 31 comes by exporting effective chip selection signal to each from equipment 33 and should communicate from equipment.
Embodiment six
For a kind of data access system that the embodiment of the present invention six provides, its structural representation is identical with the structural representation in embodiment five, as shown in Figure 10, described data access system comprises: main equipment 31, clock delay module 32 and at least one is from equipment 33, wherein:
Described main equipment 31, export for utilizing GPIO_MOSI port and read flag data, reference address data and access length data give the SPI_MOSI port from equipment, send from the first clock delay number N bit needed for equipment to clock delay module 32, the N bar time delay command that receive clock time delay module 32 sends, and for every bar time delay command, perform following operation: within a clock period, after exporting the low level of half clock period by GPIO_CLK port to the SPIS_CLK port from equipment, export the high level of half clock period again, after executing aforesaid operations N time, by GPIO_CLK port to the SPIS_CLK output low level from equipment, and after the data utilizing local GPIO_MISO port accepts to export from the SPI_MISO port of equipment, send from the second clock time delay number M-bit needed for equipment to clock delay module 32, the M bar time delay command that receive clock time delay module sends, and after execution described operation M time, by GPIO_CLK port to the SPIS_CLK output low level from equipment, described M, N is positive integer,
Described from equipment 32, for receiving reading flag data, reference address data and accessing length data of main equipment output, receive high level and the low level of main equipment output, and export the local data stored according to described flag data, reference address data and the access length data read to main equipment;
Described clock delay module 33, for receiving the first clock delay number N bit that main equipment 31 sends, and send N bar time delay command to main equipment 31, and receive the second clock time delay number M-bit of main equipment 31 transmission, and send M bar time delay command to main equipment 31.
Embodiment seven
The embodiment of the present invention seven is described in detail the process that the data access system of the embodiment of the present invention six carries out data access by the implementation procedure of microprocessor access DPD chip.
As shown in figure 11, for the microprocessor of the embodiment of the present invention seven to carry out the schematic flow sheet of read access to DPD chip, comprise the following steps:
Step 301: microprocessor obtains the spin lock for DPD chip, prepares to carry out data access to DPD chip.
Described spin lock proposes a kind of lock mechanism for realizing protection shared resource; when there being multi-microprocessor all can conduct interviews to described DPD chip; each microprocessor is before accessing described DPD chip; obtain spin lock, can effectively prevent multiple processor to conduct interviews operation to this DPD chip simultaneously.
Step 302: microprocessor, by the SPI_CS output low level of local chip selection signal to DPD chip, represents and chooses this DPD chip.
Step 303: microprocessor to be exported successively to the SPI_MOSI port of DPD chip by local GPIO_MOSI port and reads flag byte, reference address high byte, reference address low byte, visit data length high byte and visit data length low byte.
Step 304: microprocessor sends the first clock delay number 4bit to clock delay module, microprocessor utilizes the clock delay method in embodiment one to carry out the clock delay of 4bit.
Step 305:DPD chip utilizes local SPI_MISO port to export data to the GPIO_MISO port of microprocessor.
In this step 305, DPD chip comes to export data to the GPIO_MISO port of microprocessor according to the reference address byte received and visit data byte.
Step 306: microprocessor sends second clock time delay number 2bit to clock delay module, and microprocessor utilizes the clock delay method in embodiment one to carry out the clock delay of 2bit.
Step 307: microprocessor is by the SPI_CS output high level of local chip selection signal to DPD chip, and to remove choosing this chip, and release is for the spin lock of this DPD chip.
Step 308: the data that microprocessor reads to upper layer transport.
By above-mentioned steps 301-step 308, microprocessor completes the read access to DPD chip.The data of the clocked sequential exported by microprocessor GPIO_CLK port in this read access process of oscilloscope display and the port output of GPIO_MOSI under this clocked sequential as shown in figure 12.
In fig. 12, represent with GPIO_CLK the clocked sequential that GPIO_CLK port exports, represent with GPIO_MOSI the data that GPIO_MOSI port exports.
In Figure 12, data are in the output of the rising edge of clock, the data exporting a byte (8bit) need 8 clock period, number from left to right, under the effect of the clock of front 5 bytes, the data exported for the GPIO port of simulating SPIMOSI are: 00000001, 00110000, 00100000, 00000000, 00000001, these data transformations are that 16 systems are 0X01, 0X30, 0X20, 0X00, 0X02, according to above-mentioned steps 303, described 0X01 is for reading flag byte, described 0X30, 0X20 is respectively reference address high byte, reference address low byte, described 0X00, 0X02 is visit data length high byte, visit data length low byte, show that the data length that the data in DPD chip read by microprocessor is that 0X0002(is converted to 10 systems and is 2 bytes).
After the clock of described 5 bytes, the clock delay having 4bit can be seen, there is the clock of 2 bytes afterwards, in the clock of described 2 bytes, the SPI_MISO port of DPD chip exports the data of 2 bytes to the GPIO_MISO port of microprocessor, after the clock of described 2 bytes, the clock delay having 2bit can be seen, in contrast background technology, Fig. 2 reads the time diagram of DPD chip by spi bus, the clock delay method that the embodiment of the present invention provides, clock delay module and main equipment achieve DPD chip demand to the clock delay of 4bit and 2bit in data access process.
Below in conjunction with Figure 13, microprocessor is described the process that DPD chip carries out write access.
As shown in figure 13, for the microprocessor of the embodiment of the present invention seven to carry out the schematic flow sheet of write access to DPD chip, comprise the following steps:
Step 401: microprocessor receives the data that need send to DPD chip from upper strata.
Step 402: microprocessor obtains the spin lock for described DPD chip, prepares to carry out data access to described DPD chip.
Step 403: microprocessor, by the SPI_CS output low level of local chip selection signal to DPD chip, represents and chooses this DPD chip.
Step 404: microprocessor to be exported successively to the SPI_MOSI port of DPD chip by the port of local GPIO_MOSI and writes flag byte, reference address low byte, visit data length high byte, visit data length low byte.
Step 405: microprocessor exports its data from upper strata received by the port of local GPIO_MOSI to the SPI_MOSI port of DPD chip.
Step 406: microprocessor is by the SPI_CS output high level of local chip selection signal to DPD chip, and to remove choosing this chip, and release is for the spin lock of this DPD chip.
Because DPD chip carries out in the process of write access to microprocessor to it, there is no clock delay demand, therefore clock delay is not carried out in above-mentioned steps 401-step 406, if other chips are in write access process, have clock latency requirement, then clock delay method, clock delay module and the main equipment that the embodiment of the present invention also can be utilized to provide carry out number of write access operations to other chips described.
Above-mentioned steps 401-step 406 completes microprocessor and carries out number of write access operations to DPD chip, and the data of the clocked sequential exported by microprocessor GPIO_CLK port in the described number of write access operations of oscilloscope display and GPIO_MOSI port output under this clocked sequential as shown in figure 14.
In fig. 14, number from left to right, under the effect of the clock of front 5 bytes, the data exported for the GPIO port of simulating SPIMOSI in microprocessor are: 00000000, 01000000, 00001000, 00000000, 00000010, these data transformations are that 16 systems are 0X00, 0X40, 0X08, 0X00, 0X02, according to above-mentioned steps 403, described 0X00 is for reading flag byte, described 0X40, 0X08 is respectively reference address high byte, reference address low byte, described 0X00, 0X02 is visit data length high byte, visit data length low byte, show that the data length that the data in DPD chip read by microprocessor is that 0X0002(is converted to 10 systems and is 2 bytes).6th byte and the 7th byte are the data of 2 bytes exported to the SPI_MOSI port of DPD for the GPIO port of simulating SPIMOSI in microprocessor, and be respectively: 0X34,0X12, the number forming 16 systems is 0X1234.
For under built-in Linux operating system, the implementation procedure (also namely based on the functional block diagram of Fig. 5, the accessing time sequence of Fig. 3 and Fig. 4 be realized) of microprocessor access DPD chip be realized, the bsp driver of abstract hardware under needing the system that realizes.Can by the clock delay method software simulating of the embodiment of the present invention one, and as a clock delay interface of driver, be combined DPD chip drives to call upper layer software (applications) read-write system and do the operation of concrete hardware logic and five interface: init_dpd () providing, realize opening DPD chip; Exit_dpd (), realizes closing DPD chip; Write_dpd (), writes data in DPD chip; Read_dpd (), reads data from DPD chip; Cfg_dpd (), configuration DPD chip generates the driving to microprocessor.Drive after realizing, upper level applications is called read apparatus calling interface and is write system call interfaces, and bottom layer driving just realizes corresponding sequential on microprocessor pin.
Obviously, those skilled in the art can carry out various change and modification to the present invention and not depart from the spirit and scope of the present invention.Like this, if these amendments of the present invention and modification belong within the scope of the claims in the present invention and equivalent technologies thereof, then the present invention is also intended to comprise these change and modification.
Claims (2)
1. a method for data access, the clock delay being applied to needs is not the chip of the integral multiple of 8bit, and it is characterized in that, described data access method comprises:
Main equipment utilize GPIO port export read flag data, reference address data and access length data give from the MOSI port the SPI of equipment, wherein, for exporting the described GPIO port reading flag data, reference address data and access length data be: in multiple GPIO ports of main equipment, for simulating the GPIO port of the MOSI port in SPI;
After utilizing clock delay method to perform the clock delay of N bit to main equipment, by GPIO port to from the clock port output low level in the SPI of equipment;
The data that main equipment utilizes local GPIO port accepts to export from the MISO port the SPI of equipment, wherein, for receiving the GPIO port of the data exported from the MISO port the SPI of equipment be: in multiple GPIO ports of main equipment, for simulating the GPIO port of the MISO port of SPI;
After utilizing following clock delay method to perform the clock delay of M-bit to main equipment, by GPIO port to from the clock port output low level in the SPI of equipment, wherein, for to the GPIO port from the clock port output low level in the SPI of equipment being: in multiple GPIO ports of main equipment, for the GPIO port of analog series external interface SPI clock port, described M, N are positive integer;
Described clock delay method is:
Receive the first clock delay number N bit that main equipment sends, described N is positive integer;
Circulation performs following operation N time:
To the instruction of described main equipment forward delay interval, instruction main equipment is within a clock period, by GPIO port after the low level exporting half clock period from the clock port in the SPI of equipment, export the high level of half clock period again, wherein, described GPIO port is in multiple GPIO ports of main equipment, for simulating the GPIO port of the clock port in SPI.
2. a data access system, the clock delay being applied to needs is not the chip of the integral multiple of 8bit, and it is characterized in that, described data access system comprises: main equipment, clock delay module and at least one is from equipment, wherein:
Described main equipment, export for utilizing GPIO port and read flag data, reference address data and access length data are given from the MOSI port the SPI of equipment, send from the first clock delay number N bit needed for equipment to clock delay module, the N bar time delay command that receive clock time delay module sends, and for every bar time delay command, perform following operation: within a clock period, by GPIO port after the low level exporting half clock period from the clock port in the SPI of equipment, export the high level of half clock period again, after executing aforesaid operations N time, by GPIO port to from the clock port output low level in the SPI of equipment, utilize the data that local GPIO port accepts exports from the MISO port the SPI of equipment, send from the second clock time delay number M-bit needed for equipment to clock delay module, the M bar time delay command that receive clock time delay module sends, and after execution described operation M time, by GPIO port to from the clock port output low level in the SPI of equipment, described M, N is positive integer, wherein:
For exporting the described GPIO port reading flag data, reference address data and access length data be: in multiple GPIO ports of main equipment, for simulating the GPIO port of the MOSI port in SPI,
For receiving the GPIO port of the data exported from the MISO port the SPI of equipment be: in multiple GPIO ports of main equipment, for simulating the GPIO port of the MISO port of SPI,
For to the GPIO port of the low level and high level that export half clock period from the clock port in the SPI of equipment being: in multiple GPIO ports of main equipment, for the GPIO port of analog series external interface SPI clock port;
For to the GPIO port from the clock port output low level in the SPI of equipment being: in multiple GPIO ports of main equipment, for the GPIO port of analog series external interface SPI clock port;
Described from equipment, for receiving reading flag data, reference address data and accessing length data of main equipment output, receive high level and the low level of main equipment output, and export the local data stored according to described flag data, reference address data and the access length data read to main equipment;
Described clock delay module, for receiving the first clock delay number N bit that main equipment sends, and sends N bar time delay command to main equipment, and receives the second clock time delay number M-bit of main equipment transmission, and send M bar time delay command to main equipment.
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| CN110798269B (en) * | 2019-09-24 | 2021-12-10 | 深圳震有科技股份有限公司 | Method and system for realizing PCM slave function based on GPIO |
| CN111611186B (en) * | 2020-05-26 | 2021-11-02 | 大唐微电子技术有限公司 | Transmission control method and device in embedded chip |
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| CN102012877A (en) * | 2010-11-26 | 2011-04-13 | 成都智科通信技术有限公司 | Method for expanding embedded processor GPIO by using CPLD |
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